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Nellyw888
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VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb

Reinforcement Learning
Transformers
Safetensors
qwen2
text-generation
verilog
reasoning
rtl
text-generation-inference
Model card Files
xet
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Nellyw888 commited on
Commit
58652c2
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verified ·
1 Parent(s): 1b8aad7

Training in progress, step 430

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Files changed (3) hide show
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  2. model-00002-of-00002.safetensors +1 -1
  3. training_args.bin +1 -1
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