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Организация и йерархия на кеш паметта. Повишаване на производителността на кеш-памет. страницата се нуждае от дописване/преглеждане Разяснения Производителността на компютрите се намалява поради голямата разлика в бързодействието на ОП и ЦП. За сравнение на един такт на процесора при изпълнение на дадена инструкция е нужна една наносекунда, докато около 50 наносекунди са нужни за достъп до паметта. Терминът „идеална памет” означава такава памет, която в момента на подаване на адреса на исканата клетка от паметта, да бъде върната информацията от тази клетка. Но това е трудно осъществимо. За да се помогне работата на ЦП и да се намали до някаква степен това време на изчакване което се получава, навлиза идеята за направата на по-малки и по-бързи(RAM) памети с по-малко забавяне наречени кеш памети. Тези памети са реализирани на основата на предположенията, че ако на процесора му е трябвала някаква инструкция, то в скоро време тя отново ще му потрябва в близкото бъдеще и второ, че ако на процесора му е трябвала някоя инструкция, то тези около нея ще му потрябват в близкото бъдеще. Тази нова, малка и бърза памет се вкарва във Фон Ноймановата архитектура между ЦП и ОП. Кешът се състои от регистрова памет(RF) и/или статична памет(SRAM), а ОП се състои от динамична памет (DRAM). При поискването на информация от ЦП се проверява първо дали тази информация я има в кеш, ако я има то имаме hit. Това означава, че ще имаме достъп до данните с малко закъснение. Ако не може да се намери търсената информация в кеш паметта, то имаме miss. Това означава, че ще трвбва да се обърнем към DRAM и да търсим информацията там, което от своя страна означава, че ще имаме голямо закъснение при получаването на данните. Структура на кеш паметта Кеш паметта е съставена от множества. Всяко множество е съставено от равен брой фреймове(line), които пък от своя страна са съставени от идентификатор(address tag), блок(data block) и два бита за състояние. address tag – а е част от адреса в ОП и еднозначно идентифицира разположението на данните в ОП. Фреймовете в кеша са разбъркани от големи и малки адреси. Ако трябва да сложим копие на някакви данни от ОП (блок) в кеша има три начина това да стане в зависимост от организацията на кеш паметта: При пълно асоциативен кеш (fully associative) – имаме едно множество от всички фреймове и там може да се сложи на произволно място. При двупътно асоциативен кеш (set associative) – тогава имаме няколко индексирани множества с по равен брой фреймове където по индексът на множеството се ориентираме къде трябва да се постави новия блок. Кеш с директно изобразяване (direct map) – тук отново имаме едно множество от индексирани фреймове и блокът се поставя на точно определеното място. Четенето съответно при трите вида кеш става по следния начин: Fully Associative Set Associative Direct Map Време за достъп Средно време за достъп в паметта = времето при hit + Колко средно се получава miss * Глоба (времето необходимо да се извлече информацията от ОП и да се запише в кеш) Average memory access time = Hit time + Miss rate x Miss penalty To improve performance: - reduce the hit time - reduce the miss rate (e.g., larger cache) - reduce the miss penalty (e.g., L2 cache) Причини за miss при кеш паметта - задължителен miss при първо обръщение към този адрес – студен старт - поради капацитета – капацитета се е запълнил и е изхвърлил данни и тях ги няма, но на нас ни трябват - по каква схема се разполагат блоковете и кои линии се изхвърлят при запълване на капацитета Различните варианти на кеш паметта имат различни преимущества и недостатъци. Ако размерът на кеш паметта е по – голям, това ще намали miss-овете но ще увеличи времето за hit. Ако има по-голяма асоциативност отново може да се увеличи времето за hit. По-големият размер на блока също увеличава miss-овете. Replacement Policy Кой фрейм трябва да се извърли? - Random - Least Recently Used (LRU) - LRU cache state must be updated on every access - true implementation only feasible for small sets (2-way) - pseudo-LRU binary tree often used for 4-8 way - First In, First Out (FIFO) a.k.a. Round-Robin - used in highly associative caches - Not Least Recently Used (NLRU) - FIFO with exception for most recently used block or blocks - One-bit LRU - Each way represented by a bit. Set on use, replace first unused. Кеш с много нива Кеш паметта се реализира вече на 3 нива(L1, L2, L3) L1 – най-малка като обем и най-бърза L2 - малко по-голяма и по–бавна L3 – най-голяма и най-бавна И трите са много по-бързи за достъп от ОП и трите съдържат само дубликати. Ако един адрес е представен в L1, то той е представен по същия начин в L2 и L3 (съответно в ОП), но ако е в L3, например, то не е задължително той да е представен в L1 и L2. Колкото е по-малка по обем една памет, толкова е по-бърза. Затова кеша се разделя на три нива и L1 се разделя на памет за инструкции (IS – instruction сегмент) и памет за данни (DS – data segment )( при Intel – 8 KB за данни и 8 KB за инструкции). Когато L2 е вътре в процесора (заедно с L1), се повишава скоростта на работа. Идеята е скоростта на работа с данните между регистрите и L1 да е почти същата като тази на процесора ( с % по-малка ). Преди освен с бързината е имало проблем и с обема на паметта – не е стигала. Например в IBM 360 адресната решетка е била 24 бита, тоест адресируеми са били 16МВ. На практика обаче размерът на реалната памет е бил 1МВ. Затова е започнала да се използва виртуална памет, като паметта 1МВ е в ОП, а останалите се записват на диск. Там са всички байтове и при 32 разрядна решетка там има 4GB. Реалната оперативна памет днес се прави така, че да достига 4 GB. Преди виртуалното пространство е било около 10 пъти повече от ОП. Сега се различават до един-два пъти. В ОП реално има дубликати на нещата от диска. Политики на писане в кеш Q1: Дали новата стойност ще се разпространи до паметта? Записва се през всички нива на кеша и се записва в основната памет. write through – проникващо през кешовете - бавно стават операциите за запис, независимо от производителността на кеша - ще се увеличава честотата на писане + при четене всички нива на кеша ще имат новата стойност Не. write back – новата стойност не стига до основната памет, а се записва само в най-близкото ниво на кеша. Заради възможността от поява на желание за промяна на паметта в бъдеще се налага добавянето на още един бит за състояние в кеша (dirty bit). когато се запише нещо в линията този бит става 1, 0 – чиста линия. + наличието на този бит улеснява replacement-а, щом е чист, значи копието му съвпада с копието в другите нива - консистентността се нарушава + ще се намали трафика от големия кеш до ОП (по голям кеш =повече трафик) Q2: Какво става когато процесора подаде данни, но адреса го няма в кеша?(имаме miss) 1. алокира се кеш блока – блокът в които трябва да се пише се изтегля от паметта и се слага в L1 кеша . Намества се в кеша без да се чете от него и след това се пише (write back) Пише се директно в ОП. Не се чете в блока, не се губи време в четене. Кеш паметта е направена за бързо четене. Паралелно със сравняването на тага се изтегля и информацията и при получаването и не се знае от кой фрейм е получена тя. Това не може да се приложи при писането в кеша. При писане първо се намира тага който ни е необходим за писане и после се пише. По този начин записът става много бавен. Решението е създаването на write buffer който се слага на входа на кеша (вътре в него). Там стоят и адреса и данните и процесорът счита, че данните са записани. При постъпване на данни за запис в кеша първо се проверява дали има hit и ако има тогава се записват в буфера и когато им доиде реда се записват в кеша. Обработката на буфера става паралелно с четенето от кеша. Надеждата при създаването на кеш паметите е, че ще има по-често четене отколкото писане. Буферът не може да бъде по-голям за да не се задържа информацията в него и процесорът ще чака докато се освободи място в него. Буферът ускорява производителността на кеша. Ако се сложи и един write-back буфер на края на кеша се ускорява и replacement-а. Има някви методи за ускоряване които няма да пиша щото стана много цялата глупост и ако успея да напиша и половината евалата!
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Microprocessors and systems architecture in today's processors To read from or write to a location in main memory, it is necessary to know its address. For this reason each memory system is connected to the address bus of the system. Furthermore, the memory system is connected to the data bus so that data (information) that can be transferred between the processor and the main memory or other devices. The system memory is also connected to the control bus. This is necessary because various control signals must be sent in memory to indicate the type of operation the processor wants to perform. For example, if the processor wants to perform a read operation, it sends a signal to indicate that the memory is a read operation and a write operation is not. If on the other hand wants the processor to perform a write operation then sends another signal to the memory. The figure shows how a processor, system memory, and input / output modules can be interconnected via the bus system In (System BUS). The processor can do two basic things to main memory. Figure 1 Can write one byte at a given position in the main memory. In this case the preceding word is lost and the new word will be stored for future use. It can read a word from a given location in memory. The processor receives the byte Data stored in this location. The content of this position does not change. Most processors can read (and write) more than one byte per time. Processors having external channels 32 bits of data can read (or write) 32 bits (4 byte) at the same time, and processors that have external data bus 64-bit can read (and write) 64 bits (8 byte) at the same time. To pass a memory location, the address of the desired position in the memory is placed on the address bus. The address is decoded by decoder system memory, and the decoder selects the memory location. The processor must be show the system's memory what kind of operation he wants to perform (read or write data). Figure 2 This is achieved by means the control channel. Although this the channel contains multiple lines, only a few lines needed for the write operation or reading. The exact number and type control lines required depend on the processor type and memory used. An important line of control is the line read / write. The processor uses it so it can send a signal indicating system memory if the function wants to perform is recording or reading. When the processor wants to save (write) data in memory, sets the line read / write to logic 0 (e.g. OV). This activates the isolators (three state buffers) between the processor and memory, and data is transferred from the selected data lines memory location. When the processor wants to read information from the memory, sets the line write/read R/W in logic 1 (to a high positive voltage voltage, e.g., + 3.3V). This voltage activates the buffers (three state buffers) between the processor and memory during so that the flow of data is from the memory to the data lines, and therefore the processor. For example, if the processor wants to access memory location whose address is 14, place this number to the address lines in binary form (eg 00001110. The processor also enables the line W/R, to show that the memory is a write operation, not a read operation. The address is decoded after the memory decoder (special electronic circuit) and select the seted memory location. In this case, the memory location 14. THREE-STATE OUTPUT CIRCUITS The function of a circuit with three-state output shown in Figure 1. A three-state output can be in one of 3 states. The output can be in a logic state "0" or logic "1" state, or may be in a high impedance state, in this case the output is disconnected from the inlet. The circuit is similar to a conventional logic gate YES and has a third terminal usually called the enable input. When the enable input is a logic 1 (e.g. +5V), the three-state gate behaves as a YES gate. Figure 1 That is, a logic 1 inlet gives a logic 1 at its output, and a logic 0 to the input of giving a logic 0 at its output. When the energizing voltage put in logic 0, the output of the gate is disconnected from the input, and output swing, that is to a high impedance state. The operation of a three-state gate can be represented by a switch as shown in Figure 2, which is controlled by the input actuator. When the voltage at the input trigger is logic "1", switch is closed and the input is connected to the output as shown in the figure, and when the voltage at the input actuation is logic "0", the switch is on and the output is disconnected from the inlet as shown in Figure 2D. Figure 2 The three-state gate that shown in Figure 1 uses an input trigger is activated by a high voltage (logic 1), that acts as a gateway YES. There are also gates were activated when a logic 0 (Low voltage) applied to the enable input, in this case the gate behaves like a normal circuit YES. There are also NOR gates with three-state output, these circuits can be actuated either by a logic 3, or by a logic 1, applicable at the input actuator, as shown in Figure 3. Figure 3 The binary number corresponding to data obtained from memory and is stored in the memory location indicated by the address bus. The processor can use the same technique to save (write) more data on different memory locations. To read or recover information (data) from a memory location, the processor using a similar process. For example, to provide data from main memory, the microprocessor initially puts the memory address (The address of the memory location containing the desired data or commands) to terminals address. The microprocessor activates then the control line R/W to update the memory that this is a read operation and not a write operation. The memory gets the address from the address lines and the address decoder of memory (address decoder) decodes the address. The memory control circuit copies (places) then the contents of the memory location at the terminals of data memory, which are connected to the data bus lines, and activates a signal to inform the microprocessor that has places the requested data on data lines. When the microprocessor detects this signal receives the word. That saves the data in one of its internal data registers. Figure 3a, 3b If its only one command, then the microprocessor executes, and the data are used accordingly. If more information is required, then the processor (the CPU) reads them with similar manner from memory. Similar way the CPU can read or write the information on input/output devices. These devices have a number of registers, and each register has a unique address in the system memory. Therefore, the CPU communicates to the main memory and input/output devices using the system bus. Note that some address lines can maybe activated when the control low voltage (eg. 0V) is applied to the line, and other lines control activated when applying the high voltage (eg. +5V). signals (lines) that are activated when applied a low voltage, called active low signals. The signal lines are activated when a voltage applied is a high level (eg. +5V) called active high line. For example, suppose that a line connecting the CPU with memory (READ for example, in the line above her name. In this case the line is activated when the voltage level at this line is low (eg, 0V), and the line is disabled when the voltage level at line become high (eg. +5V). If the name has not taken line above the name, then when the voltage level at line be high (eg. +5V) the signal becomes active and action representing performed, and when the voltage level line become low (eg. 0V) the signal is deactivated, and action representing not place. Depends the designer of the processor if a signal is active low or active high. DATA BUS LINE CONNECTION In a computer system various devices are connected to a single channel. Because only one device can transfer information through the channel at a given time, three-state logic circuits used to interconnect devices on the bus. The three-state gates (or isolaters) are used to disconnect all devices from the bus, except for those who communicate at this time. When a device does not send or receive information, can be disconnected from the bus by simply disabling the isolator. Every device connected to the bus has usually two three-state buffers in each I/O line. When the device is sent information, the buffer output is activated and the input buffer is turned off (inactivated) as shown in Figure 3a. When the device receives this information, the input buffer is activated and the output buffer is turned off (inactivated) as shown in Figure 3b. Besides isolators (driver and receiver buffers) semiconductor manufacturers also produce (transceivers) which are buffers that can either send or receive data from the channel. Figure 4 illustrates how used three-state gates or buffers to interconnect two devices on one bidirectional channel. To simplify the diagram we use only two lines. If the enable input E1 (enable input) is at logic 1, and the enable-input E2 is at logic 0, then the driver of the device A is connected to the lines of the bus, and receivers of the device is disconnected from the bus lines , while the drivers of the device B is disconnected from the bus and receivers are connected to the bus. So, the device A sends information (data) to device B. Figure 4 CACHE MEMORY When the processor needs an instruction or data from main memory and places them in one of the lists. Because the data (bytes) that can be temporarily stored at lists of microprocessors, are limited, there is a continuous exchange of information (data, instructions) between registers and external memory (main memory or RAM). The data transfer between the main memory and the processor registers is a relatively slow process, if compared to the speed with which information can be transferred into the processor. So most computers delayed not only by the speed of the processor, but the relatively long delay from the data transfer between main memory and processor. It is obvious that for a system to be quick, the processor must have access to various data needs direct to the internal registers. But, it is not possible to save the entire program or data that are required to run a program on data registers because they are very few, therefore, this information must be transferred from the slower memory to registers. Figure 5 One of the best ways to bypass the problem resulting from the relatively slow data transfer between main memory and internal registers of the processor is to use a small amount of fast intermediate memory, so that the overall memory system to acquire, nearly the speed of a small fast memory (ie registers) and the large capacity of the main memory in a relatively low price. The buffer memory is called cache or Cache. This type of memory is composed of ultra-fast read/write SRAM (Static RAM chips) chip. The Cache memory is located between the main memory and the processor as shown in Figure 5. The cache memory can be accessed much faster than the CPU. The memory chip SRAM is more expensive than the memory chip DRAM. The price difference occurs because the manufacture of the DRAM using less transistors for each bit of the memory of the SRAM. The cache memory contains information (ie data and commands) frequently accessed by the processor. So when the processor needs this information, read directly from the cache memory rather than the slower main memory. Because the access time (ie the time required to read out data from the memory to the processor) of cache memory is smaller than the access time of main memory, the processor operates faster since it is not necessary to read the data from the relatively slow main memory (DRAM). Figure 6 Therefore, a cache memory is a special quick subsystem memory in a PC in which has stored data (or commands) that is very likely the processor to need soon. If the processor finds the information it needs to cache memory (this is called a cache "hit"), then you get this information from the cache memory rather than the main memory. If the processor does not find the information you need to cache memory (this is called a cache "miss"), then the processor will take the data from the main memory. But, the recovery of data from main memory requires a lot of time (many clock cycles) while retrieving data from the cache memory is a very fast process. The cache memory can provide data to the processor faster than the main memory so a cache memory can improve computer performance significantly. The cache memory is divided into two categories: Level One cache, and the Level Two cache. Level one cache memory (Level One), and level two cache memory (Level Two). The level one cache memory usually runs at the clock speed of the processor, so the processor can obtain the information you need quickly. The cache memory is divided usually into two sections, one for data and one for instructions. Note that the level one cache memory can provide data and commands faster than the CPU level two cache memory. Level one cache memory is also called "original memory cache or primary cache", or simply L1 cache memory. The level two cache memory is used as a medium between the very fast Level One cache and the slower chip DRAM main memory of the computer. Figure 7 Before the Pentium II or Athlon, the cache memory level Two was manufactured with standards SRAM (L2) and was located in the motherboard and it was running with the same speed of the system bus (system bus). This is a disadvantage because the system bus speed is much slower than the speed a processor. To overcome the disadvantage, the Pentium Pro, Pentium II, the new generations of processors have their own level two cache memory. To Pentium II and the more recent processors have loaded the level two cache memory on the same chip with the processor. If the processor finds the information needed to cache memory is recalled (this is called "cache hit"), then it will take the information from the cache memory. Otherwise, a cache miss has occurred and the processor must receive information either from another level of cache memory (L2), or to recover from the main memory of the system (RAM). Both level one and level two cache can provide data and commands to the prossesor much faster than to take them from the main memory (RAM). That is a way of improving the performance of the computer. CACHE MEMORY CONTROLLER A cache memory needs a controller. This is a circuit whose function is to determine whether the information should be accessed by the processor, is in the cache memory or will be transferred from the main memory (Figure 6). Because in a memory system with a cache memory, the information is transferred from the controller cache memory into the blocks, on the exquisite cache controller the main memory is divided into blocks or rows of information. The block is the unit of data exchanged between cache memory and main memory. Each block of main memory usually consists of 2, 4, or 8 words and is numbered (has a tag) with a block address as shown in Figure 7. For example, if we assume that the main memory is equal to 16 Mbyte and each block of main memory consists of 4 words (8 bit), and each word consists of 4 bytes (ie, 4x8 bit = 32 bit), then one block in main memory comprised of 16 bytes (4 wordsx4 = 16 bytes), therefore the main memory is divided into 16 Mbytes/16bytes = 1000000 block. When the processor needs to read data or instructions from memory, places the address of the main memory into the address bus. The high cache memory read the address and then checks to see if the data or commands are in the cache memory (SRAM). If this happens then we have a cache-hit, and the data or commands are immediately transferred to the processor from the memory cache. In this way, the time consuming process of transferring data or commands from the main memory is avoided. Due to the high speed cache memory, processors with higher clock speeds can access the data they need without any wait cycles. If on the other hand the data needed by the processor are not in the cache memory, then we have a cache miss. In this case the controller cache memory reads data word or instructions required by the processor along with several contiguous words from memory and sends it to the cache memory, and then the desired word is transferred to the processor. The number of words (or bytes) transferred from the main memory during this process is called a line (line or block). If the processor mast have access to this data again, it will immediately read them from the cache memory. The operation of the cache between the processor and the main memory is illustrated in Figure 8. If the processor wants to write data to the main memory, the cache memory controller checks to see if the data are already in the cache memory, then the controller carries then to the main memory. If, on the other hand, the data is not in cache memory, the proccesor transfers data with a high speed in cache memory, and later writes at the main RAM memory. WRITE-THROUGH AND WRITE-BACK An important feature of any memory hierarchy is how it handles the data records (writes). When the processor, transfer, or update the information in cachce memory, cache memory controller sends this information to the main memory, using either the Write through or Write back-BACK technique. The write-through technique is simple. Whenever the processor wants to write data to the cache memory, the controller will send or renew these data also located in the main memory. That processor writes data simultaneously in the cache memory and main memory. This is the best technique but also the slowest. The write-back technique allows the processor to transfer the information or renew the changed block data or instruction cache in memory but does not convey information simultaneously in main memory. The controller's cache memory will write the changed or new data in the main memory later. A write-back cache speeds up the write process, but requires a more complex fine. INPUT/OUTPUT (I/O) An input device is a device that introduces information (data) in the system to process. An example of an input device is the keyboard, when you press a key data is entered into the system. Another input device is a sensor (sensor), for example, a pressure sensor or temperature sensor. An output device is a device that receives information from the system. Few examples of devices that export are printers and monitors. Tutorials Calculators