<p>In the paper <a href="http://research.microsoft.com/en-us/um/people/lamport/pubs/interprocess.pdf" rel="nofollow">"On Interprocess Communication"</a>, the author Leslie Lamport have developed a formalism for interprocess communication via shared registers based on lower-level, <em>non-atomic</em> operations and have proposed the definitions of <em>safe, regular, and atomic</em> registers. <a href="http://research.microsoft.com/en-us/um/people/lamport/pubs/pubs.html#interprocess" rel="nofollow">Also Lamport's description for the "interprocess" publication.</a></p>

<p>For <em>safe</em> registers, a read that overlaps a write operation is allowed to return <em>any</em> one of the possible values of the register.</p>

<p>My problem is </p>

<blockquote>
  <p>How practically relevant is this specification of <em>safe</em> registers?</p>
</blockquote>

<p>Particularly, is it possible for a read of an <em>actual register/memory unit</em> in a multiprocessor computer to return an arbitrary value when it is concurrent with a write?</p>

<p>What about going to a lower level such as circuits/flip-flop?</p>

<p>In what sense, does a <em>safe</em> register exist?</p>

CC BY-SA 3.0
2015-01-08T19:03:14.373Z
See http://en.wikipedia.org/wiki/Cache_coherence — you do not read & write the same **physical** register simultaneously, however, you may read & write cached copies of the value in different local caches, and then it is up to the **cache coherence protocol** what might happen. Usually, the low-level details are not visible to the programmer; the contract between the programmer and the underlying system is the **memory model**, http://en.wikipedia.org/wiki/Memory_model_(programming)
Jukka Suomela
CC BY-SA 3.0
2015-01-08T19:12:31.043Z
Oh, I just realised that there are certain systems in which simultaneous read & write on a physical level might be indeed possible: dual-port RAM. For example, this might be relevant: http://www.microsemi.com/document-portal/doc_view/129836-ac374-simultaneous-read-write-operations-in-dual-port-sram-for-flash-based-csocs-and-fpgas-app-note
Jukka Suomela
CC BY-SA 3.0
2015-01-10T11:08:14.723Z
@JukkaSuomela Thanks. The "dual-port RAM" article is helpful. Would you mind converting your comment to an answer?
hengxin
CC BY-SA 3.0
2015-01-10T14:09:36.463Z
Let's wait and see if someone who knows a bit more about the topic writes an answer. :)  I think you might also consider asking at http://electronics.stackexchange.com/ where there are people who actually understand the low-level hardware details much better.
Jukka Suomela
<dc.distributed-comp><concurrency><ar.hardware-architecture>
In what sense, does a safe register exist?
hengxin
# In what sense, does a safe register exist?

(Asked by: username_0 on 2015-01-07)

In the paper ["On Interprocess Communication"](http://research.microsoft.com/en-us/um/people/lamport/pubs/interprocess.pdf), the author Leslie Lamport have developed a formalism for interprocess communication via shared registers based on lower-level, *non-atomic* operations and have proposed the definitions of *safe, regular, and atomic* registers. [Also Lamport's description for the "interprocess" publication.](http://research.microsoft.com/en-us/um/people/lamport/pubs/pubs.html#interprocess)

For *safe* registers, a read that overlaps a write operation is allowed to return *any* one of the possible values of the register.

My problem is

> How practically relevant is this specification of *safe* registers?

Particularly, is it possible for a read of an *actual register/memory unit* in a multiprocessor computer to return an arbitrary value when it is concurrent with a write?

What about going to a lower level such as circuits/flip-flop?

In what sense, does a *safe* register exist?

**Tags:** dc.distributed-comp, concurrency, ar.hardware-architecture

> **Comments:**
> **username_1**: See http://en.wikipedia.org/wiki/Cache_coherence — you do not read & write the same **physical** register simultaneously, however, you may read & write cached copies of the value in different local caches, and then it is up to the **cache coherence protocol** what might happen. Usually, the low-level details are not visible to the programmer; the contract between the programmer and the underlying system is the **memory model**, http://en.wikipedia.org/wiki/Memory_model_(programming)  
> **username_1**: Oh, I just realised that there are certain systems in which simultaneous read & write on a physical level might be indeed possible: dual-port RAM. For example, this might be relevant: http://www.microsemi.com/document-portal/doc_view/129836-ac374-simultaneous-read-write-operations-in-dual-port-sram-for-flash-based-csocs-and-fpgas-app-note  
> **username_0**: @JukkaSuomela Thanks. The "dual-port RAM" article is helpful. Would you mind converting your comment to an answer?  
> **username_1**: Let's wait and see if someone who knows a bit more about the topic writes an answer. :)  I think you might also consider asking at http://electronics.stackexchange.com/ where there are people who actually understand the low-level hardware details much better.  

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## 0 answers

