<p>While I understand the question you are trying to ask, I find the presentation sub-optimal. This might just be me, but I find the tone of the question slightly condescending. I'm sure this is not what you meant to convey -- I'm just telling you how it comes across to me.</p>

<p>Anyway, I can try to answer some of your questions. Let me start with a pair of misconceptions:</p>

<ul>
<li><strong>Misconception 1</strong>: PARITY not in AC0 says that "it is not possible to build polynomial-size constant-depth circuits to compute parity in the real world." </li>
</ul>

<p>This is not true at all. The result claims exactly what it does: It is not possible to compute parity using a constant-depth polynomial-size circuit composed only of (and this is the important part) NOT gates, and unbounded fan-in AND and OR gates.</p>

<ul>
<li><strong>Misconception 2</strong>: It is believed that just because AND, OR and NOT gates form a complete basis, AC0 is robust under changing these gates to any other gates.</li>
</ul>

<p>As you pointed out, this is not true. If you used unbounded fan-in XOR gates, then obviously PARITY has a depth-1 circuit. The class which has unbounded fan-in XOR gates in addition to the usual NOT, AND and OR gates is called AC<sup>0</sup>[2]. AC0 is not robust under changing the gate set (unlike some other classes like NC0, where any complete basis will do the job). For example if we allow the MAJORITY gate in addition to the AND, OR and NOT gates, we get a class called TC0, which is much bigger than AC0.</p>

<p>An interesting question which arises, and which you have explicitly asked, is the following:</p>

<blockquote>
  <p>"The definition of AC0, with the restriction of using only AND ∧, OR ∨, and NOT ¬ gates, seems arbitrary. What is the fundamental basis for this restriction?"</p>
</blockquote>

<p>This is a nice question. It also has a good answer. I don't think I can answer this satisfactorily myself, so I'll let someone else do it. I'll try answering it myself if no one else chooses to do so. But note that the answer is not  "AC0 models real world circuits."</p>

<p>This question also immediately leads to the question "Why is this result interesting?" I'm not sure if this is what you meant to ask, but some good answers are given on the <a href="http://blog.computationalcomplexity.org/2008/03/why-is-parity-not-in-ac0-important.html">complexity theory blog</a>.</p>

<p>So if we look at your your claimed "subtle and unstated" assumptions, you'll find that most of them are very clearly stated. For example, the fact that you can only use AND, OR and NOT is in the <em>definition</em> of AC0. I can't imagine anything being stated more explicitly than that!</p>

<h2>Answer to revision 4</h2>

<p>In revision 4 it seems like the question really is "Why don't we allow AC0 to have NAND gates also (because those are the gates used in real life by EE folks)?"</p>

<p>The answer is simple. Adding unbounded fan-in NAND gates to AC0 does not make AC0 more powerful. So you can interpret PARITY not in AC0 as saying that "PARITY cannot be computed by constant-depth circuits with unbounded fan-in AND, OR, NAND and NOT gates."</p>

<p>An unbounded fan-in NAND gate is just an unbounded fan-in AND gate with the output negated. So every NAND gate can be replaced by an AND gate and a NOT gate. Then, all the NOT gates can be pushed down to the inputs using standard techniques. At the end, the depth remains the same, and the size might increase by something like a factor of 4. </p>

CC BY-SA 2.5
2010-12-07T02:26:11.777Z
But note that the answer is not "AC0 models real world circuits." Indeed. Just because $AC^0$ is defined in terms of logic gates doesn't mean we have to think of it so. If you prefer, we can think of $AC^0$ as the class of languages recognized by poly-length programs over finite, aperiodic monoids.
mhum
CC BY-SA 2.5
2010-12-08T01:24:26.547Z
I think this question is closely related to the issue being discussed

http://cstheory.stackexchange.com/questions/1794/circuit-lower-bounds-over-arbitrary-sets-of-gates
gabgoh
CC BY-SA 2.5
2010-12-07T01:01:57.460Z
2010-12-07T23:27:08.427Z
2010-12-07T23:27:08.427Z
Robin Kothari
<blockquote>
  <p>Below, a link is given to a six transistor, THREE  input XOR (i.e., PARITY) gate. This means it is trivially possible to physically build "at least" THREE input with constant depth of one  XOR / PARITY gates.</p>
</blockquote>

<p>Unless I am completely misinterpreting these sentences, I think there may be some confusion in how "constant depth" is defined. First off, in circuit complexity, we deal in families of circuits, one circuit for each input size. So, when we say we can compute PARITY in some circuit model, what we mean is we have a sequence of circuits $C_1, C_2, C_3, \ldots$ such that $C_k$ computes the parity function on $k$ boolean inputs. The idea of constant depth is that there exists some $D$ such that each circuit $C_k$ has depth at most $D$ <b>for all</b> $k$, no matter how large. Similarly, "poly-size" implies that there is some polynomial $p(x)$ such that each circuit $C_k$ has no more than $p(k)$ gates.</p>

<p>Exhibiting an instance of a circuit that computes the parity function on 3 inputs does not really say anything about "constant depth" as it is defined in complexity theory. "Constant depth" is a property of the asymptotic behavior of your circuit family.</p>

CC BY-SA 2.5
2010-12-07T09:14:49.197Z
2010-12-07T09:14:49.197Z
mhum
<p><strong>Regarding the choice of basis:</strong> all finite bases are (polynomially) equivalent. That means that if $C$ is a circuit over a <em>finite</em> base $B$ and $B'$ is any complete basis, then there is an equivalent circuit $C'$ over $B'$ of size at most $\alpha_1 |C|^{\alpha_2}$, where $\alpha_1,\alpha_2$ depend only on $B,B'$. This is proved for example in <a href="http://www.cs.toronto.edu/~sacook/homepage/reckhow_thesis.pdf" rel="noreferrer">Reckhow's thesis</a> (Section 5.3), though the result itself is due to <a href="http://citeseer.uark.edu:8080/citeseerx/showciting;jsessionid=F593B995B9338A1124209542D7EE5B48?cid=1249521" rel="noreferrer">Spira</a>. What this means informally is that when we're doing circuit complexity, we don't really care whether the basis is NAND or AND, OR, NOT. (That's because in circuit complexity we often don't care about polynomial factors.) NAND was chosen because that's what can be implemented in hardware. AND, OR, NOT were chosen for historical reasons: that's what was used in logic (along with similar bases such as NOT, IMPLIES for which $\alpha_2 = 1$ both ways). Circuits with unlimited arity PARITY gates don't fall under this formalism, since the basis is infinite.</p>

<p><strong>Regarding the importance of Håstad's result:</strong> This was the first non-trivial bound in circuit complexity. It is still one of the best bounds known for non-monotone models, along with the Razborov&ndash;Smolensky methods, and Razborov's slightly superlinear lower bound for switching networks. All other bounds rely on restrictions of the model, usually monotonicity.</p>

<p>Parity is computed in real life in an iterative fashion, using tables or simply by "deep" circuits (this concept is of course hard to define exactly, since constant depth is an asymptotic notion). That's a different model. Circuits considered in circuit complexity are good enough for the P vs. NP question (or rather, P/poly vs. NP). At the time, it seems that people thought that the methods developed for small complexity classes would scale up to polysize circuits, but this hope hasn't materialized. Nowadays it is a less presumptuous specialist area.</p>

CC BY-SA 3.0
2014-01-24T21:35:23.843Z
2014-01-24T21:35:23.843Z
Yuval Filmus
<p><strong>attempt to restate question</strong></p>

<p>From the feedback, it is obvious that I have not clearly articulated my point.  Also, it is not my intent to be condescending.  I very clearly have a notion / idea / question that is contrary to the doctrine subscribed to by the readers of this question.  I am genuinely trying to reconcile something that is so incongruent to me that it is difficult to even put in to words.  I literally do no know how to express it in a succinct simple paragraph.</p>

<p>This may not help, but let me try an analogy.  Let's say that hypothetically there are two different groups, the first one is called 'EE' and the second is called 'CS'.  Both groups consider themselves to be authoritative experts in Boolean circuits.  As unlikely as it may seem, for some reason the two groups do not speak to each other or read the others results, despite their common interest.  There are some differences:</p>

<p>The "EE" group builds boolean circuits.  They literally turn theoretical ideas into to something physical.  Physical goods mean there are very tangible, objectively unambiguous costs involved.</p>

<p>The "CS" group does not (usually) build circuits.  Because nothing is physically produced, the physical resource costs tend to be dramatically lower for the "CS" group, almost to the point where it is "effectively zero."</p>

<p>Although both groups consider themselves boolean circuit experts, there is a curious discrepancy in the choice for their respective "boolean basis."  As long as the boolean basis is "complete", that basis can be provably shown to be able to serve as the building block for every possible <em>n</em>-arity boolean function.  What is important is that there are a couple of "natural" boolean basis choices, but as long as the boolean basis choice is "complete", the different "natural" choices can all implement all <em>n</em>-arity boolean functions- that is to say, one choice is not "more powerful" or "more expressive" than the other.  The "complete" property means that they are "logically identical", despite the seemingly paradoxical fact that they are composed of distinctly different primitives.</p>

<p>Almost since the dawn of building boolean circuits, the "EE" group has consistently and invariably chosen "NAND" (which, to an EE person, there is no need to state the obvious "and NOR" qualification).  For the EE group, the reason for this choice is so obvious to them it literally does not occur to them that anyone would make a different choice.</p>

<p>The "CS" group, on the other hand, has chosen "AND, OR, NOT".  This choice can express exactly the same <em>n</em>-arity circuits as "NAND", and vice versa, due to the fact that both are a "complete" boolean basis.</p>

<p>The fact that the "EE" group has very real physical costs, which tends to translate directly in to money, means that even though there is no logical difference between a boolean basis choice, if one of the many available choices in any way what-so-ever has a monetary advantage, that's the one that is picked.</p>

<p>Money has a tendency to place a <strong>simply enormous pressure</strong> to ensure that whatever "choice" is made is the optimal one.  It is not hyperbole to say that <em>billions</em> of dollars riding on the decision.  It is difficult to put in to words how much pressure and effort goes in to this.  There is simply no detail, and the pedantic consequences of every possible permutation of those details, behind choosing "NAND" that is not completely understood and justified.</p>

<p>In my original question, I point out two examples of this: The Apollo Guidance Computer, which made landing on the moon possible, and the Cray-1, the legendary computer by Seymour Cray.</p>

<p>If you are unaware of the details, it is difficult to express what it means to "Space Certify" a design.  I think it's safe to say that Seymour Cray is widely recognized to be genuinely gifted at "building circuits".  Although it may seem "insignificant", the decision to use 4 / 5 input NAND gates exclusively in the design of the Cray 1 was one of the contributing factors behind its legendary performance.</p>

<p>Again, I sincerely apologize for the lengthy exposition, but based on the responses I can't help but feel that at least some of you do not fully appreciate the significance of the fact that</p>

<ul>
<li>There is another group of people who consider themselves "boolean circuit experts".</li>
<li>This other group of "boolean circuit experts" has consistently, universally, and invariably chosen "NAND" as their boolean basis, despite the fact that there are multiple, equivalent options.</li>
<li>As near as I can tell, the "CS" group began developing their boolean circuit models (i.e., $AC^0$, $NC$, etc) right around the time the first P vs. NP descriptions and theories began to take form in the 1970's.</li>
<li>This means that the "EE" boolean circuit theories predate the "CS" boolean circuit theories by decades.</li>
<li>Yet, despite a rich, mature, and well understood body of work that was available, the "CS" group made the curious decision to go with "AND, OR, NOT".</li>
<li>At some point, someone in the "CS" group "discovered" that PARITY was not in $AC^0$, and published a peer reviewed paper.</li>
</ul>

<p>I fully appreciate that all of this sounds completely condescending.  This is genuinely not my intent.  It's difficult for me to gauge this audience to determine at what point providing the justification for my point turns in to sounding like a condescending ass.</p>

<p>It is fairly obvious that I felt a need to justify my simple question:</p>

<blockquote>
  <p>The well known result regarding <em>parity</em> and $AC^0$, also taken from from <a href="http://en.wikipedia.org/wiki/Circuit_complexity" rel="nofollow">Wikipedia</a>:</p>
  
  <blockquote>
    <p>The Boolean function PARITY, which is 1 if and only if the sum of its input bits is odd, does not lie in $AC^0$.</p>
  </blockquote>
  
  <p>My question is: "Why is this considered to be a fundamentally important result?"</p>
</blockquote>

<p>Now, I admit, this is an extremely odd question.  The reason why I asked it is because, at least for me, I find this detail <em><strong>extremely interesting</strong></em>:</p>

<ul>
<li>The people who actually build circuits use NAND as their boolean basis.</li>
<li>The "CS" theory people choose "AND, OR, NOT".</li>
</ul>

<p>For me, this stands out like a neon red light. Even if you think I'm completely wrong, I at least hope that you recognize "I wasn't aware of any of this, but now that you mention, it does seem a little bit weird." Experience tells me this usually goes one of two ways:</p>

<ol>
<li>You completely and thoroughly understand the consequences of breaking with the established tradition.</li>
<li>You're ignorant of the nuances.</li>
</ol>

<p>People in the first category are easy to spot.  For me, it is simply inconceivable that anyone who truly understood the ramifications of deciding to go with "AND, OR, NOT" instead of "NAND" did not spend 5 minutes doodling out the maximal worst case for 3, 4, etc bits.  At which point, you sort of chuckle and say "Man, this is going to totally suck in the XOR corner case."</p>

<p>People in the second category are harder to predict.  In the worst case, they spend no effort researching the issue.  This is unfortunate because they tend to end up "rediscovering" things that have been known for over 100 years.</p>

<p>This is why I am asking the seemingly "obvious" question.  I find it almost impossible to believe that someone in group 1, who truly understood the issues involved, would deliberately and knowingly break with the fully vetted NAND boolean basis without understanding all of the consequences of doing so.  It literally takes just a few minutes to work through some corner cases.  I simply can not understand how someone who studied the issue would not know that:</p>

<ul>
<li>The XOR / PARITY corner case is going to be comically bad.</li>
<li>Your practical experience tells you that this "effect" does not accurately reflect how XOR / PARITY circuits are built anyways, so it is completely benign and safe to ignore.</li>
</ul>

<p>On the other hand, there is a peer reviewed, published paper that says "The PARITY / XOR corner case sucks when using 'AND, OR, NOT'."  This is a contradiction.  How do you completely understand the consequences of breaking with the established norm, and then be "surprised" by something that was hopefully blatantly obvious the moment it was decided to go with "AND, OR, NOT"?</p>

<p>I can't help be get the feeling that this whole "2 input NAND" thing is genuinely novel to you.  You do understand what it means, right?  The <a href="http://en.wikipedia.org/wiki/NAND_logic" rel="nofollow">2 input NAND gate</a> is <a href="http://en.wikipedia.org/wiki/Functional_completeness" rel="nofollow">functionally complete</a> for the entire boolean domain.  If you can prove that this simple, 2 input NAND gate has some property, you can prove it for the entire boolean domain.  Hypothetically you could do something like this:</p>

<ul>
<li>$\{AC^0\} ∖ \{NAND\} = ∅$
</li>
<li>$\{AC^*\} ∖ \{NAND\} = ∅$
</li>
<li>$\{ACC^0\} ∖ \{NAND\} = ∅$
</li>
<li>$\{ACC^*\} ∖ \{NAND\} = ∅$
</li>
<li>$\{TC^0\} ∖ \{NAND\} = ∅$
</li>
<li>$\{TC^*\} ∖ \{NAND\} = ∅$
</li>
</ul>

<p>Seems too good to be true, doesn't it?  Why stop there!</p>

<ul>
<li>$\{TM\} ∖ \{NAND\} = ∅$
</li>
</ul>

<p>Cool!  But, what does that mean for...</p>

<ul>
<li>$\{NTM\} ∖ \{NAND\} = ∅$
</li>
</ul>

<p>.... we should be careful, we might rip a whole in the universe... </p>

<ul>
<li>$\{P\} ∖ \{NAND\} = ∅$
</li>
</ul>

<p>Whoa!  Is there anything NAND can't do!?  Thankfully, it's not that simple, because if it were I'm pretty sure someone would have pointed it out before now.</p>

<p>I am <em><strong>deeply curious</strong></em> if anyone can point me to a published proof that details why it can't be done, though.  ;)</p>

<p><strong>original question follows</strong></p>

<p>A definition of $AC^0$ <em>circuit complexity</em> taken from <a href="http://en.wikipedia.org/wiki/Circuit_complexity" rel="nofollow">Wikipedia</a>:</p>

<blockquote>
  <p>A Boolean circuit with <em>n</em> input bits is a directed acyclic graph in which every node (usually called gates in this context) is either an input node of in-degree 0 labeled by one of the <em>n</em> input bits, an AND gate, an OR or a NOT gate.</p>
</blockquote>

<p>The well known result regarding <em>parity</em> and $AC^0$, also taken from from <a href="http://en.wikipedia.org/wiki/Circuit_complexity" rel="nofollow">Wikipedia</a>:</p>

<blockquote>
  <p>The Boolean function PARITY, which is 1 if and only if the sum of its input bits is odd, does not lie in $AC^0$.</p>
</blockquote>

<p>My question is: "Why is this considered to be a fundamentally important result?"</p>

<p><strong>edit:</strong> From the comments, it is clear that the fundamental point / question is not being understood.  Specifically: It is <em><strong>obviously</strong></em> possible to physically build <em>bounded depth</em> and <em>polynomial size</em> PARITY circuits- you need only open up a book on constructing CMOS circuits and look at how a XOR gate is <em>physically</em> constructed.</p>

<p>The fact that you can not build <em>n</em> input <em>constant depth</em> XOR / PARITY gates using <em><strong>only</strong></em> AND and OR gates is not doubted or disputed- that's obvious.  Below, a link is given to a <em><strong>six</strong></em> transistor, <em><strong>THREE</strong></em> input XOR (i.e., PARITY) gate.  This means it is trivially possible to physically build "at least" THREE input with <em>constant depth</em> of <em>one</em> XOR / PARITY gates.</p>

<p>The primary point is: The fact that you can not build <em>constant depth</em> XOR / PARITY gates using AND and OR gates <em><strong>DOES NOT</strong></em> imply that <em>constant depth</em> XOR / PARITY gates can not be built.  The $AC^0$ PARITY proof proves something much weaker: that <em>constant depth</em> XOR / PARITY gates can not be built using just AND and OR gates.  This is <em><strong>not</strong></em> the same thing as proving that <em>constant depth</em> XOR / PARITY gates can not be built, and it is a mistake to assume that they are.</p>

<p>If this distinction is still not clear to you, consider that a proof that <em>constant depth</em> XOR / PARITY gates can not be built using a <em>constant depth</em> / <em>polynomial size</em> number of <em><strong>transistors</strong></em> would not only be a far stronger result, but can also be trivially falsified because such constructions do, in fact, exist (links provided below).</p>

<p><strong>end edit</strong></p>

<p>If this question seems <em>naive</em> to you, then a better question to you might be "The definition of $AC^0$, with the restriction of using only AND ∧, OR ∨, and NOT ¬ gates, seems arbitrary.  What is the fundamental basis for this restriction?"</p>

<p>If your first impulse to "What is the fundamental basis for this restriction?" is that "The primitives AND ∧, OR ∨, and NOT ¬ are functionally complete for all of the boolean nullinary, unary, and binary operators" then: <em><strong>beware of the flaming arrows.</strong></em></p>

<p>As an example of why the $AC^0$ restriction of AND ∧, OR ∨, and NOT ¬ is arbitrary, consider that:</p>

<ul>
<li>The <a href="http://en.wikipedia.org/w/index.php?title=Apollo_Guidance_Computer" rel="nofollow">Apollo Guidance Computer</a>, circa 1966, was built using approximately 4,100 3-input NOR ⊽ gates.</li>
<li>The <a href="http://en.wikipedia.org/wiki/Cray-1" rel="nofollow">Cray-1</a>, circa 1976, was built using approximately 200,000 4 and 5 input NAND ⊼ gates.</li>
</ul>

<p>For circuit builders, the decision to use either NAND ⊼ or NOR ⊽ gates as the <em><strong>only</strong></em> primitive is so blatantly obvious that it doesn't need mentioning.  If this does not seem blatantly obvious to you, then: <em>beware of the <strong>incoming</strong> flaming arrows.</em></p>

<p>Restricting ourselves to 2 input AND ∧, 2 input OR ∨, and 1 input NOT ¬ gates it is possible to create:</p>

<ul>
<li>A 2 input XOR ⊻ gate using two AND ∧, one OR ∨, and one NOT ¬ gate.</li>
</ul>

<p>Restricting ourselves to just a single, 2 input NAND ⊼ gate, it is possible to create:</p>

<ul>
<li>A 2 input AND ∧ gate using two NAND ⊼ gates.</li>
<li>A 2 input OR ∨ gate using three NAND ⊼ gates.</li>
<li>A 1 input NOT ¬ gate using one NAND ⊼ gate.</li>
</ul>

<p>Using the above, it is possible to restate $AC^0$ in terms of NAND ⊼ gates and furthermore calculate that it takes a total of seven NAND ⊼ gates using the original two AND ∧, one OR ∨, and one NOT ¬ gate definition for XOR ⊻.  However, it is also possible to build a XOR ⊻ gate using less NAND ⊼ gates:</p>

<ul>
<li>A 2 input XOR ⊻ gate using four NAND ⊼ gates.</li>
</ul>

<p>The seven NAND ⊼ gate and four NAND ⊼ gate constructions for a 2 input XOR ⊻ gate are "logically identical", producing exactly the same output for the same inputs.  The fact that we were able to reduce the number of gates by nearly 50% for an XOR ⊻ gate should <em><strong>immediately raise serious questions as to whether or not the definition of $AC^0$ is useful, or even meaningful.</strong></em></p>

<p>To make matters worse, when one goes to actually <em>build</em> gates in CMOS, the basic primitive is the FET transistor.  For example, the following are "common" transistor counts for most CMOS technologies:</p>

<ul>
<li>Four transistors for a 2 input NAND ⊼ gate.</li>
</ul>

<p>Therefore, in CMOS, it is possible to physically build the "logically equivalent" 2 input XOR ⊻ gate using</p>

<ul>
<li>Seven physical 2 input NAND ⊼ gates.  This would require a total of <em><strong>twenty eight</strong></em> transistors. </li>
<li>Four physical 2 input NAND ⊼ gates.  This would require a total of <em><strong>sixteen</strong></em> transistors. </li>
</ul>

<p>However, "logically equivalent" does not imply "physically optimal":</p>

<ul>
<li><em><strong>Six</strong></em> transistors for a 2 input XOR ⊻ gate.  Depending on some pedantic details, <em><strong>four</strong></em> transistor constructions are possible.</li>
</ul>

<p>Which leads me back to my original question: "Why is this [PARITY does not lie in $AC^0$] considered to be a fundamentally important result?"</p>

<p>Because, at least to me, the result has absolutely nothing to deal with reality.  In fact, taken at face value, one would incorrectly assume that the result implies that it is fundamentally impossible to construct a 2 input XOR ⊻ gate using "just" six transistors (relative to the four transistors required for a 2 input NAND ⊼ gate).</p>

<p>To cast further doubt as to whether or not the PARITY result is meaningful, it implies that constructing a <em>n</em> input XOR ⊻ gate would require "significantly" (for some definition of significantly) more "gates".  However, using three 2 input XOR ⊻ gates, it is clearly possible to construct a "logically equivalent" <em>n</em> input XOR ⊻ gate:</p>

<ul>
<li>3 input XOR ⊻ gate using two 2 input XOR ⊻ gates, for a total transistor count of ~twelve transistors.</li>
<li>4 input XOR ⊻ gate using three 2 input XOR ⊻ gates, for a total transistor count of ~eighteen transistors.</li>
</ul>

<p>The following paper gives a description of a 3 input XOR ⊻ gate using just <em><strong>six</strong></em> transistors. </p>

<p>The 3 input xor gate is provided here: <a href="http://ir.hit.edu.tw/dspace/bitstream/310993100/202/1/02-12%E9%AB%98%E6%80%A7%E8%83%BD%E4%B8%89%E8%BC%B8%E5%85%A5%E4%BA%92%E6%96%A5%E6%88%96%EF%BC%8F%E5%8F%8D%E4%BA%92%E6%96%A5%E6%88%96%E9%9B%BB%E8%B7%AF%E4%B9%8B%E8%A8%AD%E8%A8%88.pdf" rel="nofollow">http://ir.hit.edu.tw/dspace/bitstream/310993100/202/1/02-12高性能三輸入互斥或／反互斥或電路之設計.pdf</a></p>

<p>The following paper gives a description of a <a href="http://altareen.googlepages.com/xor02jul2006copyright.pdf" rel="nofollow">4 input XOR ⊻ gate</a> using just <em><strong>fourteen</strong></em> transistors, and the author specifically states "<em>I am sure that smaller gates do exist, but their implementation is beyond the scope of my experience.</em>"</p>

<p>Am I mistaken, or does the $AC^0$ PARITY "proof" make the subtle and unstated assumptions:</p>

<ul>
<li>The only boolean primitives available are AND ∧, OR ∨, and NOT ¬.</li>
<li>That the fact that AND ∧, OR ∨, and NOT ¬ are functionally complete for all of the boolean nullinary, unary, and binary operators, and therefore "logically equivalent" to different "boolean basis" formulations (i.e., either NAND ⊼ or NOR ⊽ basis).</li>
<li>The AND ∧, OR ∨, and NOT ¬ basis is the "optimal" (for some definition and/or metric of "optimal") basis for the boolean domain actualization (i.e., AND ∧, OR ∨, and NOT ¬ is the "provably optimal" physical manifestation).</li>
<li>That "logically equivalent" is sufficiently strong / closed over "provably optimal" (for some "loose and informal" definition for the purposes of our discussion/point).</li>
</ul>

<p>... or have I missed something?  Is there something "fundamentally compelling" about the decision to limit $AC^0$ to AND ∧, OR ∨, and NOT ¬?  Or the fact that it is possible to physically construct <em>n</em> input XOR ⊻ gates using significantly less resources than what one would expect using the "proven $AC^0$ PARITY result"?</p>

CC BY-SA 2.5
2010-12-06T22:53:49.947Z
This is a acceptable question (although might be elementary for this site) but I think it is unnecessarily long and written in a non-professional way. I am down-voting for now because of length and style but will reverse my vote if you rewrite it more professionally and trim it to a reasonable size.
Kaveh
CC BY-SA 2.5
2010-12-06T22:59:42.237Z
ps: Circuit complexity classes are sets of circuit *families*, one circuit for each input size ($AC^0$ is not a set of circuits). The $AC^0$ is **bounded depth** and polynomial size, i.e. the depth of the circuit families in $AC^0$ is independent of input size. Also it allows *unbounded fan-in* versions of $OR$ and $AND$ gates. Compare with circuit complexity class $NC^0$. The parity function in the result mentioned is also the *unbounded fan-in* version.
Kaveh
CC BY-SA 2.5
2010-12-06T22:59:59.320Z
XOR, NAND, and NOR gates can be simulated within $AC^0$ with AND, OR, and NOT gates with only a constant factor increase in depth/size. Thus, adding these to the set of allowable primitives doesn't actually increase the power of $AC^0$. In other words, even with XOR, NAND, and NOR gates (in addition to AND, OR, and NOT), you still can't make a polynomially-sized, constant depth circuit to compute PARITY.
mhum
CC BY-SA 2.5
2010-12-06T23:02:23.717Z
Also, the "definition" you quote at the top of your question is not the definition of $AC^0$ but rather the definition of a boolean circuit in general. $AC^0$ requires constant depth and polynomial size.
mhum
CC BY-SA 2.5
2010-12-06T23:50:10.027Z
@mhum: You state `In other words, even with XOR (...) you still can't make a polynomially-sized, constant depth circuit to compute PARITY`.  This is obviously false: If you allow "unbounded fan-in XOR gates" in to $AC^0$, then PARITY can always be calculated in a bounded depth of exactly **one**, regardless of input size.  That is to say that allowing "unbounded fan-in XOR gates" in to $AC^0$ **fundamentally** alters and **greatly** increases the power of $AC^0$.
johne
CC BY-SA 2.5
2010-12-07T00:14:25.247Z
I really would like to know what the question is here. If you're asking why the result is important, then one answer is because it was one of the first demonstration of circuit lower bounds. Is there some other answer you're looking for ?
Suresh Venkat
CC BY-SA 2.5
2010-12-07T00:44:28.077Z
@suresh: The question is that the result is important iff you restrict yourself to just ∧,∨,¬.  In other words, "_n_ input PARITY can not be computed using a constant depth of **only** unbounded fan-in ∧,∨,¬ gates".  However, "_n_ input PARITY can be computed in a constant depth of exactly **one** if you allow unbounded fan-in XOR gates", which is to say the proofs result is due only to the (arbitrary?) limitation of using "just" ∧,∨,¬ gates.  In the real world, when _n_ input PARITY / XOR gates are built, this limitation does not apply.  Therefore, the "proof" is specious.
johne
CC BY-SA 2.5
2010-12-07T01:08:24.967Z
johne, I suggest you edit the question and make it a one-paragraph question written in a professional way, the question seems to be easy to express (if I understood your comment correctly): *in practice unbounded Parity can be implemented using bounded depth circuits of polynomial size using basic electronic parts, so does the result that "parity is not in $AC^0$" have any practical value? If not, why does people consider it to be an important result?*
Kaveh
CC BY-SA 2.5
2010-12-07T01:08:29.327Z
One reason AC0 was studied was to prove oracle results about the polynomial time hierarchy. Another reason was a connection with first-order logic. No one has ever claimed that constant-depth PARITY circuits can't be built in the real world. But we know they can't be built out of AND, OR, NOT in constant depth with reasonable size circuits. The proofs of this have *many* other nice consequences beyond just "PARITY is not in AC0". They tell you interesting lessons about what AND and ORs can really do. I invite you to look into them.
Ryan Williams
CC BY-SA 2.5
2010-12-07T01:42:23.967Z
Ah. A terrible mistake. I misspoke in my previous comment. I was thinking only of binary (or, at least, bounded fan-in) XOR. The whole point is that unbounded fan-in XOR (i.e.: PARITY) is not in $AC^0$. I had not read your extensive question thoroughly enough.
mhum
CC BY-SA 2.5
2010-12-07T02:04:09.650Z
In your edit, you mention that you link to constructions of PARITY circuits that are constant-depth and poly-size in terms of transistors. However, the two linked papers seem only to consider 3-input and 4-input XOR without any discussion of extending these constructions to n inputs. Is it evident that the constructions presented scale polynomially to n inputs?
mhum
CC BY-SA 2.5
2010-12-07T06:05:20.680Z
I strongly recommend that you do as suggested and simplify your question down to a single paragraph or two. If not, I'm inclined to cast a (virtual) vote to close.
Suresh Venkat
CC BY-SA 2.5
2010-12-07T22:46:48.617Z
@johne: I don't see the point made by your current revision (revision 4). Adding unbounded fan-in NAND gates to AC0 does not make AC0 more powerful. So you can interpret PARITY not in AC0 as saying that "PARITY cannot be computed by constant-depth circuits with unbounded fan-in AND, OR, NAND and NOT gates." Does that answer your question?
Robin Kothari
CC BY-SA 2.5
2010-12-07T23:03:04.240Z
@johne it seems like after all of this, your question is: what happens if you throw NAND gates into the mix for AC^0. Is that correct ?
Suresh Venkat
CC BY-SA 2.5
2010-12-07T23:05:12.613Z
Also, I think the relevant question then is: can you simulate an unbounded fanin NAND circuit of constant depth by a constant depth circuit of only ANDS/ORs and NOTs
Suresh Venkat
CC BY-SA 2.5
2010-12-07T23:07:05.467Z
@Robin, you should post it as an answer, because I think it does answer the OP's question.
Suresh Venkat
CC BY-SA 2.5
2010-12-07T23:28:25.367Z
@Suresh: Alright. I've added that comment to my answer along with a short explanation for how NAND can be simulated by AND/NOT, without affecting the depth of the circuit.
Robin Kothari
CC BY-SA 2.5
2010-12-08T00:05:22.700Z
Based on revisions the OP is making it seems to me that the OP does not understand the concept of a **circuit family**. Therefore he does not understand why *bounded depth circuit families of polynomial size built from NAND gates* is different from *exponential size circuit families built from NAND gates* (which contains all boolean functions).
Kaveh
<cc.complexity-theory><circuit-complexity>
Parity and circuit complexity
johne
# Parity and circuit complexity

(Asked by: username_0 on 2010-12-06)

**attempt to restate question**

From the feedback, it is obvious that I have not clearly articulated my point. Also, it is not my intent to be condescending. I very clearly have a notion / idea / question that is contrary to the doctrine subscribed to by the readers of this question. I am genuinely trying to reconcile something that is so incongruent to me that it is difficult to even put in to words. I literally do no know how to express it in a succinct simple paragraph.

This may not help, but let me try an analogy. Let's say that hypothetically there are two different groups, the first one is called 'EE' and the second is called 'CS'. Both groups consider themselves to be authoritative experts in Boolean circuits. As unlikely as it may seem, for some reason the two groups do not speak to each other or read the others results, despite their common interest. There are some differences:

The "EE" group builds boolean circuits. They literally turn theoretical ideas into to something physical. Physical goods mean there are very tangible, objectively unambiguous costs involved.

The "CS" group does not (usually) build circuits. Because nothing is physically produced, the physical resource costs tend to be dramatically lower for the "CS" group, almost to the point where it is "effectively zero."

Although both groups consider themselves boolean circuit experts, there is a curious discrepancy in the choice for their respective "boolean basis." As long as the boolean basis is "complete", that basis can be provably shown to be able to serve as the building block for every possible *n*-arity boolean function. What is important is that there are a couple of "natural" boolean basis choices, but as long as the boolean basis choice is "complete", the different "natural" choices can all implement all *n*-arity boolean functions- that is to say, one choice is not "more powerful" or "more expressive" than the other. The "complete" property means that they are "logically identical", despite the seemingly paradoxical fact that they are composed of distinctly different primitives.

Almost since the dawn of building boolean circuits, the "EE" group has consistently and invariably chosen "NAND" (which, to an EE person, there is no need to state the obvious "and NOR" qualification). For the EE group, the reason for this choice is so obvious to them it literally does not occur to them that anyone would make a different choice.

The "CS" group, on the other hand, has chosen "AND, OR, NOT". This choice can express exactly the same *n*-arity circuits as "NAND", and vice versa, due to the fact that both are a "complete" boolean basis.

The fact that the "EE" group has very real physical costs, which tends to translate directly in to money, means that even though there is no logical difference between a boolean basis choice, if one of the many available choices in any way what-so-ever has a monetary advantage, that's the one that is picked.

Money has a tendency to place a **simply enormous pressure** to ensure that whatever "choice" is made is the optimal one. It is not hyperbole to say that *billions* of dollars riding on the decision. It is difficult to put in to words how much pressure and effort goes in to this. There is simply no detail, and the pedantic consequences of every possible permutation of those details, behind choosing "NAND" that is not completely understood and justified.

In my original question, I point out two examples of this: The Apollo Guidance Computer, which made landing on the moon possible, and the Cray-1, the legendary computer by Seymour Cray.

If you are unaware of the details, it is difficult to express what it means to "Space Certify" a design. I think it's safe to say that Seymour Cray is widely recognized to be genuinely gifted at "building circuits". Although it may seem "insignificant", the decision to use 4 / 5 input NAND gates exclusively in the design of the Cray 1 was one of the contributing factors behind its legendary performance.

Again, I sincerely apologize for the lengthy exposition, but based on the responses I can't help but feel that at least some of you do not fully appreciate the significance of the fact that

* There is another group of people who consider themselves "boolean circuit experts".
* This other group of "boolean circuit experts" has consistently, universally, and invariably chosen "NAND" as their boolean basis, despite the fact that there are multiple, equivalent options.
* As near as I can tell, the "CS" group began developing their boolean circuit models (i.e., $AC^0$, $NC$, etc) right around the time the first P vs. NP descriptions and theories began to take form in the 1970's.
* This means that the "EE" boolean circuit theories predate the "CS" boolean circuit theories by decades.
* Yet, despite a rich, mature, and well understood body of work that was available, the "CS" group made the curious decision to go with "AND, OR, NOT".
* At some point, someone in the "CS" group "discovered" that PARITY was not in $AC^0$, and published a peer reviewed paper.

I fully appreciate that all of this sounds completely condescending. This is genuinely not my intent. It's difficult for me to gauge this audience to determine at what point providing the justification for my point turns in to sounding like a condescending ass.

It is fairly obvious that I felt a need to justify my simple question:

> The well known result regarding *parity* and $AC^0$, also taken from from [Wikipedia](http://en.wikipedia.org/wiki/Circuit_complexity):
>
> > The Boolean function PARITY, which is 1 if and only if the sum of its input bits is odd, does not lie in $AC^0$.
>
> My question is: "Why is this considered to be a fundamentally important result?"

Now, I admit, this is an extremely odd question. The reason why I asked it is because, at least for me, I find this detail ***extremely interesting***:

* The people who actually build circuits use NAND as their boolean basis.
* The "CS" theory people choose "AND, OR, NOT".

For me, this stands out like a neon red light. Even if you think I'm completely wrong, I at least hope that you recognize "I wasn't aware of any of this, but now that you mention, it does seem a little bit weird." Experience tells me this usually goes one of two ways:

1. You completely and thoroughly understand the consequences of breaking with the established tradition.
2. You're ignorant of the nuances.

People in the first category are easy to spot. For me, it is simply inconceivable that anyone who truly understood the ramifications of deciding to go with "AND, OR, NOT" instead of "NAND" did not spend 5 minutes doodling out the maximal worst case for 3, 4, etc bits. At which point, you sort of chuckle and say "Man, this is going to totally suck in the XOR corner case."

People in the second category are harder to predict. In the worst case, they spend no effort researching the issue. This is unfortunate because they tend to end up "rediscovering" things that have been known for over 100 years.

This is why I am asking the seemingly "obvious" question. I find it almost impossible to believe that someone in group 1, who truly understood the issues involved, would deliberately and knowingly break with the fully vetted NAND boolean basis without understanding all of the consequences of doing so. It literally takes just a few minutes to work through some corner cases. I simply can not understand how someone who studied the issue would not know that:

* The XOR / PARITY corner case is going to be comically bad.
* Your practical experience tells you that this "effect" does not accurately reflect how XOR / PARITY circuits are built anyways, so it is completely benign and safe to ignore.

On the other hand, there is a peer reviewed, published paper that says "The PARITY / XOR corner case sucks when using 'AND, OR, NOT'." This is a contradiction. How do you completely understand the consequences of breaking with the established norm, and then be "surprised" by something that was hopefully blatantly obvious the moment it was decided to go with "AND, OR, NOT"?

I can't help be get the feeling that this whole "2 input NAND" thing is genuinely novel to you. You do understand what it means, right? The [2 input NAND gate](http://en.wikipedia.org/wiki/NAND_logic) is [functionally complete](http://en.wikipedia.org/wiki/Functional_completeness) for the entire boolean domain. If you can prove that this simple, 2 input NAND gate has some property, you can prove it for the entire boolean domain. Hypothetically you could do something like this:

* $\{AC^0\} ∖ \{NAND\} = ∅$
* $\{AC^\*\} ∖ \{NAND\} = ∅$
* $\{ACC^0\} ∖ \{NAND\} = ∅$
* $\{ACC^\*\} ∖ \{NAND\} = ∅$
* $\{TC^0\} ∖ \{NAND\} = ∅$
* $\{TC^\*\} ∖ \{NAND\} = ∅$

Seems too good to be true, doesn't it? Why stop there!

* $\{TM\} ∖ \{NAND\} = ∅$

Cool! But, what does that mean for...

* $\{NTM\} ∖ \{NAND\} = ∅$

.... we should be careful, we might rip a whole in the universe...

* $\{P\} ∖ \{NAND\} = ∅$

Whoa! Is there anything NAND can't do!? Thankfully, it's not that simple, because if it were I'm pretty sure someone would have pointed it out before now.

I am ***deeply curious*** if anyone can point me to a published proof that details why it can't be done, though. ;)

**original question follows**

A definition of $AC^0$ *circuit complexity* taken from [Wikipedia](http://en.wikipedia.org/wiki/Circuit_complexity):

> A Boolean circuit with *n* input bits is a directed acyclic graph in which every node (usually called gates in this context) is either an input node of in-degree 0 labeled by one of the *n* input bits, an AND gate, an OR or a NOT gate.

The well known result regarding *parity* and $AC^0$, also taken from from [Wikipedia](http://en.wikipedia.org/wiki/Circuit_complexity):

> The Boolean function PARITY, which is 1 if and only if the sum of its input bits is odd, does not lie in $AC^0$.

My question is: "Why is this considered to be a fundamentally important result?"

**edit:** From the comments, it is clear that the fundamental point / question is not being understood. Specifically: It is ***obviously*** possible to physically build *bounded depth* and *polynomial size* PARITY circuits- you need only open up a book on constructing CMOS circuits and look at how a XOR gate is *physically* constructed.

The fact that you can not build *n* input *constant depth* XOR / PARITY gates using ***only*** AND and OR gates is not doubted or disputed- that's obvious. Below, a link is given to a ***six*** transistor, ***THREE*** input XOR (i.e., PARITY) gate. This means it is trivially possible to physically build "at least" THREE input with *constant depth* of *one* XOR / PARITY gates.

The primary point is: The fact that you can not build *constant depth* XOR / PARITY gates using AND and OR gates ***DOES NOT*** imply that *constant depth* XOR / PARITY gates can not be built. The $AC^0$ PARITY proof proves something much weaker: that *constant depth* XOR / PARITY gates can not be built using just AND and OR gates. This is ***not*** the same thing as proving that *constant depth* XOR / PARITY gates can not be built, and it is a mistake to assume that they are.

If this distinction is still not clear to you, consider that a proof that *constant depth* XOR / PARITY gates can not be built using a *constant depth* / *polynomial size* number of ***transistors*** would not only be a far stronger result, but can also be trivially falsified because such constructions do, in fact, exist (links provided below).

**end edit**

If this question seems *naive* to you, then a better question to you might be "The definition of $AC^0$, with the restriction of using only AND ∧, OR ∨, and NOT ¬ gates, seems arbitrary. What is the fundamental basis for this restriction?"

If your first impulse to "What is the fundamental basis for this restriction?" is that "The primitives AND ∧, OR ∨, and NOT ¬ are functionally complete for all of the boolean nullinary, unary, and binary operators" then: ***beware of the flaming arrows.***

As an example of why the $AC^0$ restriction of AND ∧, OR ∨, and NOT ¬ is arbitrary, consider that:

* The [Apollo Guidance Computer](http://en.wikipedia.org/w/index.php?title=Apollo_Guidance_Computer), circa 1966, was built using approximately 4,100 3-input NOR ⊽ gates.
* The [Cray-1](http://en.wikipedia.org/wiki/Cray-1), circa 1976, was built using approximately 200,000 4 and 5 input NAND ⊼ gates.

For circuit builders, the decision to use either NAND ⊼ or NOR ⊽ gates as the ***only*** primitive is so blatantly obvious that it doesn't need mentioning. If this does not seem blatantly obvious to you, then: *beware of the **incoming** flaming arrows.*

Restricting ourselves to 2 input AND ∧, 2 input OR ∨, and 1 input NOT ¬ gates it is possible to create:

* A 2 input XOR ⊻ gate using two AND ∧, one OR ∨, and one NOT ¬ gate.

Restricting ourselves to just a single, 2 input NAND ⊼ gate, it is possible to create:

* A 2 input AND ∧ gate using two NAND ⊼ gates.
* A 2 input OR ∨ gate using three NAND ⊼ gates.
* A 1 input NOT ¬ gate using one NAND ⊼ gate.

Using the above, it is possible to restate $AC^0$ in terms of NAND ⊼ gates and furthermore calculate that it takes a total of seven NAND ⊼ gates using the original two AND ∧, one OR ∨, and one NOT ¬ gate definition for XOR ⊻. However, it is also possible to build a XOR ⊻ gate using less NAND ⊼ gates:

* A 2 input XOR ⊻ gate using four NAND ⊼ gates.

The seven NAND ⊼ gate and four NAND ⊼ gate constructions for a 2 input XOR ⊻ gate are "logically identical", producing exactly the same output for the same inputs. The fact that we were able to reduce the number of gates by nearly 50% for an XOR ⊻ gate should ***immediately raise serious questions as to whether or not the definition of $AC^0$ is useful, or even meaningful.***

To make matters worse, when one goes to actually *build* gates in CMOS, the basic primitive is the FET transistor. For example, the following are "common" transistor counts for most CMOS technologies:

* Four transistors for a 2 input NAND ⊼ gate.

Therefore, in CMOS, it is possible to physically build the "logically equivalent" 2 input XOR ⊻ gate using

* Seven physical 2 input NAND ⊼ gates. This would require a total of ***twenty eight*** transistors.
* Four physical 2 input NAND ⊼ gates. This would require a total of ***sixteen*** transistors.

However, "logically equivalent" does not imply "physically optimal":

* ***Six*** transistors for a 2 input XOR ⊻ gate. Depending on some pedantic details, ***four*** transistor constructions are possible.

Which leads me back to my original question: "Why is this [PARITY does not lie in $AC^0$] considered to be a fundamentally important result?"

Because, at least to me, the result has absolutely nothing to deal with reality. In fact, taken at face value, one would incorrectly assume that the result implies that it is fundamentally impossible to construct a 2 input XOR ⊻ gate using "just" six transistors (relative to the four transistors required for a 2 input NAND ⊼ gate).

To cast further doubt as to whether or not the PARITY result is meaningful, it implies that constructing a *n* input XOR ⊻ gate would require "significantly" (for some definition of significantly) more "gates". However, using three 2 input XOR ⊻ gates, it is clearly possible to construct a "logically equivalent" *n* input XOR ⊻ gate:

* 3 input XOR ⊻ gate using two 2 input XOR ⊻ gates, for a total transistor count of ~twelve transistors.
* 4 input XOR ⊻ gate using three 2 input XOR ⊻ gates, for a total transistor count of ~eighteen transistors.

The following paper gives a description of a 3 input XOR ⊻ gate using just ***six*** transistors.

The 3 input xor gate is provided here: [http://ir.hit.edu.tw/dspace/bitstream/310993100/202/1/02-12高性能三輸入互斥或／反互斥或電路之設計.pdf](http://ir.hit.edu.tw/dspace/bitstream/310993100/202/1/02-12%E9%AB%98%E6%80%A7%E8%83%BD%E4%B8%89%E8%BC%B8%E5%85%A5%E4%BA%92%E6%96%A5%E6%88%96%EF%BC%8F%E5%8F%8D%E4%BA%92%E6%96%A5%E6%88%96%E9%9B%BB%E8%B7%AF%E4%B9%8B%E8%A8%AD%E8%A8%88.pdf)

The following paper gives a description of a [4 input XOR ⊻ gate](http://altareen.googlepages.com/xor02jul2006copyright.pdf) using just ***fourteen*** transistors, and the author specifically states "*I am sure that smaller gates do exist, but their implementation is beyond the scope of my experience.*"

Am I mistaken, or does the $AC^0$ PARITY "proof" make the subtle and unstated assumptions:

* The only boolean primitives available are AND ∧, OR ∨, and NOT ¬.
* That the fact that AND ∧, OR ∨, and NOT ¬ are functionally complete for all of the boolean nullinary, unary, and binary operators, and therefore "logically equivalent" to different "boolean basis" formulations (i.e., either NAND ⊼ or NOR ⊽ basis).
* The AND ∧, OR ∨, and NOT ¬ basis is the "optimal" (for some definition and/or metric of "optimal") basis for the boolean domain actualization (i.e., AND ∧, OR ∨, and NOT ¬ is the "provably optimal" physical manifestation).
* That "logically equivalent" is sufficiently strong / closed over "provably optimal" (for some "loose and informal" definition for the purposes of our discussion/point).

... or have I missed something? Is there something "fundamentally compelling" about the decision to limit $AC^0$ to AND ∧, OR ∨, and NOT ¬? Or the fact that it is possible to physically construct *n* input XOR ⊻ gates using significantly less resources than what one would expect using the "proven $AC^0$ PARITY result"?

**Tags:** cc.complexity-theory, circuit-complexity
> **Comments:**
> **username_1**: This is a acceptable question (although might be elementary for this site) but I think it is unnecessarily long and written in a non-professional way. I am down-voting for now because of length and style but will reverse my vote if you rewrite it more professionally and trim it to a reasonable size.  
> **username_1**: ps: Circuit complexity classes are sets of circuit *families*, one circuit for each input size ($AC^0$ is not a set of circuits). The $AC^0$ is **bounded depth** and polynomial size, i.e. the depth of the circuit families in $AC^0$ is independent of input size. Also it allows *unbounded fan-in* versions of $OR$ and $AND$ gates. Compare with circuit complexity class $NC^0$. The parity function in the result mentioned is also the *unbounded fan-in* version.  
> **username_2**: XOR, NAND, and NOR gates can be simulated within $AC^0$ with AND, OR, and NOT gates with only a constant factor increase in depth/size. Thus, adding these to the set of allowable primitives doesn't actually increase the power of $AC^0$. In other words, even with XOR, NAND, and NOR gates (in addition to AND, OR, and NOT), you still can't make a polynomially-sized, constant depth circuit to compute PARITY.  
> **username_2**: Also, the "definition" you quote at the top of your question is not the definition of $AC^0$ but rather the definition of a boolean circuit in general. $AC^0$ requires constant depth and polynomial size.  
> **username_0**: @mhum: You state `In other words, even with XOR (...) you still can't make a polynomially-sized, constant depth circuit to compute PARITY`.  This is obviously false: If you allow "unbounded fan-in XOR gates" in to $AC^0$, then PARITY can always be calculated in a bounded depth of exactly **one**, regardless of input size.  That is to say that allowing "unbounded fan-in XOR gates" in to $AC^0$ **fundamentally** alters and **greatly** increases the power of $AC^0$.  
> **username_3**: I really would like to know what the question is here. If you're asking why the result is important, then one answer is because it was one of the first demonstration of circuit lower bounds. Is there some other answer you're looking for ?  
> **username_0**: @suresh: The question is that the result is important iff you restrict yourself to just ∧,∨,¬.  In other words, "_n_ input PARITY can not be computed using a constant depth of **only** unbounded fan-in ∧,∨,¬ gates".  However, "_n_ input PARITY can be computed in a constant depth of exactly **one** if you allow unbounded fan-in XOR gates", which is to say the proofs result is due only to the (arbitrary?) limitation of using "just" ∧,∨,¬ gates.  In the real world, when _n_ input PARITY / XOR gates are built, this limitation does not apply.  Therefore, the "proof" is specious.  
> **username_1**: johne, I suggest you edit the question and make it a one-paragraph question written in a professional way, the question seems to be easy to express (if I understood your comment correctly): *in practice unbounded Parity can be implemented using bounded depth circuits of polynomial size using basic electronic parts, so does the result that "parity is not in $AC^0$" have any practical value? If not, why does people consider it to be an important result?*  
> **username_4**: One reason AC0 was studied was to prove oracle results about the polynomial time hierarchy. Another reason was a connection with first-order logic. No one has ever claimed that constant-depth PARITY circuits can't be built in the real world. But we know they can't be built out of AND, OR, NOT in constant depth with reasonable size circuits. The proofs of this have *many* other nice consequences beyond just "PARITY is not in AC0". They tell you interesting lessons about what AND and ORs can really do. I invite you to look into them.  
> **username_2**: Ah. A terrible mistake. I misspoke in my previous comment. I was thinking only of binary (or, at least, bounded fan-in) XOR. The whole point is that unbounded fan-in XOR (i.e.: PARITY) is not in $AC^0$. I had not read your extensive question thoroughly enough.  
> **username_2**: In your edit, you mention that you link to constructions of PARITY circuits that are constant-depth and poly-size in terms of transistors. However, the two linked papers seem only to consider 3-input and 4-input XOR without any discussion of extending these constructions to n inputs. Is it evident that the constructions presented scale polynomially to n inputs?  
> **username_3**: I strongly recommend that you do as suggested and simplify your question down to a single paragraph or two. If not, I'm inclined to cast a (virtual) vote to close.  
> **username_5**: @johne: I don't see the point made by your current revision (revision 4). Adding unbounded fan-in NAND gates to AC0 does not make AC0 more powerful. So you can interpret PARITY not in AC0 as saying that "PARITY cannot be computed by constant-depth circuits with unbounded fan-in AND, OR, NAND and NOT gates." Does that answer your question?  
> **username_3**: @johne it seems like after all of this, your question is: what happens if you throw NAND gates into the mix for AC^0. Is that correct ?  
> **username_3**: Also, I think the relevant question then is: can you simulate an unbounded fanin NAND circuit of constant depth by a constant depth circuit of only ANDS/ORs and NOTs  
> **username_3**: @Robin, you should post it as an answer, because I think it does answer the OP's question.  
> **username_5**: @Suresh: Alright. I've added that comment to my answer along with a short explanation for how NAND can be simulated by AND/NOT, without affecting the depth of the circuit.  
> **username_1**: Based on revisions the OP is making it seems to me that the OP does not understand the concept of a **circuit family**. Therefore he does not understand why *bounded depth circuit families of polynomial size built from NAND gates* is different from *exponential size circuit families built from NAND gates* (which contains all boolean functions).  

---

## 3 answers

### Answer by username_5 on 2010-12-07. Score: 18

While I understand the question you are trying to ask, I find the presentation sub-optimal. This might just be me, but I find the tone of the question slightly condescending. I'm sure this is not what you meant to convey -- I'm just telling you how it comes across to me.

Anyway, I can try to answer some of your questions. Let me start with a pair of misconceptions:

* **Misconception 1**: PARITY not in AC0 says that "it is not possible to build polynomial-size constant-depth circuits to compute parity in the real world."

This is not true at all. The result claims exactly what it does: It is not possible to compute parity using a constant-depth polynomial-size circuit composed only of (and this is the important part) NOT gates, and unbounded fan-in AND and OR gates.

* **Misconception 2**: It is believed that just because AND, OR and NOT gates form a complete basis, AC0 is robust under changing these gates to any other gates.

As you pointed out, this is not true. If you used unbounded fan-in XOR gates, then obviously PARITY has a depth-1 circuit. The class which has unbounded fan-in XOR gates in addition to the usual NOT, AND and OR gates is called AC0[2]. AC0 is not robust under changing the gate set (unlike some other classes like NC0, where any complete basis will do the job). For example if we allow the MAJORITY gate in addition to the AND, OR and NOT gates, we get a class called TC0, which is much bigger than AC0.

An interesting question which arises, and which you have explicitly asked, is the following:

> "The definition of AC0, with the restriction of using only AND ∧, OR ∨, and NOT ¬ gates, seems arbitrary. What is the fundamental basis for this restriction?"

This is a nice question. It also has a good answer. I don't think I can answer this satisfactorily myself, so I'll let someone else do it. I'll try answering it myself if no one else chooses to do so. But note that the answer is not "AC0 models real world circuits."

This question also immediately leads to the question "Why is this result interesting?" I'm not sure if this is what you meant to ask, but some good answers are given on the [complexity theory blog](http://blog.computationalcomplexity.org/2008/03/why-is-parity-not-in-ac0-important.html).

So if we look at your your claimed "subtle and unstated" assumptions, you'll find that most of them are very clearly stated. For example, the fact that you can only use AND, OR and NOT is in the *definition* of AC0. I can't imagine anything being stated more explicitly than that!

## Answer to revision 4

In revision 4 it seems like the question really is "Why don't we allow AC0 to have NAND gates also (because those are the gates used in real life by EE folks)?"

The answer is simple. Adding unbounded fan-in NAND gates to AC0 does not make AC0 more powerful. So you can interpret PARITY not in AC0 as saying that "PARITY cannot be computed by constant-depth circuits with unbounded fan-in AND, OR, NAND and NOT gates."

An unbounded fan-in NAND gate is just an unbounded fan-in AND gate with the output negated. So every NAND gate can be replaced by an AND gate and a NOT gate. Then, all the NOT gates can be pushed down to the inputs using standard techniques. At the end, the depth remains the same, and the size might increase by something like a factor of 4.

> **Comments:**
> **username_2**: But note that the answer is not "AC0 models real world circuits." Indeed. Just because $AC^0$ is defined in terms of logic gates doesn't mean we have to think of it so. If you prefer, we can think of $AC^0$ as the class of languages recognized by poly-length programs over finite, aperiodic monoids.  
> **username_6**: I think this question is closely related to the issue being discussed  http://cstheory.stackexchange.com/questions/1794/circuit-lower-bounds-over-arbitrary-sets-of-gates  

---

### Answer by username_2 on 2010-12-07. Score: 7

> Below, a link is given to a six transistor, THREE input XOR (i.e., PARITY) gate. This means it is trivially possible to physically build "at least" THREE input with constant depth of one XOR / PARITY gates.

Unless I am completely misinterpreting these sentences, I think there may be some confusion in how "constant depth" is defined. First off, in circuit complexity, we deal in families of circuits, one circuit for each input size. So, when we say we can compute PARITY in some circuit model, what we mean is we have a sequence of circuits $C\_1, C\_2, C\_3, \ldots$ such that $C\_k$ computes the parity function on $k$ boolean inputs. The idea of constant depth is that there exists some $D$ such that each circuit $C\_k$ has depth at most $D$ **for all** $k$, no matter how large. Similarly, "poly-size" implies that there is some polynomial $p(x)$ such that each circuit $C\_k$ has no more than $p(k)$ gates.

Exhibiting an instance of a circuit that computes the parity function on 3 inputs does not really say anything about "constant depth" as it is defined in complexity theory. "Constant depth" is a property of the asymptotic behavior of your circuit family.


---

### Answer by username_7 on 2014-01-24. Score: 5

**Regarding the choice of basis:** all finite bases are (polynomially) equivalent. That means that if $C$ is a circuit over a *finite* base $B$ and $B'$ is any complete basis, then there is an equivalent circuit $C'$ over $B'$ of size at most $\alpha\_1 |C|^{\alpha\_2}$, where $\alpha\_1,\alpha\_2$ depend only on $B,B'$. This is proved for example in [Reckhow's thesis](http://www.cs.toronto.edu/~sacook/homepage/reckhow_thesis.pdf) (Section 5.3), though the result itself is due to [Spira](http://citeseer.uark.edu:8080/citeseerx/showciting;jsessionid=F593B995B9338A1124209542D7EE5B48?cid=1249521). What this means informally is that when we're doing circuit complexity, we don't really care whether the basis is NAND or AND, OR, NOT. (That's because in circuit complexity we often don't care about polynomial factors.) NAND was chosen because that's what can be implemented in hardware. AND, OR, NOT were chosen for historical reasons: that's what was used in logic (along with similar bases such as NOT, IMPLIES for which $\alpha\_2 = 1$ both ways). Circuits with unlimited arity PARITY gates don't fall under this formalism, since the basis is infinite.

**Regarding the importance of Håstad's result:** This was the first non-trivial bound in circuit complexity. It is still one of the best bounds known for non-monotone models, along with the Razborov–Smolensky methods, and Razborov's slightly superlinear lower bound for switching networks. All other bounds rely on restrictions of the model, usually monotonicity.

Parity is computed in real life in an iterative fashion, using tables or simply by "deep" circuits (this concept is of course hard to define exactly, since constant depth is an asymptotic notion). That's a different model. Circuits considered in circuit complexity are good enough for the P vs. NP question (or rather, P/poly vs. NP). At the time, it seems that people thought that the methods developed for small complexity classes would scale up to polysize circuits, but this hope hasn't materialized. Nowadays it is a less presumptuous specialist area.


---

