<p>I'm a bit new to the practical use of memristors in general, but I'm starting to see it as a (3D stacked) grid of components that could be treated as transistors or flip-flops on demand (which may be completely wrong, I'm not sure). It seems like the usual Von Neumann architecture wouldn't be ideal at all (of course you could emulate it, but it doesn't seem like a good idea). Does anyone know of any models that are better suited? I'm trying to get my brain to move past a model that would create variable "cores" that scale with size as the program runs in the memristive space (I've been poisoned by the current models) and more of one where the "core" and memory is combined (no independent TLB/cache/RAM).</p>

<p><strong>Edit:</strong> As to what I mean by memristive grid -- So, lets say you have a 3 dimensional hypercube with "nodes" at each discrete x,y,z coordinate. Each one of these nodes is addressable. When you address a node, you can tell it to become a bit of memory or a gate (just like an FPGA gate). After you tell all of the nodes what they are, you can then perform computation in the hypercube using the landscape of memory and gates that you designed. It's kinda like a processor with bits of memory sitting right next to the transistors, but you can reconfigure it as you go (under a nanosecond for each reconfiguration), possibly after each instruction that you execute in the landscape.</p>

<p><strong>Edit:</strong> One of the things that got me interested in thinking about this problem is the idea that you can calculate Hilbert integers for a space filling curve and transpose the hypercube into a linear space using reflected binary codes -- it might lead into some interesting memory arrangements when you try to optimize the clustering of memristive memory and computation.</p>

CC BY-SA 3.0
2011-05-20T17:41:26.303Z
I wonder if this is more related to electrical engineering than theoretical computer science? Would it make sense to try http://electronics.stackexchange.com/ or http://physics.stackexchange.com/ first?
Jukka Suomela
CC BY-SA 3.0
2011-05-20T17:52:44.583Z
I don't really think that EE is the right category for this. I'm referring to computational models in a memrestive grid (the specifics of the hardware really doesn't matter much). I guess I could rephrase the question to use an abstract piece of hardware based on material conditionals, but I'm not sure how to phrase it so it makes sense.
Jon Bringhurst
CC BY-SA 3.0
2011-05-20T18:04:14.377Z
@Jon: I think it would be very useful to try to describe the high-level properties of a memristor grid. TCS people do study computation in all kinds of grids (cellular automata, DNA computation, distributed and parallel computing, etc.), but most of us have no idea what is a memristor grid. [I thought I knew what memristors are, but I have never thought that they would have any TCS implications...]
Jukka Suomela
CC BY-SA 3.0
2011-05-20T18:54:51.257Z
Although it's a bit lengthly, here's a good video on the topic (by the guy who runs the HP lab): http://www.youtube.com/watch?v=bKGhvKyjgLY
Jon Bringhurst
CC BY-SA 3.0
2011-05-20T19:29:18.477Z
@Jukka Another impact this might have on TCS might be the concept of using material implication rather than nand based logic. There's some guy who made a C compiler that reduced compiled code size by like 1/3 from this (compared to nand/nor). I can't seem to find a paper anywhere tho.
Jon Bringhurst
CC BY-SA 3.0
2011-05-23T07:02:56.183Z
I think this question is definitely in scope, although it might help to tighten up the model slightly
Suresh Venkat
CC BY-SA 3.0
2011-05-26T22:53:58.207Z
The model stated in the question sounds related to cellular automata (on hypercubes instead of the usual linear tapes).
Tsuyoshi Ito
<computability><machine-models>
What is the the optimal computational model for memristive style CMOS?
Jon Bringhurst
# What is the the optimal computational model for memristive style CMOS?

(Asked by: username_0 on 2011-05-20)

I'm a bit new to the practical use of memristors in general, but I'm starting to see it as a (3D stacked) grid of components that could be treated as transistors or flip-flops on demand (which may be completely wrong, I'm not sure). It seems like the usual Von Neumann architecture wouldn't be ideal at all (of course you could emulate it, but it doesn't seem like a good idea). Does anyone know of any models that are better suited? I'm trying to get my brain to move past a model that would create variable "cores" that scale with size as the program runs in the memristive space (I've been poisoned by the current models) and more of one where the "core" and memory is combined (no independent TLB/cache/RAM).

**Edit:** As to what I mean by memristive grid -- So, lets say you have a 3 dimensional hypercube with "nodes" at each discrete x,y,z coordinate. Each one of these nodes is addressable. When you address a node, you can tell it to become a bit of memory or a gate (just like an FPGA gate). After you tell all of the nodes what they are, you can then perform computation in the hypercube using the landscape of memory and gates that you designed. It's kinda like a processor with bits of memory sitting right next to the transistors, but you can reconfigure it as you go (under a nanosecond for each reconfiguration), possibly after each instruction that you execute in the landscape.

**Edit:** One of the things that got me interested in thinking about this problem is the idea that you can calculate Hilbert integers for a space filling curve and transpose the hypercube into a linear space using reflected binary codes -- it might lead into some interesting memory arrangements when you try to optimize the clustering of memristive memory and computation.

**Tags:** computability, machine-models
> **Comments:**
> **username_1**: I wonder if this is more related to electrical engineering than theoretical computer science? Would it make sense to try http://electronics.stackexchange.com/ or http://physics.stackexchange.com/ first?  
> **username_0**: I don't really think that EE is the right category for this. I'm referring to computational models in a memrestive grid (the specifics of the hardware really doesn't matter much). I guess I could rephrase the question to use an abstract piece of hardware based on material conditionals, but I'm not sure how to phrase it so it makes sense.  
> **username_1**: @Jon: I think it would be very useful to try to describe the high-level properties of a memristor grid. TCS people do study computation in all kinds of grids (cellular automata, DNA computation, distributed and parallel computing, etc.), but most of us have no idea what is a memristor grid. [I thought I knew what memristors are, but I have never thought that they would have any TCS implications...]  
> **username_0**: Although it's a bit lengthly, here's a good video on the topic (by the guy who runs the HP lab): http://www.youtube.com/watch?v=bKGhvKyjgLY  
> **username_0**: @Jukka Another impact this might have on TCS might be the concept of using material implication rather than nand based logic. There's some guy who made a C compiler that reduced compiled code size by like 1/3 from this (compared to nand/nor). I can't seem to find a paper anywhere tho.  
> **username_2**: I think this question is definitely in scope, although it might help to tighten up the model slightly  
> **username_3**: The model stated in the question sounds related to cellular automata (on hypercubes instead of the usual linear tapes).  

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## 0 answers

