VHDL and Verilog are some of the HDLs used today.
What are the advantages and disadvantages of using Verilog or VHDL over the other?
I can't tell you which to learn, but here's some contrasting points (from a very VHDL-centric user, but I've tried to be as fair as possible!), which may help you make a choice based on your own preferences in terms of development style:
And keep in mind the famous quote which goes along the lines of "I prefer whichever of the two I'm not currently using" (sorry, I can't recall who actually wrote this - possibly Janick Bergeron?)
VHDL

strongly-typed
more verbose
very deterministic
non-C-like syntax (and mindset)

Lots of compilation errors to start with, but then mostly works how you expect.  This can lead to a very steep feeling learning curve (along with the unfamiliar syntax)
Verilog

weakly-typed
more concise
only deterministic if you follow some rules carefully
more C-like syntax (and mindset)

Errors are found later in simulation - the learning curve to "feeling like getting something done" is shallower, but goes on longer (if that's the right metaphor?)
Also in Verilog's favour is that high-end verification is leaning more and more to SystemVerilog which is a huge extension to Verilog.  But the high-end tools can also combine VHDL synthesis code with SystemVerilog verification code.

For another approach entirely: MyHDL - you get all the power of Python as a verification language with a set of synthesis extensions from which you can generate either VHDL or Verilog.
Or Cocotb - all the power of Python as a verification language, with your synthesisable code still written in whichever HDL you decided to learn (ie VHDL or Verilog).
SystemC is also a good option for an HDL. SystemC supports both System level and Register Transfer Level (RTL) design. You need only a C++ compiler to simulate it. High-Level Synthesis tools will then convert SystemC code to Verilog or VHDL for logic synthesis.
