Project abstract for group sapatnek
Computer-Aided Design of VLSI Circuits
These researchers use MSI supercomputing resources to solve problems in the domain of computer-aided analysis and optimization of VLSI designs. Specifically, the projects will address problems in the areas of: impact of thermal-mechanical effects on circuit performance in sub-micron planar and 3D-IC technologies; and electromigration-aware power delivery network analysis.The key aspects are described below.
The first project, on the impact of thermal-mechanical effects on circuit performance in sub-micron planar and 3D-IC technologies, involves two aspects. First, 3D integrated circuits are an emerging technology paradigm where multiple layers of conventional 2D circuits are stacked over each other, with through-silicon vias (TSVs) used to connect the layers. TSVs introduce thermal stress into the silicon die, which in turn causes electrical changes due to piezoresistive effects. This first part of this project studies the effects of TSVs on circuit behavior. Second, IC manufacturing uses silicon-dioxide to isolate (also called STI) different active regions in a chip that make up the transistors. The active regions are made up of silicon. Due to the CTE mismatch between Silicon and SiO2 there is a thermal residual stress developed inside the active silicon that impacts its electrical properties and hence its circuit performance. This second part of this project studies the effects of STI on circuit behavior.
The rationale for the second project is that electromigration has become a serious reliability issue while designing VLSI circuits in current technologies. There is a growing need to accurately model the effects of electromigration, which is critical in the design of the VLSI circuits. Current models for electromigration in interconnects are simple and inaccurate, and we would like to develop accurate yet computationally efficient electromigration model for the interconnects (metal wires), and further apply the model to analyze the power delivery network on chip which typically has tens of thousands of metal wires.