November 8, 2007 -- The SOC (system on chip) began life in the image of the board-level computers that preceded it: as a central processor that a CPU bus connected to local memory and peripheral controllers. That CPU-centric, bus-oriented architecture has since been the underlying plan for many SOCs. But integration has brought complexity in the form of complex peripherals with their own DMA (direct-memory-access) controllers, coprocessors, and additional central processors, all on the same die. Accordingly, the interconnect architecture of SOCs is changing. The old CPU-centric bus is fast retreating to within the functional blocks of the chip; multiple buses, specialized point-to-point links, and on-chip networks are replacing it.
Change is rapid, and architects are nearly unanimous in worrying that the change has far outrun the tools necessary to support it. "Today, we still see a number of classic SOC designs, with an ARM core, peripherals, and a memory interface," observes Hugh Durdan, Vice President of Marketing at ASIC supplier eSilicon. "Even when these designs grow to include multiple processing cores, they often stick with the classic AMBA AHB [Advanced Microcontroller Bus Architecture Advanced High Performance Bus] structure."
But there are growing indications that the centralized-bus approach to SOC interconnect is simply running out of steam (see sidebar “Is the problem bus bandwidth or processor bandwidth?”). This problem appears to be partly architectural. As the number of processing nodes on a chip increases and as the data traffic that those nodes generate or consume grows and becomes more varied, the simple demand for raw bandwidth becomes a problem (Figure 1). Yes, it is possible with nine layers of metal and statistical-timing tools to give a multimaster bus almost-arbitrary bandwidth. But the costs in layout complexity, signal-integrity analysis, power consumption, and congestion—especially in this day of stringent design-for-manufacturing rules—make this approach nearly intractable.