The northbridge: a look back at the Intel 430HX
The northbridge is really the heart of the motherboard, which is why a chipset usually goes by the name of its northbridge chip. For instance, the Intel 82443BX/82371SB northbridge/southbridge combination, which we'll take a look at later in this guide, was a chipset that went by the official name of "440BX" and was popularly called the "BX chipset." Similarly, the chipset that we'll look at in the next two sections is called the Intel 430HX chipset, because it consists of the 82439HX northbridge and the 82371SB southbridge. The 430HX is a fairly typical Pentium-era chipset, which is why we'll use it as an example chipset to get you familiar with the the basics of northbridge and southbridge functionality.
The northbridge is so important is because attached to it are the most critical components in the computer system: the CPU, RAM, and the all of the PC's most bandwidth-intensive I/O devices (video, sound, networking, and the other devices that sit on the high-bandwidth expansion bus.). Segregating these high-bandwidth components from the rest of the system and giving them their own private "hub" enables system designers to keep down the cost of the bridge chip and the motherboard. Thus the northbridge can focus primarily on routing traffic among processor, memory, and bandwidth-intensive I/O components, while letting another chip (the southbridge) focus on slower I/O traffic and miscellaneous functionality (timing, power management, the BIOS, etc.).
Note: if you're reading this and thinking "I thought that the southbridge handled all of the I/O, including the PCI bus," you're probably thinking of chipsets produced after Intel's 800-series chipsets. The 800-series introduced the Intel Hub Architecture by turning the northbridge and southbridge into a Memory Controller Hub (MCH) and an I/O Controller Hub (ICH), respectively. However, for chipsets that supported the original Pentium, the Pentium Pro, the Pentium II, and the early Pentium III (along with their competitors), the PCI bus is attached to the northbridge. In fact, the northbridge has consistently handled high-bandwidth I/O devices in one form or another at least since the original Pentium days.
Figure 5 from the previous section (reproduced above with one addition as Figure 6) is essentially a diagram of a system based on the Intel 430HX (a.k.a. Triton II) chipset. The 430HX was one of the more popular business-oriented chipsets for the original Pentium, and it supported features like USB, EDO DRAM, and PCI.
As you can see from Figure 5, the 430HX's northbridge (the 82439HX) has four buses hanging off of it:
- The memory bus is the RAM's single avenue of communication with the rest of the system. The northbridge's memory controller manages traffic on the memory bus, and performs all of the memory accesses on behalf of the rest of the components in the system.
- The frontside bus (FSB) connects the CPU to northbridge, and thus it is the CPU's sole means of communication with the rest of the system. Instructions, data, and results all travel to and from the CPU over the frontside bus. Because the FSB plays such a critical role in enabling the processor to talk to the other components on the motherboard, it is essential that the FSB have as much bandwidth as possible.
- The peripheral component interconnect (PCI) bus connects the northbridgeand hence the CPU and RAM alsoto two things: 1) the southbridge chip, and 2) a collection of important and bandwidth-intensive add-on devices like the video card, network card, soundcard, etc.
- The L2 cache bus connects the northbridge to the L2 cache. The level 2 cache, which was soldered onto the motherboard in many early PC systems, serves as even faster "fast storage" than RAM. Thus the L2 cache sits "between" the RAM and the CPU on the storage heirarchy. Most L2 caches have moved off the motherboard and are now etched onto the same silicon die as the CPU, so they more properly belong in a CPU guide and not a motherboard guide. This being the case, I've mainly included the L2 cache and cache bus here for completeness' sake, and I won't be discussing it more in this guide.
We'll look at the first three buses above in more detail later, but for now it's sufficient to note their names and functions.
Bus protocols and bridges
The memory bus, FSB, and PCI bus each speak a special language called a bus protocol. In fact, each type of bus that we'll meet as we explore the motherboard has a different bus protocol. Because bus protocols are unique to each type of bus, the bridge chips that connect these buses together must not only act as traffic routers, but they must also function as translators, translating information encoded in one bus protocol into another bus protocol for transmission on a different bus.
Figure 7: The Intel 430HX northbridge
This being the case, the northbridge needs special interface hardware for each of its three buses. I mentioned above that the memory controller sits on the northbridge and acts as the interface between main memory and the rest of the system. This memory controller translates memory access requests that originate with the CPU and other system components into a language that the memory subsystem can understand.
Similarly, the northbridge also has a special frontside bus interface (= "host interface" in Figure 7 above) through which the northbridge and the rest of the system can communicate with the CPU. Finally, the PCI bus is attached to a PCI controller, which manages PCI bus traffic and handles protocol translation chores.
Incidentally, these crucial protocol translation functions are why the two chips that make up the chipset are called "bridge" chipsbecause their on-board interface hardware bridges the language gap between different bus protocols.