One of the standard types of testing that is done in XJTAG’s Connection Test is to detect stuck-high and stuck-low faults (shorts to power/ground).
Using the IEEE 1149.1 JTAG standard this can be done providing the net has full IN/OUT functionality – that is to say it can both drive output and read input at the same time. The test is implemented by driving the net high or low and then checking that the value read from the net changes to reflect the value driven.
This method works very well – however it cannot be used on nets that cannot both input and output at the same time. If a net’s JTAG pin(s) only has/have input capability, the Connection Test cannot deduce a fault if the pin is not going high and low during the test, because the net cannot be driven. Alternatively, if the JTAG pin(s) on a net only has/have output capability, XJTAG can try to drive the net high and low but it cannot check that the actual value of the net changes.
The 1149.6 revision to the JTAG standard added a lot of extra functionality to allow testing of high speed signals – part of this functionality can however also be used to test for stuck-at faults (shorts to power or ground) on input-only pins.
When an input-capable pin implements the 1149.1 standard, data loaded into the boundary scan cell used to capture the value of a pin has no effect, because it is always overwritten by the digital value captured from the net. Any voltage below the low threshold of the pin will result in a 0 being captured and any value above this threshold will result in a 1 being captured.
1149.6 input pins (in 1149.1-compatible mode) behave slightly differently – they have two thresholds. At a voltage below the low threshold the input cell will capture a 0, and above the high threshold the cell will capture a 1. However if the voltage on the pin is between the these two thresholds then the data loaded into the boundary scan cell by scanning data through the JTAG chain will remain unchanged.
XJTAG makes use of this functionality by deliberately loading a pattern of 0s and 1s into the input cells for 1149.6 pins. Because of this we can detect a net which is stuck high or low because instead of reading back the pattern that we load in, it will read back either always a 1 or always a 0.
While it is very useful that 1149.6 gives an additional mechanism to test for stuck at faults there can be problems. It has been found that some devices do not correctly implement this aspect of the 1149.6 standard and this leads to stuck at faults being falsely reported on boards containing such devices.
In order to allow boards containing devices that have a faulty 1149.6 implementation to be tested, XJDeveloper has an option, on the configuration dialog for the JTAG device, to ignore stuck-at faults that are identified in the 1149.6 phase of testing. This will remove errors from these (1149.6-non-compliant) pins but be aware that it also slightly reduces the test coverage for the device, in that it can hide real stuck-at errors should they occur. Often the spurious stuck-at errors will occur on unconnected inputs, and so setting this option will remove stuck-at test coverage from all the 1149.6-capable inputs of the device, not just the unconnected ones. If this is not acceptable then setting each of the unconnected inputs to have a Constant Value of “Input” will just prevent testing of those nets.
It is relatively rare for an 1149.6 pin to have full IN/OUT functionality but when they do then they will still be tested for stuck at faults in the same way as an 1149.1 pin.