The DesignWare Ethernet Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802 and consortium specifications for 1G, 2.5G, 5G and 10G Ethernet PCS layers. The DesignWare Ethernet PCS core provides an interface between the Media Access Control (MAC) and Physical Medium Attachment Sublayer (PMA) through a Media independent interface. With support for GMII for 1000BASE-X PCS defined for a single lane which operates at 125 MHz to support 1000BASE-X PMA and XGMII for 10GBASE-X PCS defined for four lanes which operate at 312.5 MHz on each lane to support 10GBASE-X and 10GBASE-R PMA. To maintain transition density and DC balancing, the 1000BASE-X and 10GBASE-X PCS use 8B/10B encoding/decoding and 10GBASE-R PCS uses 64B/66B encoding or decoding and the scrambling technique.
The DesignWare Ethernet PCS IP is verified using state-of-the-art methodologies including the RTL design, verification, hardware verification and interoperability tests. The IP is easily configured with a user-friendly application interface for easy functional and implementation objectives to meet design requirements, making the DesignWare Ethernet PCS IP a streamlined and flexible solution. Coupled with the DesignWare XGMAC IP and a configurable Media Access Control (MAC) that supports 1G/2.5G/5G/10G Ethernet applications, the Ethernet PCS IP offers easy SoC integration into 1G/2.5G/5G/10G Ethernet designs.
The DesignWare Ethernet IP solutions consist of configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.
Option to have either IEEE 802.3 Clause 45 compliant MDIO serial interface or parallel micro-controller interface for the host.