What about evolving the hardware to do the hashing rather than writing it as straight VHDL?
I had a good idea about using hadoop clusters to run the fitness tests for the evolutionary algorithm testing.
For those who have no clue what i am talking about, read the article about the professors that got an fpga to recognize the difference between two tones with way less than 100 gates and no CLK.
I always had a thought that evolving the circuits would be a way to find really fast ways of "cracking" various hashing algorithms, as well as making really tiny encoders and decoders for various projects.
Anyhow, i enjoyed this thread.
You're on the right track - the synthesis of ASIC or FPGA circuitry from Verilog or VHDL code is very very good these days, but there are ways to make things better particularly when you are building an ASIC.
Could you expand more on this idea? Not all applications are suited for evolutionary approaches, and my guess is that hashing algorithms are definitely not one of them.
That kind of application is well suited to evolutionary approaches.
There's not supposed to be any smooth gradients in a cryptographically secure hash, so I don't see how any evolution-based approach could work for cracking them. What exactly do you have in mind?
I'm very interested in high performance,low cost and ultra low energy hardware for mining.
The FPGA already meets my needs for low power use and high performance,now all I need is it to be low cost and I can easily get my hands on one.Hope its in UK soon.
The setup has to be easy as well.
If someone can create something that can rival my Radeon HD 6950 (400MHash/s),then I can finally put those noisy GPU and CPU things to rest.
Een if it doesn't rival my card,I can use several FPGAs together to get that performance anyways.
I worked out its less than 13Watts with 6 units (1 each produces 70MHash/s) VS 210Watts for my card.