Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
Report: ASUSTeK K55A K55A.407 read
[PATCH] Add support for Fujitsu...
Carl-Daniel Hailfinger
Hi Vadim,
thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques.
On 09.04.2010 08:12, Vadim Girlin wrote:
I'm going to try coreboot on Gigabyte GA-MA770-UD3. It's AMD 770 (RX780 / SB700).
My motherboard supports hardware dual bios - with two chips on it. I'm going to try flashing backup chip and boot from it. It seems to be possible - I've tested it (flashing at least). Chips on this board could be switched by changing bit 0 at undocumented register EF on LDN 7 of IT8720. I can use slightly patched flashrom for accessing any chip I want without any problems. And this is tested many times.
My idea is to use backup chip for debugging - that always keeps my chance to reboot from main bios chip. And removes the need for desoldering etc.
And second problem is that original bios is checking second chip - and trying to recover it by flashing the bios from main chip on reboot? rewriting coreboot. AFAICS this could be solved by including some signatures etc. It seems to be easy to find out. May be someone is working on this?
BTW I can send the patch for flashrom - but I think that with information I mentioned above somebody could make it much better than my ugly hack. I hope the regs should be the same for all latest Gigabyte MBs using IT8720/18
It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips.
By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers.
Regards, Carl-Daniel
-- http://www.hailfinger.org/
Andriy Gapon
New subject: Dualbios on GA-MA770-UD3
on 09/04/2010 15:18 Carl-Daniel Hailfinger said the following:
BTW: http://www.flashrom.org/pipermail/flashrom/2009-September/000542.html
Doesn't look like anybody showed interest that time.
-- Andriy Gapon
On 09.04.2010 14:35, Andriy Gapon wrote:
I'm very sorry about that. Your mail is still on my huge TODO list (final university exams are eating up my time). Two weeks from now I'll finally have time to start tackling all flashrom TODOs.
No problem, I frequently find myself in the same situation.
Vadim Girlin
New subject: [coreboot] Dualbios on GA-MA770-UD3
On 04/09/2010 04:18 PM, Carl-Daniel Hailfinger wrote:
OK, I'm sending the patch for flashrom - but it is based on RE and needs careful testing. It works fine on GA-MA770-UD3 (rev 1.0) but should be tested with other MBs. Anyway I hope it should work for all latest Gigabyte MBs with dual bios chips connected through IT8720/18. I think it's not ready for inclusion in flashrom - it probably should be done in more safe and generic way. Probably it should check for default values in regs etc.
It may be used as following:
flashrom -p it87spi:gbdualindex=0 ... flashrom -p it87spi:gbdualindex=1 ...
This value needs to be set only once and further ops on selected chip can be performed without parameters.
Index: it87spi.c =================================================================== --- it87spi.c	(revision 992) +++ it87spi.c	(working copy) @@ -155,6 +155,28 @@ sio_write(port, 0x65, (flashport & 0xff)); free(portpos); } + +	portpos = extract_param(&programmer_param, +	"gbdualindex=", ",:"); +	if (portpos) { +	int chip_index = strtol(portpos, (char **)NULL, 0); +	if ((chip_index!=0) && (chip_index!=1))	{ +	msg_perr("Dual bios: Invalid chip index requested: %d\n",chip_index); +	flashport=0; +	} else { +	tmp=sio_read(port,0xEF); +	msg_pinfo("Dual bios: Current chip : %d\n",tmp&1); +	if (chip_index!=(tmp&1)) { +	sio_write(port,0xEF,(tmp&0xFE)|chip_index); +	tmp=sio_read(port,0xEF)&1; +	if (tmp!=chip_index) { +	msg_perr("Dual bios: Chip selection failed.\n"); +	flashport=0; +	} else msg_pinfo("Dual bios: Selected chip: %d\n",tmp&1); +	} +	} +	free(portpos); +	} } exit_conf_mode_ite(port); break;
That could be very helpful for me. This register (LDN 7 reg EF) seems to be very interesting. Bit 0 is chip select, but also bits 2,4,5,6 are used in bios code. Bit 6 probably is some watchdog setting - setting it on with resetting other bits causes reboot in ~ a second.
Also there is some moment in bios code about test reg 2F @ LDN F4 - it is toggled in some place and this could be important - may be enabling some undocumented features.
Another interesting moment is checking for status of RI2 event (LDN 4 reg F1 bit 1) - it's almost first op in bios startup code. AFAICS RI2 event causes switch to chip 1 (Backup) and reboot - but there is no COM2 port on that board. And settings at reg 29 after boot told me that RI2 pin is switched to GPIO mode. So it is probably some debugging feature - if we find the way to set RI2 event then it seems to be an easy way to boot from backup bios.
BTW all info I have on this is from it8718 datasheet, but it seems that the code is same for 8718 and 8720.
Here is a dump of all regs of superio chip - may be it will help:
entered cfg 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 F4 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x00 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 3 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 6 2 0 0 2 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x01 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 3 F8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 4 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 50 50 50 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x02 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 50 50 50 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x03 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 3 78 0 0 0 80 0 0 0 0 0 0 0 0 0 0 70 7 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x04 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 2 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 8 8 2A 80 88 3E 1B 0 0 0 0 0 0 0 0 0 selected LDN 0x05 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 60 0 64 0 0 0 0 0 0 0 0 0 0 0 0 70 1 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x06 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 C 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x07 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 2 20 2 38 0 0 0 0 0 0 0 0 0 0 70 0 1 0 38 0 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 80 0 0 40 1 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 3E 3E 7E F0 0 0 0 0 0 0 26 0 0 0 0 0 8C 0 0 0 selected LDN 0x08 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x09 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x0A 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 3 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 B 2 0 0 4 4 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x0B 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 B 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x0C 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x0D 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 D 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x0E 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 E 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0x0F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 selected LDN 0xF4 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 F4 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 87 20 5 40 3A 0 10 0 40 80 0 0 1 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 left cfg
-- Best regards, Vadim Girlin
Rudolf Marek
Hm the LDN 7 EF is not documented in old 0.4 version of datasheet.
Yes no docs again,
This bit is marked reserved.
Hmm the LDN F4 is really some debug feature... Maybe someone should get new datasheet ;)
The test register is only RW when written from LDN F4.
Thanks, Rudolf
13 Apr 13 Apr
On 04/09/2010 08:05 PM, Rudolf Marek wrote:
Sorry, it seems that I should not send any dumps of bios code to this list. It is mentioned on the page on flashrom.com - but not on the page about mailing list on coreboot.com.
I've seen this only now. Probably you should mention it on the page about mailing list on coreboot.com.
I hope it's not a big problem.
Logs and output from flashrom/superiotool/lspci are OK. Only BIOS images ("dumps") retrieved with "flashrom -r" or downloaded from the vendor website are problematic.
Stefan Tauner
20 Jul 20 Jul
On Fri, 09 Apr 2010 19:08:21 +0400 vadimgirlin at gmail.com (Vadim Girlin) wrote:
Index: it87spi.c
--- it87spi.c	(revision 992) +++ it87spi.c	(working copy) @@ -155,6 +155,28 @@ sio_write(port, 0x65, (flashport & 0xff)); free(portpos); }
portpos = extract_param(&programmer_param,
"gbdualindex=", ",:");
if (portpos) {
int chip_index = strtol(portpos, (char **)NULL, 0);
if ((chip_index!=0) && (chip_index!=1))	{
msg_perr("Dual bios: Invalid chip index requested: %d\n",chip_index);
flashport=0;
tmp=sio_read(port,0xEF);
msg_pinfo("Dual bios: Current chip : %d\n",tmp&1);
if (chip_index!=(tmp&1)) {
sio_write(port,0xEF,(tmp&0xFE)|chip_index);
tmp=sio_read(port,0xEF)&1;
if (tmp!=chip_index) {
msg_perr("Dual bios: Chip selection failed.\n");
} else msg_pinfo("Dual bios: Selected chip: %d\n",tmp&1);
free(portpos);
} exit_conf_mode_ite(port); break;
Hello Vadim!
Someone has tested a refinement of your patch with an ITE 8728 and it (still) worked fine. I'd like to request a sign-off from you in case we want to eventually integrate it. (see http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure for details). Thanks!
-- Kind regards/Mit freundlichen Grüßen, Stefan Tauner
On 07/20/2013 05:44 AM, Stefan Tauner wrote:
Hi Stefan!
Signed-off-by: Vadim Girlin vadimgirlin@gmail.com
Is it sufficient to add it here or do I need to resend the patch with sign-off?
Vadim
On Sat, 20 Jul 2013 16:33:03 +0400 Vadim Girlin vadimgirlin@gmail.com wrote:
That's fine. I was just wanting to make sure it is ok with you :) thanks!
10 Aug 10 Aug
New subject: [PATCH] IT87: Add ability to select between chips on	GIGABYTE DualBIOS boards.
Thanks to Vadim Girlin for finding out how to do that The patent describing the overall implementation of DualBIOS can be found here: http://www.google.com/patents/US6892323 This is known to work on GA-MA770-UD3, GA-B75M-D3V, GA-B75N and GA-H61M-S1 (only M_BIOS is populated).
Signed-off-by: Vadim Girlin vadimgirlin@gmail.com Signed-off-by: Damien Zammit damien@zamaudio.com Signed-off-by: Stefan Tauner stefan.tauner@student.tuwien.ac.at Tested-by: Damien Zammit damien@zamaudio.com Tested-by: Anton Kochkov anton.kochkov@gmail.com --- flashrom.8 | 13 +++++++++++++ internal.c | 5 ++--- it87spi.c | 47 ++++++++++++++++++++++++++++++++++++++++------- 3 files changed, 55 insertions(+), 10 deletions(-)
diff --git a/flashrom.8 b/flashrom.8 index dccfd1a..c52542a 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -315,6 +315,19 @@ do not match, it will refuse to write the image unless you specify .TP .B ITE IT87 Super I/O .sp +If your mainboard is manufactured by GIGABYTE and supports DualBIOS it is very likely that it uses an +ITE IT87 series Super I/O to switch between the two flash chips. Only one of them can be accessed at a time +and you can manually select which one to use with the +.sp +.B " flashrom -p internal:dualbiosindex=chip" +.sp +syntax where +.B chip +is the index of the chip to use (0 = main, 1 = backup). You can check which one is currently selected by +leaving out the +.B chip +parameter. +.sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. If you want to set the I/O base port of the IT87 series SPI controller manually instead of diff --git a/internal.c b/internal.c index ab3c81f..30b184f 100644 --- a/internal.c +++ b/internal.c @@ -331,9 +331,8 @@ int internal_init(void) return ret;
#if defined(__i386__) || defined(__x86_64__) -	/* Probe unconditionally for IT87* LPC->SPI translation and for -	* IT87* Parallel write enable. -	*/ +	/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and +	* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ init_superio_ite(); #endif
diff --git a/it87spi.c b/it87spi.c index 8e4e0ad..dbba7b4 100644 --- a/it87spi.c +++ b/it87spi.c @@ -27,6 +27,7 @@
#include <string.h> #include <stdlib.h> +#include <errno.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -36,7 +37,7 @@ #define ITE_SUPERIO_PORT1	0x2e #define ITE_SUPERIO_PORT2	0x4e
-uint16_t it8716f_flashport = 0; +static uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ static int fast_spi = 1;
@@ -124,10 +125,40 @@ static const struct spi_programmer spi_programmer_it87xx = { static uint16_t it87spi_probe(uint16_t port) { uint8_t tmp = 0; -	char *portpos = NULL; uint16_t flashport = 0;
enter_conf_mode_ite(port); +	+	char *param = extract_programmer_param("dualbiosindex"); +	if (param != NULL) { +	sio_write(port, 0x07, 0x07); /* Select GPIO LDN */ +	tmp = sio_read(port, 0xEF); +	if (*param == '\0') { /* Print current setting only. */ +	free(param); +	} else { +	char *dualbiosindex_suffix; +	errno = 0; +	long chip_index = strtol(param, &dualbiosindex_suffix, 0); +	free(param); +	if (errno != 0 || *dualbiosindex_suffix != '\0' || chip_index < 0 || chip_index > 1) { +	msg_perr("DualBIOS: Invalid chip index requested.\n"); +	exit_conf_mode_ite(port); +	return 1; +	} +	if (chip_index != (tmp & 1)) { +	msg_pdbg("DualBIOS: Previous chip index: %d\n", tmp & 1); +	sio_write(port, 0xEF, (tmp & 0xFE) | chip_index); +	tmp = sio_read(port, 0xEF); +	if ((tmp & 1) != chip_index) { +	msg_perr("DualBIOS: Chip selection failed.\n"); +	exit_conf_mode_ite(port); +	return 1; +	} +	} +	} +	msg_pinfo("DualBIOS: Selected chip: %d\n", tmp & 1); +	} + /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; /* Check if LPC->SPI translation is active. */ @@ -163,11 +194,11 @@ static uint16_t it87spi_probe(uint16_t port) flashport |= sio_read(port, 0x65); msg_pdbg("Serial flash port 0x%04x\n", flashport); /* Non-default port requested? */ -	portpos = extract_programmer_param("it87spiport"); -	if (portpos) { +	param = extract_programmer_param("it87spiport"); +	if (param) { char *endptr = NULL; unsigned long forced_flashport; -	forced_flashport = strtoul(portpos, &endptr, 0); +	forced_flashport = strtoul(param, &endptr, 0); /* Port 0, port >0x1000, unaligned ports and garbage strings * are rejected. */ @@ -180,7 +211,8 @@ static uint16_t it87spi_probe(uint16_t port) msg_perr("Error: it87spiport specified, but no valid " "port specified.\nPort must be a multiple of " "0x8 and lie between 0x100 and 0xff8.\n"); -	free(portpos); +	exit_conf_mode_ite(port); +	free(param); return 1; } else { flashport = (uint16_t)forced_flashport; @@ -190,7 +222,7 @@ static uint16_t it87spi_probe(uint16_t port) sio_write(port, 0x65, (flashport & 0xff)); } } -	free(portpos); +	free(param); exit_conf_mode_ite(port); it8716f_flashport = flashport; if (internal_buses_supported & BUS_SPI) @@ -228,6 +260,7 @@ int init_superio_ite(void) case 0x8716: case 0x8718: case 0x8720: +	case 0x8728: ret |= it87spi_probe(superios[i].port); break; default:
-- Kind regards, Stefan Tauner