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This application is a continuation application of U.S. patent application Ser. No. 13/855,637 filed Apr. 2, 2013, now allowed, which is a continuation of U.S. patent application Ser. No. 12/591,165 filed Nov. 10, 2009, now U.S. Pat. No. 8,445,921, which is a continuation of U.S. patent application Ser. No. 11/978,680 filed Oct. 30, 2007, now U.S. Pat. No. 7,649,210, which is a continuation of U.S. patent application Ser. No. 10/975,095 filed Oct. 28, 2004, now U.S. Pat. No. 7,691,650, which is a divisional of U.S. patent application Ser. No. 10/179,010 filed Jun. 26, 2002, now U.S. Pat. No. 6,841,802, all of which are incorporated by reference in their entirety for all purposes as if fully set forth herein.
A passivation layer, beneficially about a 1000 Å-thick SiO2 or SixNy layer, can be located on the blue-LED element, but in such a manner that the p and n contact pads are exposed. The passivation layer can be formed using PECVD, sputtering, electron beam evaporation, or coating with a material, such as epoxy or flowable Si02. PECVD is particularly beneficial in that it provides protected sidewalls. Spin-coating is a useful method of material coating. The passivation layer can then be patterned to expose the p and n contact pads using photolithography and a suitable etchant (such a BOE, HF, and/or photo-resist stripping).
The vertical GaN-based LED 54 has advantages in that step etching is not required. However, to locate the n-metal contact 56 below the GaN buffer layer 55, the sapphire substrate (not shown) that is used for initial GaN growth is removed. Sapphire substrate removal using laser lift-off is known, reference U.S. Pat. No. 6,071,795 to Cheung et al., entitled, "Separation of Thin Films From Transparent Substrates By Selective Optical Processing," issued on Jun. 6, 2000, and Kelly et al. "Optical process for liftoff of group HI-nitride films", Physica Status Solidi (a) vol. 159, 1997, pp. R3-R4). Furthermore, highly advantageous methods of fabricating GaN semiconductor layers on sapphire (or other insulating and/or hard) substrates are taught in U.S. patent application Ser. No. 10/118,317 entitled "A Method of Fabricating Vertical Devices Using a Metal Support Film" and filed on Apr. 9, 2002 by Myung Cheol Yoo, and in U.S. patent application Ser. No. 10/118,316 entitled "Method of Fabricating Vertical Structure" and filed on Apr. 9, 2002 by Lee et al. Additionally, a method of etching GaN and sapphire (and other materials) is taught in U.S. patent application Ser. No. 10/118,318 entitled "A Method to Improve Light Output of GaN-Based Light Emitting Diodes" and filed on Apr. 9, 2002 by Yeom et al., all of which are hereby incorporated by reference as if fully set forth herein.
wherein the phosphor layer is parallel to the n-GaN layer and has a two-digit micrometer thickness.
wherein the conductive substrate comprises at least one of Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al, or alloys thereof.
3. The vertical light emitting diode structure of claim 1, further comprising a reflective layer between the p-electrode and the p-GaN layer.
4. The vertical light emitting diode structure of claim 1, wherein the phosphor layer is an integral element of the chip, and not part of a package.
5. The vertical light emitting diode structure of claim 1, wherein the phosphor layer is patterned.
6. The vertical light emitting diode structure of claim 1, wherein the phosphor layer comprises various materials that emit light of different colors.
7. The vertical light emitting diode structure of claim 1, further comprising an n-electrode pad to bond a wire on the n-electrode coupled to the n-GaN layer through the phosphor layer.
8. The vertical light emitting diode structure of claim 7, wherein the phosphor layer contacts the n-electrode pad.
9. The vertical emitting diode structure of claim 1, wherein the passivation layer comprises at least one of SiO2, SiN, Si3N4, or epoxy, and has a four-digit angstrom thickness.
10. The vertical emitting diode structure of claim 1, wherein the n-electrode comprises at least one of Ti or Al.
wherein the phosphor layer is thicker than the GaN based semiconductor structure.
12. The vertical light emitting diode structure of claim 11, wherein the phosphor layer comprises different phosphor materials that emit light of different colors.
13. The vertical light emitting diode structure of claim 11, wherein the phosphor layer is thicker than the passivation layer.
14. The vertical light emitting diode structure of claim 11, wherein the conductive substrate comprises at least one of Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al, or alloys thereof.
wherein the passivation layer includes an opening on a top surface of n-GaN layer such that the opening accommodates at least a portion of the n-electrode.
wherein the phosphor layer is thicker than the passivation layer.
17. The vertical light emitting diode structure of claim 15, wherein the phosphor layer is thicker than the passivation layer.
a wavelength converting layer on the passivation layer.
wherein both the opening of the wavelength converting layer and the opening of the passivation layer overlap each other.
wherein a space where both the opening of the wavelength converting layer and the opening of the passivation layer overlap each other is filled with the transparent layer.
wherein the second-type semiconductor layer is a p-type semiconductor layer.
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