Q: 1Hz pulse generator - LVCMOS 1.8 output I am pretty new to electronic design so sorry in advance if the question is too naive.
I need to build a small portable 1Hz pulse generator and connect it to a FPGA input pin, configured in LVCMOS 1.8V. This is supposed to emulate a GPS PPS signal for testing purpose, without requiring a GPS signal/antenna.
Currently my plan is to use a 9V battery and use a 555 timer to build the pulses.
This part is OK, and I have successfully simulated it with LTSpice to verify my resistances and capacitors values meet the desired frequency and duty cycle.
The step where I'm stuck is how to interface it cleanly to the FPGA, and be 100% sure I won't damage it.
I have tried with an LDO (LT3021-1.8) after the 555, but the simulation tells that the rising edge goes up to 3V for a small amount of time before stabilizing at 1.8V.
Remembering my electronics lessons, I tried a divider (with two resistances) and a LM358 configured in follower.
The results are a little better but the simulation still shows a rise to 2.4V during the rising edge.
I discovered there are specific component called "voltage shifter" that could  be appropriate for what I'm looking after, but I'm having a hard time finding one with LVCMOS 1.8V output, and that I can solder by myself.
Do you have any suggestion for a component that would fit the purpose ?
Would a Zener diode help to limit the output to 1.8 V ?
Also, for running the simulation I need to simulate the load of the FPGA input pin, but cannot find such information in the datasheet (this is a  Xilink Z7000). What would be a correct way to simulate this load (what impedance) ?

A: You could use something like a 74LVC541 with 1.8V Vcc as a buffer. Its inputs are 5 V tolerant.
Alternatively build an oscillator around a 74LVC14A and get rid of the 555 and higher voltages altogether.

A: You might try just putting a resister between the +5 from the timer and the op amp.  The op amp will have built-in protective diodes that need to be protected from too much fault current.  The max fault current may be quite high however.  Check the data sheet and size the resister to limit the current well below that.


A: If your FPGA is not finalized, or if you've got a spare test point available, try synthesizing the 1 Hz in the FPGA and driving an LVCMOS output, then jumpering the two points for test purposes.
