Others have attempted to solve this problem by proposing a heat sink molded into the plastic package. See for example U. S. Pat. No. 6,646,339. Its FIGS. 2B and 3 are representative of a typical internal heat sink. A half etched lead frame 170 has a heat sink pedestal 180 with half etched sections 150. Heat is transferred via thermal conduction from the bottom of the die 20 to the pedestal 110 where it is dissipated in the ambient environment of the device 13. One drawback of such an arrangement is that heat generated near the surface of the die 20 and travels through the thickness of the die before reaching the heat sink pedestal 110. However, the location of the heat sink at the bottom increases the assembly cost and there is not too much heat dissipated from the top of the package.
One solution to the problem or removing heat from the top surface of a die is proposed in U. S. Pat. No. 6,844,622. See its FIGS. 5, 6 and 7. That patent describes heat sinks 53, 63, and 73 that are located above the upper surface of a semiconductor die. All those heat sinks have an exposed external surface and an internal surface member that contacts or is in thermal conduction with the top surface of the die.
FIG. 2 b is sectional view of the assembled upper heat sink taken along the line 2 b-2 b′of FIG. 2 a.
FIG. 2 d is a sectional view take view of the assembled upper heat sink taken along the line of 2 c-2 c′of FIG. 2 a.
The upper heat sink is assembled onto a lead frame 20 and semiconductor device 30 as shown in FIGS. 2 a-2 c. The lead frame has opposite side rails 21, 22, a number of input and output lead pads 24.1-24.8 along edges parallel to the side rails 21, 22 and tie bars 23.1-23.4. The tie bars are on the other two edges of the lead frame and connect any one lead frame to adjacent lead frames. Those skilled in the art understand that multiple lead frames are held together with side rails and tie bars and such lead frame assemblies commonly have four to six die pads for receiving semiconductor devices or integrated circuits. The lead frames are temporarily held together by the tie bars located between die attach pads. After molding is completed, the individual packaged devices are separated from each other by severing the tie bars. The lead frame 20 may be a half etched lead frame that provides a lower heat sink 50 as an integral part of a die attach pad 31 as shown in FIGS. 2 or 3.
The semiconductor device 30 is secured to the die attach pad 31 by epoxy or solder 25. The support arms 18.1-18.4 are connected respectively to the tie bars 23.1-23.4. The input/output pads 24.1-24.4 are disposed along one edge of the lead frame and the other input/output pads 24.5-25.8 are disposed along the opposite edge. Bond wires (not shown) extend between contact pads (not shown) on the periphery of the semiconductor or integrated circuit to the input/output pads of the lead frame. 20. For example, see FIG. 3 where input/output pad 24.5 is connected to the device 30 through bond wires 32 and 33. Other wire bond connections are shown but reference numbers are omitted to render the figure more understandable. That figure also shows the lower heat sink 50 and the connections of the support arms 18.1-18.4 to the respective tie bars 23.1-23.4. In larger packages, the tie bars may be located in the comers. Tie bar location is determined by the type of package (double or quad sided) and is not related to package size. See for example FIG. 4 where the tie bars are in the comers in order to provide more space around the periphery for input/output pads.
an upper heat sink connected to the leadframe, said upper heat sink having a planar member with a protruding surface, said protruding surface contacting the upper surface of the semiconductor device and said upper heat sink exposed to dissipate heat from the semiconductor device.
2. The packaged semiconductor device of claim 1 wherein the lead frame comprises a lower heat sink.
3. The packaged semiconductor device of claim 1 wherein the upper heat sink has one or more support members extending from the upper heat sink to the lead frame.
4. The packaged semiconductor device of claim 1 wherein the lead frame has four comer tie bars and the support members of the upper heat sink are connected to the tie bars.
5. The packaged semiconductor device of claim 1 wherein the semiconductor device comprises one of the group consisting of integrated circuits, systems on chip, and discrete devices.
6. The packaged semiconductor device of claim 1 wherein the planar member of the upper heat sink further comprises an annular ring with an inner boundary surrounding the protruding surface.
7. The packaged semiconductor device of claim 6 wherein the upper heat sink further comprises wall members extending from the inner boundary of the annular ring to the contact surface of the protruding surface.
8. The packaged semiconductor device of claim 1 wherein the upper heat sink comprises a metal comprising copper or aluminum.
9. The packaged semiconductor device of claim 1 wherein the lead frame is a half etched lead frame with a lower pedestal heat sink on the die pad for holding the die.
a molded upper heat sink connected to the leadframe, said upper heat sink having a planar member with a protruding surface, said protruding surface contacting the upper surface of the semiconductor device and said upper heat sink exposed to dissipate heat from the semiconductor device.
11. The double exposed semiconductor device of claim 10 wherein the upper heat sink is connected by one or more support members extending from the planar member to the half etched lead frame.
12. The double exposed semiconductor device of claim 11 wherein the half etched lead frame has four comer tie bars and the support members of the upper heat sink are connected to the tie bars.
13. The double exposed semiconductor device of claim 10 wherein half etched lead frame has a plurality of input and output pads and the semiconductor device is electrically connected to the input and output pads by bond wires.
14. The double exposed semiconductor device of claim 10 wherein the semiconductor device comprises one of the group consisting of integrated circuits, systems on chip, and discrete devices.
15. The double exposed semiconductor device of claim 10 wherein planar member of the upper heat sink further comprises an annular ring with an inner boundary surrounding the protruding surface.
16. The double exposed semiconductor device of claim 15 wherein the upper heat sink further comprises wall members extending from the inner boundary of the annular ring to the contact surface of the protruding surface.
17. The double exposed semiconductor device of claim 10 wherein the upper heat sink comprises a metal comprising copper or aluminum.
upper heat sink means disposed above the semiconductor device, connected to the surface of the semiconductor device and to the leadframe, and a surface exposed to ambient environment for dissipating heat from the semiconductor device.
19. The packaged semiconductor device of claim 18 wherein the upper heat sink means comprises a thermal conductive material.
20. The packaged semiconductor device of claim 18 wherein the upper heat sink means comprises a plate attached to the top of the semiconductor device and a plurality of arms connected to the lead frame.
21. The packaged semiconductor device of claim 18 wherein the lead frame has a plurality of severed tie bars and the arms are connected to the severed tie bars.
22. The packaged semiconductor device of claim 18 wherein the mold resin surrounds the exposed surface of the upper heat sink means.
24. The method of claim 23 wherein the lead frame comprises multiple central die regions and corresponding input and output pads disposed between opposite side rails and the further comprising the step of simultaneously encapsulating the multiple dies and then separating the encapsulated dies from each other.
25. The method of claim 23 wherein the lead frame has tie bars and each support arm of the upper heat sink is connected to a tie bar.