Q: VHDL - Want to create a simple divider I'm using Vivado 2018.2
I want to make a simple divider, say the input is 153 and the constant is 53. So with 153/53, I want to see 2 and the remainder 47.
The code I have so far errors out (sequential).
entity divider_main is
    port(
            dividend: in std_logic_vector(7 downto 0);
            remainder: out std_logic_vector(5 downto 0);    
            quotient: out std_logic_vector(2 downto 0)
         ); 
end divider_main;

architecture Behavioral of divider_main is

signal dividend_signal: signed(7 downto 0);
signal remainder_signal: std_logic_vector(5 downto 0);
signal fifty_three: signed(7 downto 0);
signal count: unsigned(2 downto 0);

begin
    dividend_signal <= signed(dividend);
    fifty_three <= "00011101";
    count <= "000";
    process(dividend, dividend_signal) is 
        begin
        if dividend_signal < fifty_three then
            remainder(5 downto 0) <= std_logic_vector(dividend_signal(5 downto 0));
            quotient <= std_logic_vector(count);
            dividend_signal <= "00000000";
            count(2 downto 0) <= "000";
        else
            count <= count + 1;
            dividend_signal <= dividend_signal - fifty_three;
            quotient(2 downto 0) <= "000";
            remainder <= "000000";
        end if;
    end process;
end Behavioral;

I'm new to vhdl so let me know what I am doing wrong!
