Interconnects for data transfers consume a significant fraction of overall circuit power. We showed that high-level synthesis has a significant impact on the interconnect power consumption. We presented a comprehensive study of interconnect-aware high-level synthesis for low power. A method for estimating data transfer power consumption at the RTL was proposed. Using this method, RTL interconnect power is taken into consideration during high-level synthesis for low power. Since binding has a great impact on the interconnect topology and switching activity, we adopted two metrics to guide binding for low power. Moreover, we presented extended signal gating techniques to suppress SSA in interconnects as well as DPUs. Experimental results demonstrate the benefits of incorporating interconnect-awareness into high-level synthesis for low power and the effectiveness of the proposed techniques. Our techniques are general and can be easily incorporated into other high-level synthesis systems. Because the underlying tool, SCALP, is only applicable to data-dominated behaviors, the benchmarks used in this paper were data-dominated. Nevertheless, our techniques are equally applicable to control-flow intensive behaviors.