Q: How does power dissipation for surface mount components work? I know that with usual through hole components we can attach heatsinks etc. But how does it work with surface mount components? Is having a copper plate around the component the way to go? How do we go about calculating the area required?
In particular I am looking at this SO8 package surface mount switching power MOSFET IRF7452(datasheet). I am sure that it requires an external form of heatsinking other than its case. But I don't seem to see it written anywhere on the datasheet? How do you know how much maximum heat energy can be dissipated using the case of the MOSFET itself? How does one go about designing the heatsinking for something like this? Would the copper plane be connected to the ground? Which part of the chip will contact and transfer most of the heat? 

A: SMT components are usually heat-sunk to a copper plane or a copper pour on the PCB.  Ground and power planes are usually the largest copper pours, so it's nice to be able to heat sink to them.  But that's not always possible, and additional copper pours need to be created.
In some case certain pins are better for heat sinking than others.   For example, in this power MOSFET, drain pins provide heat sinking.  As far as I know, all MOSFETs in SOIC are arranged like that.
 (source Fig.5 in the application note)
Electrically, the drain is usually not connected to power or ground, and a separate copper pour needs to be created for heat sinking.
The area of the copper pour sets the thermal resistance between the outside of component and ambient air.  Some data on PCB heat sinking can be found in the LM317 datasheet pp. 15-17
Here's my own example of PCB heat sink.  A 7805 voltage regulator in TO-252 (U4) is heat sunk to a 2-layer PCB. Fortunately, the thermal pad on 7805 is connected to ground.  So, I can use the ground copper pours for heat sinking.
Top layer 
Bottom layer 
Manual for the SMPS controller's evaluation board is another source of layout guidelines.  (Not just thermal management.  SMPSes can be layout sensitive.)
Further reading
Fairchild (now part of On Semiconductor) application note Maximum Power Enhancement Techniques for SO-8 Power MOSFETs
TI application note Semiconductor and IC package thermal metrics

A: In general, usually the heat is conducted out the leadframe, either through a thermal pad on the bottom of the package or through the leads. The thermal resistance can vary enormously from one part type to another, even for nominally similar components, due to differences in construction and materials used in the leadframe. 
In the case of your IRF part, the datasheet shows the \$\theta_{JA}\$ as 50°C/W under specified conditions. 

However, the note that we'd expect to find on page 8 of the datasheet is not there, so we don't know. Another similar part says (reference is to note 4 in that case, IRF7401)

Okay, so to figure out what you're actually going to get when your situation differs from the typical.. refer to information such as this IRF application note AN-994. 

That's based on a standard board design with 2-oz copper as follows: 

Refer to the application note for more information. 
2-oz copper is relatively thick, but you can also have situations where the part is on a 4-layer board with thermal vias conducting heat to internal planes, or even use aluminum core board. With SMD devices that, and the package, can make an order of magnitude difference in the ability to dissipate heat, especially with small packages such as SC-70.
Although the principles don't change, it's vitally important to use the exact parameters from the manufacturer and package type that you are actually using, because the variations can be quite large (for example from a Kovar to a copper leadframe).  
