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CPC Section H
CPC Class H03
CPC Subclass H03M
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Version: 2022.01
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COOPERATIVE PATENT CLASSIFICATION
H03M
CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C 4/00; optical analogue/digital converters G02F 7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) [2019-01]
The following IPC groups are not in the CPC scheme. The subject matter for these IPC groups is classified in the following CPC groups:
H03M7/32 covered by H03M 7/3002, H03M 7/3004, H03M 7/3006, H03M 7/3008, H03M 7/3011, H03M 7/3013, H03M 7/3015, H03M 7/3017, H03M 7/302, H03M 7/3024, H03M 7/3028, H03M 7/3031, H03M 7/3033, H03M 7/3035, H03M 7/3037, H03M 7/304, H03M 7/3042, H03M 7/3048
H03M7/34 covered by H03M 7/3051
H03M7/36 covered by H03M 7/3022, H03M 7/3026, H03M 7/3044
H03M7/44 covered by H03M 7/40
In this subclass non-limiting references (in the sense of paragraph 39 of the Guide to the IPC) may still be displayed in the scheme.
H03M 1/00
Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M 3/00) [2019-05]
H03M 1/001
{Analogue/digital/analogue conversion} [2013-01]
{Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed} [2019-01]
{Reconfigurable analogue/digital or digital/analogue converters (H03M 1/02 takes precedence)} [2013-01]
{among different converters types} [2013-01]
{among different resolutions} [2013-01]
{among different conversion characteristics, e.g. between mu-255 and a-laws} [2013-01]
Reversible analogue/digital converters [2013-01]
using stochastic techniques [2013-01]
Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M 1/10) [2013-01]
H03M 1/0602
{of deviations from the desired transfer characteristic (H03M 1/0617 takes precedence)} [2013-01]
{at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M 1/18)} [2013-01]
{Offset or drift compensation (removal of offset already present on the analogue input signal H03M 1/1295)} [2013-01]
{at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error} [2013-01]
{over the full range of the converter, e.g. for correcting differential non-linearity} [2013-01]
{of harmonic distortion (H03M 1/0617 takes precedence)} [2013-01]
{characterised by the use of methods or means not specific to a particular type of detrimental influence} [2013-01]
{by dividing out the errors, i.e. using a ratiometric arrangement} [2013-01]
{with auxiliary conversion of a value corresponding to the physical parameter(s) to be compensated for} [2013-01]
{by synchronisation} [2013-01]
{by filtering} [2013-01]
{Anti-aliasing} [2013-01]
{Smoothing} [2013-01]
{by averaging out the errors, e.g. using sliding scale} [2013-01]
{in the amplitude domain} [2013-01]
{using dither, e.g. using triangular or sawtooth waveforms (for increasing resolution H03M 1/201)} [2019-01]
{the dither being a random signal} [2013-01]
{in the spatial domain} [2013-01]
{by analogue redistribution among corresponding nodes of adjacent cells, e.g. using an impedance network connected among all comparator outputs in a flash converter} [2013-01]
{by arranging the quantisation value generators in a non-sequential pattern layout, e.g. symmetrical} [2013-01]
{by selecting the quantisation value generators in a non-sequential order, e.g. symmetrical} [2013-01]
{the order being based on measuring the error} [2013-01]
{in the time domain, e.g. using intended jitter as a dither signal} [2019-01]
{by calculating a running average of a number of subsequent samples} [2013-01]
{by continuously permuting the elements used, i.e. dynamic element matching} [2013-01]
{using clocked averaging} [2013-01]
{using data dependent selection of the elements, e.g. data weighted averaging} [2013-01]
{the selection being based on the output of noise shaping circuits for each element} [2013-01]
{using different permutation circuits for different parts of the digital signal} [2013-01]
{using random selection of the elements (with data-controlled random generator H03M 1/0665)} [2013-01]
{using redundancy} [2013-01]
{using additional components or elements, e.g. dummy components} [2013-01]
{the original and additional components or elements being complementary to each other, e.g. CMOS} [2013-01]
{using a differential network structure, i.e. symmetrical with respect to ground} [2013-01]
{using real and complementary patterns} [2013-01]
{using fault-tolerant coding, e.g. parity check, error correcting codes (H03M 1/069 takes precedence)} [2013-01]
{by range overlap between successive stages or steps} [2013-01]
{using a diminished radix representation, e.g. radix 1.95} [2013-01]
{using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type} [2019-01]
{in time, e.g. using additional comparison cycles} [2013-01]
of noise {(H03M 1/0617 takes precedence)} [2013-01]
{of bubble errors, i.e. irregularities in thermometer codes} [2013-01]
{of clock feed-through} [2013-01]
{of electromagnetic or electrostatic field noise, e.g. preventing crosstalk by shielding or optical isolation} [2019-01]
{of phase error, e.g. jitter} [2013-01]
{of power supply variations, e.g. ripple} [2013-01]
{of quantisation noise} [2013-01]
{of switching transients, e.g. glitches} [2013-01]
{by disabling changes in the output during the transitions, e.g. by holding or latching} [2013-01]
{by forcing a gradual change from one output level to the next, e.g. soft-start} [2013-01]
{of temperature variations} [2013-01]
Calibration or testing [2013-01]
{without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated (H03M 1/1009, H03M 1/1071 take precedence)} [2013-01]
{Calibration} [2013-01]
{at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M 1/18)} [2013-01]
{by storing a corrected or correction value in a digital look-up table} [2013-01]
{Offset correction (H03M 1/1019 takes precedence; removal of offset already present on the analogue input signal H03M 1/1295)} [2013-01]
{at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M 1/18)} [2013-01]
{by storing corrected or correction values in one or more digital look-up tables (H03M 1/1057 takes precedence)} [2013-01]
{the look-up table containing corrected values for replacing the original digital values (H03M 1/1052 takes precedence)} [2013-01]
{using an auxiliary digital/analogue converter for adding the correction values to the analogue signal (H03M 1/1052 takes precedence)} [2013-01]
{using two or more look-up tables each corresponding to a different type of error, e.g. for offset, gain error and non-linearity error respectively} [2013-01]
{by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values} [2013-01]
{using digitally programmable trimming circuits} [2013-01]
{Mechanical or optical alignment} [2013-01]
{Measuring or testing} [2013-01]
{Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit} [2013-01]
{Converters having special provisions for facilitating access for testing purposes} [2013-01]
{using domain transforms, e.g. Fast Fourier Transform} [2013-01]
{for dc performance, i.e. static testing (H03M 1/1085 takes precedence)} [2013-01]
{for ac performance, i.e. dynamic testing (H03M 1/1085 takes precedence)} [2013-01]
Analogue/digital converters ({H03M 1/001 – } H03M 1/10 take precedence) [2019-01]
{Multiplexed conversion systems} [2013-01]
{Interleaved, i.e. using multiple converters or converter parts for one channel} [2013-01]
{using time-division multiplexing} [2013-01]
{Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages} [2019-01]
{Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters} [2013-01]
{Non-linear conversion not otherwise provided for in subgroups of H03M 1/12} [2013-01]
{Sampling or signal conditioning arrangements specially adapted for A/D converters} [2019-01]
{Details of sampling arrangements or methods} [2013-01]
{Asynchronous, i.e. free-running operation within each conversion cycle} [2019-01]
{Synchronisation of the sampling frequency or phase to the input frequency or phase} [2013-01]
{Multi-rate systems, i.e. adaptive to different fixed sampling rates} [2013-01]
{Non-uniform sampling} [2013-01]
{at intervals varying with the rate of change of the input signal} [2013-01]
{at extreme values only} [2013-01]
{at random intervals, e.g. digital alias free signal processing [DASP]} [2013-01]
{Synchronous circular sampling, i.e. using undersampling of periodic input signals} [2013-01]
{Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling (H03M 1/18 takes precedence); Out-of-range indication} [2013-01]
{Clamping, i.e. adjusting the DC level of the input signal to a predetermined value} [2013-01]
Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit [2013-01]
{in which at least one step is of the folding type; Folding stages therefore} [2013-01]
{the reference generators for the steps being arranged in a common two-dimensional array} [2013-01]
{in pattern-reading type converters, e.g. having both absolute and incremental tracks on one disc or strip (H03M 1/16 takes precedence)} [2013-01]
{the steps being performed sequentially in a single stage, i.e. recirculation type (H03M 1/141, H03M 1/143, H03M 1/16 take precedence)} [2013-01]
{the steps being performed sequentially in series-connected stages (H03M 1/141, H03M 1/143, H03M 1/16 take precedence)} [2013-01]
{all stages being simultaneous converters} [2013-01]
{at least two of which share a common reference generator} [2013-01]
{the reference generator being arranged in a two-dimensional array} [2013-01]
with scale factor modification, i.e. by changing the amplification between the steps {(H03M 1/141 takes precedence)} [2013-01]
{in pattern-reading type converters, e.g. with gearings} [2013-01]
{the steps being performed sequentially in a single stage, i.e. recirculation type (H03M 1/161 takes precedence)} [2013-01]
{the steps being performed sequentially in series-connected stages (H03M 1/161 takes precedence)} [2013-01]
{in which two or more residues with respect to different reference levels in a stage are used as input signals for the next stage, i.e. multi-residue type} [2013-01]
{all stages comprising simultaneous converters (H03M 1/165 takes precedence)} [2013-01]
{and delivering the same number of bits} [2013-01]
Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging [2013-01]
{in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values} [2013-01]
{the feedback signal controlling the reference levels of the analogue/digital converter} [2013-01]
{the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter} [2013-01]
{the determination of the range being based on more than one digital output value, e.g. on a running average, a power estimation or the rate of change} [2013-01]
{in feedforward mode, i.e. by determining the range to be selected directly from the input signal} [2013-01]
{using an auxiliary analogue/digital converter} [2013-01]
{Multi-path, i.e. having a separate analogue/digital converter for each possible range} [2013-01]
Increasing resolution using an n bit system to obtain n + m bits [2013-01]
{by dithering} [2013-01]
{by interpolation} [2013-01]
{using an analogue interpolation circuit} [2013-01]
{in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators} [2013-01]
{using resistor strings for redistribution of the original reference signals or signals derived therefrom} [2013-01]
{using a logic interpolation circuit} [2013-01]
{using a digital interpolation circuit} [2013-01]
{by prediction} [2013-01]
pattern-reading type [2017-08]
using relatively movable reader and disc or strip [2013-01]
{Constructional details of parts relevant to the encoding mechanism, e.g. pattern carriers, pattern sensors} [2019-01]
with weighted coding, i.e. the weight given to a digit depends on the position of the digit within the block or code word, e.g. there is a given radix and the weights are powers of this radix [2013-01]
with non-weighted coding [2013-01]
{of the pattern-shifting type, e.g. pseudo-random chain code} [2013-01]
{of the unit Hamming distance type, e.g. Gray code} [2013-01]
{using gradually changing slit width or pitch within one track; using plural tracks having slightly different pitches, e.g. of the Vernier or nonius type} [2013-01]
incremental [2013-01]
{Circuits or methods for processing the quadrature signals} [2013-01]
{for detecting the direction of movement} [2013-01]
{for waveshaping} [2013-01]
{with additional pattern means for determining the absolute position, e.g. reference marks} [2013-01]
using cathode-ray tubes {or analoguous two-dimensional deflection systems} [2013-01]
Analogue value compared with reference values (H03M 1/48 takes precedence) [2013-01]
{for direct conversion to a residue number representation} [2013-01]
simultaneously only, i.e. parallel type [2019-01]
{having a separate comparator and reference value for each quantisation level, i.e. full flash converter type} [2013-01]
{the reference values being generated by a resistive voltage divider} [2013-01]
{the voltage divider taps being held in a floating state, e.g. by feeding the divider by current sources} [2013-01]
{the voltage divider being a single resistor string} [2013-01]
{using current mode circuits, i.e. circuits in which the information is represented by current values rather than by voltage values} [2013-01]
{Non-linear conversion} [2013-01]
{having a single comparator per bit, e.g. of the folding type} [2013-01]
sequentially only, e.g. successive approximation type (converting more than one bit per step H03M 1/14) [2013-01]
recirculation type [2013-01]
{using switched capacitors} [2013-01]
Sequential comparisons in series-connected stages with no change in value of analogue signal [2013-01]
Sequential comparisons in series-connected stages with change in value of analogue signal [2013-01]
{the stages being of the folding type} [2013-01]
with digital/analogue converter for supplying reference values to converter [2013-01]
{Details of the control circuitry, e.g. of the successive approximation register} [2013-01]
{in which the input S/H circuit is merged with the feedback DAC array} [2013-01]
Servo-type converters [2013-01]
{for position encoding, e.g. using resolvers or synchros} [2013-01]
with intermediate conversion to time interval (H03M 1/64 takes precedence) [2019-01]
{using tapped delay lines} [2013-01]
{using pulse width modulation} [2013-01]
{the pulse width modulator being of the charge-balancing type} [2013-01]
{the pulse width modulator being of the self-oscillating type} [2013-01]
Input signal integrated with linear return to datum [2013-01]
Input signal sampled and held with linear return to datum [2013-01]
Input signal compared with linear ramp [2013-01]
Non-linear conversion [2013-01]
with intermediate conversion to frequency of pulses [2013-01]
with intermediate conversion to phase of sinusoidal {or similar periodical} signals [2013-01]
{for position encoding, e.g. using resolvers or synchros (H03M 1/485 takes precedence)} [2013-01]
Digital/analogue converters ({H03M 1/001 – } H03M 1/10 take precedence) [2019-01]
{Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing} [2013-01]
{with intermediate conversion to phase of sinusoidal or similar periodical signals} [2013-01]
{Recirculation type} [2013-01]
{Servo-type converters} [2013-01]
with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits [2013-01]
{both converters being of the unary decoded type} [2013-01]
{the quantisation value generators of both converters being arranged in a common two-dimensional array} [2013-01]
{Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type} [2013-01]
Automatic control for modifying converter range [2013-01]
Sequential conversion in series-connected stages (H03M 1/68 takes precedence) [2013-01]
Simultaneous conversion [2013-01]
{using current sources as quantisation value generators} [2013-01]
{with weighted currents} [2013-01]
{with equal currents which are switched by unary decoded digital signals} [2013-01]
using switching tree [2013-01]
{using a single level of switches which are controlled by unary decoded digital signals} [2013-01]
using ladder network [2013-01]
{using resistors, i.e. R-2R ladders} [2013-01]
using weighted impedances (H03M 1/76 takes precedence) [2013-01]
{using capacitors, e.g. neuron-mos transistors, charge coupled devices} [2013-01]
{with charge redistribution} [2013-01]
{with equally weighted capacitors which are switched by unary decoded digital signals} [2013-01]
{using resistors} [2013-01]
with intermediate conversion to time interval [2013-01]
{by comparing the input signal with a digital ramp signal} [2013-01]
{in which the total pulse width is distributed over multiple shorter pulse widths} [2013-01]
Conversion of analogue values to or from differential modulation [2013-01]
Delta modulation, i.e. one-bit differential modulation {(H03M 3/30 takes precedence)} [2013-01]
{with adaptable step size, e.g. adaptive delta modulation [ADM]} [2013-01]
{using syllabic companding, e.g. continuously variable slope delta modulation [CVSD]} [2013-01]
Differential modulation with several bits {, e.g. differential pulse code modulation [DPCM] (H03M 3/30 takes precedence)} [2019-01]
{with adaptable step size, e.g. adaptive differential pulse code modulation [ADPCM]} [2013-01]
{Delta-sigma modulation} [2019-01]
{In group branch H03M 3/30, in the absence of an indication to the contrary, classification is made in the first appropriate place.}
{with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed} [2013-01]
{Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, e.g. by using stored correction values, H03M 3/378)} [2013-01]
{characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement} [2013-01]
{by averaging out the errors} [2013-01]
{using dither} [2013-01]
{the dither being in the time domain} [2019-05]
{the dither being at least partially dependent on the input signal} [2019-05]
{in particular a pseudo-random signal} [2013-01]
{by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M 1/066)} [2013-01]
{by chopping} [2013-01]
{by double sampling, e.g. correlated double sampling} [2013-01]
{by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing} [2013-01]
{by suppressing active signals at predetermined times, e.g. muting, using non-overlapping clock phases} [2013-01]
{using return-to-zero signals} [2013-01]
{of deviations from the desired transfer characteristic} [2013-01]
{at one point, i.e. by adjusting a single reference value, e.g. bias or gain error} [2019-01]
{Offset or drift compensation (removal of offset already present on the analogue input signal H03M 3/494)} [2013-01]
{of non-linear distortion, e.g. instability (avoiding instability by structural design H03M 3/44)} [2013-01]
{by temporarily adapting the operation upon detection of instability conditions} [2013-01]
{in feedback mode, e.g. by reducing the order of the modulator} [2013-01]
{by resetting one or more loop filter stages} [2013-01]
{in feed-forward mode, e.g. using look-ahead circuits} [2013-01]
{of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators} [2013-01]
{Compensation or reduction of delay or phase error} [2013-01]
{Jitter reduction} [2013-01]
{Relaxation of settling time constraints, e.g. slew rate enhancement} [2013-01]
{Prevention or reduction of switching transients, e.g. glitches} [2013-01]
{Testing} [2013-01]
{at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error} [2019-01]
{Offset correction (removal of offset already present on the analogue input signal H03M 3/494)} [2014-07]
{by storing corrected or correction values in one or more digital look-up tables} [2014-07]
{Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M 7/3004)} [2013-01]
{Arrangements for selecting among plural operation modes, e.g. for multi-standard operation} [2013-01]
{among different orders of the loop filter} [2013-01]
{among different frequency bands} [2013-01]
{among different converter types} [2013-01]
{Arrangements for handling quadrature signals, e.g. complex modulators} [2013-01]
{Arrangements specific to bandpass modulators} [2013-01]
{characterised by the type of bandpass filters used} [2013-01]
{by the use of a pair of integrators forming a closed loop} [2013-01]
{by the use of an LC circuit} [2013-01]
{combined with modulation to or demodulation from the carrier} [2013-01]
{characterised by the number of quantisers and their type and resolution} [2013-01]
{having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type} [2013-01]
{all these quantisers being multiple bit quantisers} [2013-01]
{all these quantisers being single bit quantisers} [2013-01]
{having multiple quantisers arranged in parallel loops} [2013-01]
{having one quantiser only} [2013-01]
{the quantiser being a multiple bit one} [2013-01]
{the quantiser being a successive approximation type analogue/digital converter} [2013-01]
{with lower resolution, e.g. single bit, feedback} [2013-01]
{the quantiser being a single bit one} [2013-01]
{the quantiser being a pulse width modulation type analogue/digital converter, i.e. differential pulse width modulation} [2013-01]
{with multi-level feedback} [2013-01]
{characterised by the order of the loop filter, e.g. error feedback type} [2013-01]
In this group branch the order of the loop filters is considered to be the number of integrators for a baseband modulator and the number of resonators for a bandpass modulator respectively
{the modulator having a higher order loop filter in the feedforward path} [2013-01]
{with provisions for rendering the modulator inherently stable} [2019-05]
In this subgroup, classification is made both here and in H03M 3/478 if both subgroups are relevant
{by restricting the swing within the loop, e.g. gain scaling} [2013-01]
{using non-linear elements, e.g. limiters} [2013-01]
{by a particular choice of poles or zeroes in the z-plane, e.g. by positioning zeroes outside the unit circle, i.e. causing the modulator to operate in a chaotic regime} [2013-01]
{by removing part of the zeroes, e.g. using local feedback loops} [2013-01]
{with distributed feedforward inputs, i.e. with forward paths from the modulator input to more than one filter stage} [2013-01]
{with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input} [2013-01]
{with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage} [2013-01]
{the modulator having a first order loop filter in the feedforward path} [2013-01]
{Analogue/digital converters using delta-sigma modulation as an intermediate step} [2013-01]
{using a combination of at least one delta-sigma modulator in series with at least one analogue/digital converter of a different type} [2013-01]
{Details relating to the decimation process (decimation filters in general H03H 17/0416, H03H 17/0621)} [2013-01]
{Details of the digital/analogue conversion in the feedback path} [2013-01]
{Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters} [2013-01]
{Shared, i.e. using a single converter for multiple channels} [2013-01]
{Non-linear conversion systems} [2013-01]
{Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication} [2019-05]
In this subgroup, classification is made both here and in H03M 3/44 if both subgroups are relevant
{characterised by the type of range control, e.g. limiting} [2013-01]
{by adapting the quantisation step size} [2013-01]
{by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path} [2013-01]
{by adapting the input gain} [2013-01]
{using automatic control} [2013-01]
{in feed forward mode, i.e. by determining the range to be selected directly from the input signal} [2013-01]
{Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems} [2019-01]
{Variable sample rate} [2013-01]
{Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M 7/3004)} [2013-01]
{Details of the final digital/analogue conversion following the digital delta-sigma modulation} [2013-01]
{the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC} [2013-01]
{the final digital/analogue converter being constituted by a pulse width modulator} [2013-01]
{Details relating to the interpolation process} [2019-01]
{Automatic control for modifying converter range} [2013-01]
Conversion of the form of the representation of individual digits [2019-01]
In groups H03M 5/02 - H03M 5/22, in the absence of an indication to the contrary, an invention is classified in the last appropriate place.
{In this main group, additional information has been classified systematically for documents published from 01-04-2004 onwards.}
Conversion to or from representation by pulses [2013-01]
the pulses having two levels [2013-01]
Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell [2013-01]
Code representation by pulse width [2013-01]
Code representation by pulse frequency [2013-01]
Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code [2013-01]
Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code [2013-01]
{Conversion to or from block codes or representations thereof} [2013-01]
the pulses having three levels [2013-01]
two levels being symmetrical with respect to the third level, i.e. balanced bipolar ternary code [2013-01]
the pulses having more than three levels [2013-01]
Conversion to or from representation by sinusoidal signals [2013-01]
Conversion of a code where information is represented by a given sequence or number of digits to a code where the same {, similar or subset of} information is represented by a different sequence or number of digits [2019-01]
In groups H03M 7/001 - H03M 7/50, the last place priority rule is applied, i.e. at each hierarchical level, in the absence of an indication to the contrary, classification is made in the last appropriate place.
In groups H03M 7/02 – H03M 7/50, in the absence of an indication to the contrary, an invention is classified in the last appropriate place.
{In this main group, in the absence of an indication to the contrary, additional information has been classified systematically for documents published from 01-04-2004 onwards.}
{characterised by the elements used} [2013-01]
{using thin film devices} [2013-01]
{using superconductive devices} [2013-01]
{using magnetic elements, e.g. transfluxors} [2013-01]
{using semiconductor devices} [2019-01]
{using diodes} [2013-01]
{using resistive or capacitive elements} [2013-01]
{using opto-electronic devices} [2018-05]
Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word [2013-01]
the radix thereof being two [2013-01]
the radix thereof being a positive integer different from two [2013-01]
the radix being ten, i.e. pure decimal code [2013-01]
the radix thereof being negative [2013-01]
having two radices, e.g. binary-coded-decimal code [2013-01]
Conversion to or from non-weighted codes [2013-01]
Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code [2013-01]
{Conversion to or from thermometric code} [2013-01]
Conversion to or from residue codes [2013-01]
Conversion to or from n-out-of-m codes [2019-01]
to or from one-out-of-m codes [2013-01]
Conversion to or from floating-point codes [2013-01]
Conversion to or from stochastic codes [2013-01]
Programmable structures, i.e. where the code converter contains apparatus which is operator-changeable to modify the conversion process [2013-01]
Compression (speech analysis-synthesis for redundancy reduction G10L 19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction [2019-01]
{Conversion to or from differential modulation} [2019-01]
{In group branch H03M 7/3002, additional information has been systematically classified for all documents.}
{Digital delta-sigma modulation} [2019-01]
{Compensating for, or preventing of, undesired influence of physical parameters} [2019-01]
{by averaging out the errors, e.g. using dither} [2019-01]
{of non-linear distortion, e.g. by temporarily adapting the operation upon detection of instability conditions (avoiding instability by structural design H03M 7/3035)} [2019-01]
{Non-linear modulators} [2019-01]
{Structural details of digital delta-sigma modulators} [2019-01]
{characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path} [2019-01]
In this group the order of the loop filters is considered to be the number of integrators for a baseband modulator and the number of resonators for a bandpass modulator respectively
{the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs} [2019-01]
{with provisions for rendering the modulator inherently stable, e.g. by restricting the swing within the loop, by removing part of the zeroes using local feedback loops, by positioning zeroes outside the unit circle causing the modulator to operate in a chaotic regime} [2019-01]
{the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only} [2019-01]
{Conversion to or from differential modulation with several bits only, i.e. the difference between successive samples being coded by more than one bit, e.g. differential pulse code modulation [DPCM] (H03M 7/3004 takes precedence; voice coding G10L 19/00; image coding H04N 19/00)} [2019-01]
{adaptive, e.g. adaptive differential pulse code modulation [ADPCM]} [2019-01]
{Conversion to or from one-bit differential modulation only, e.g. delta modulation [DM] (H03M 7/3004 takes precedence)} [2019-01]
{adaptive, e.g. adaptive delta modulation [ADM]} [2019-01]
{Block-compounding PCM systems} [2013-01]
{Conversion to or from Modulo-PCM} [2013-01]
{Distributed Source coding, e.g. Wyner-Ziv, Slepian Wolf} [2013-01]
{Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression} [2013-01]
{Compressive sampling or sensing} [2013-01]
{Segmenting} [2013-01]
{by means of a mask or a bit-map} [2013-01]
{Precoding preceding compression, e.g. Burrows-Wheeler transformation} [2013-01]
{Prediction} [2013-01]
{Time} [2013-01]
{Space} [2013-01]
{Sorting} [2013-01]
{Context modeling} [2013-01]
{Vector coding (for television signals, see H04N 19/94)} [2014-11]
{using adaptive string matching, e.g. the Lempel-Ziv method} [2013-01]
{employing a sliding window, e.g. LZ77} [2013-01]
{employing the use of a dictionary, e.g. LZ78} [2013-01]
{Data deduplication} [2013-01]
{using fixed length segments} [2013-01]
{using variable length segments} [2013-01]
{Grammar codes} [2013-01]
Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code [2013-01]
{Conversion to or from arithmetic code} [2013-01]
{Binary arithmetic codes} [2013-01]
{Context adapative binary arithmetic codes [CABAC]} [2013-01]
{constant length to or from Morse code conversion} [2013-01]
{Fixed length to variable length coding} [2013-01]
{Prefix coding} [2013-01]
{Adaptive prefix coding} [2013-01]
{Tree adaptation} [2013-01]
{Coding table selection} [2013-01]
{Coding table adaptation} [2013-01]
{Parameterized codes} [2013-01]
{Golomb codes} [2013-01]
{Static prefix coding} [2013-01]
{Encoding of a tuple of symbols} [2013-01]
{Variable length to variable length coding} [2013-01]
using table look-up for the coding or decoding process, e.g. using read-only memory {(H03M 7/4006 takes precedence)} [2013-01]
{for the decoding process only} [2013-01]
Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind [2013-01]
alternating with other codes during the code conversion process, e.g. run-length coding being performed only as long as sufficientlylong runs of digits of the same kind are present [2013-01]
Conversion to or from non-linear codes, e.g. companding [2013-01]
{Compression Theory, e.g. compression of random number, repeated compression} [2013-01]
{General implementation details not specific to a particular type of compression} [2013-01]
{Decoder aspects} [2013-01]
{Encoder aspects} [2013-01]
{Methods or arrangements to increase the throughput} [2013-01]
{Parallelization} [2013-01]
{Pipelining} [2013-01]
{Handling of unkown probabilities} [2013-01]
{Compression optimized for errors} [2013-01]
{Power optimization with respect to the encoder, decoder, storage or transmission} [2013-01]
{Synchronisation of encoder and decoder} [2013-01]
{Saving memory space in the encoder or decoder} [2013-01]
{Selection of Compressor} [2013-01]
{Selection between different types of compressors} [2013-01]
{Selection between compressors of the same type} [2013-01]
{Selection strategies} [2013-01]
{according to the data type} [2013-01]
{according to reasons other than compression rate or data type} [2019-01]
{Type of the data to be coded, other than image and sound} [2013-01]
{Software} [2013-01]
{Unicode} [2013-01]
{Structured documents, e.g. XML} [2019-01]
Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C 19/00) [2013-01]
H03M 11/00
Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys (keyboard switch arrangements, structural association of coders and keyboards H01H 13/70, H03K 17/94) [2019-01]
{In this main group additional information has been classified systematically for documents published from 01-01-2013 onwards.}
H03M 11/003
{Phantom keys detection and prevention} [2013-01]
{Measures for preventing unauthorised decoding of keyboards} [2013-01]
Details [2013-01]
Coding of multifunction keys [2013-01]
by operating the multifunction key itself in different ways [2013-01]
by operating selected combinations of multifunction keys [2013-01]
by methods based on duration or pressure detection of keystrokes [2013-01]
by operating a key a selected number of consecutive times whereafter a separate enter key is used which marks the end of the series [2013-01]
by using additional keys, e.g. shift keys, which determine the function performed by the multifunction key [2013-01]
wherein the shift keys are operated after the operation of the multifunction keys [2013-01]
wherein the shift keys are operated before the operation of the multifunction keys [2013-01]
Dynamic coding, i.e. by key scanning (H03M 11/26 takes precedence) [2013-01]
Static coding (H03M 11/26 takes precedence) [2013-01]
using analogue means {, e.g. by coding the states of multiple switches into a single multi-level analogue signal or by indicating the type of a device using the voltage level at a specific tap of a resistive divider} [2019-01]
using opto-electronic means [2013-01]
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes (error detection or error correction for analogue/digital, digital/analogue or code conversion H03M 1/00 – H03M 11/00 specially adapted for digital computers G06F 11/08, for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B 20/18, for static stores G11C) [2019-01]
Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes [2013-01]
{Simulation or testing of codes, e.g. bit error rate [BER] measurements} [2019-01]
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words [2013-01]
{Theoretical methods to calculate these checking codes} [2013-01]
{Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error} [2013-01]
using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M 13/2906 takes precedence)} [2013-01]
Arithmetic codes [2019-01]
Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit [2019-01]
{Parallel or block-wise CRC computation} [2013-01]
{CRC update after modification of the information word} [2013-01]
{Error detection codes other than CRC and single parity bit codes} [2013-01]
{Checksums} [2013-01]
{using single parity bit} [2013-01]
using multiple parity bits [2013-01]
H03M 13/1102
{Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes} [2013-01]
{Decoding} [2013-01]
{Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping} [2013-01]
{Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms} [2013-01]
{Merged schedule message passing algorithm with storage of sums of check-to-bit node messages or sums of bit-to-check node messages, e.g. in order to increase the memory efficiency} [2013-01]
{using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule} [2013-01]
{with correction functions for the min-sum rule, e.g. using an offset or a scaling factor} [2013-01]
{storing only the first and second minimum values per check node} [2013-01]
{using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs} [2013-01]
{Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations} [2013-01]
{Scheduling of bit node or check node processing} [2013-01]
{Full parallel processing, i.e. all bit nodes or check nodes are processed in parallel} [2013-01]
{Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel} [2013-01]
{Shuffled, staggered, layered or turbo decoding schedules} [2013-01]
{using trapping sets} [2013-01]
{Pipelined decoding at code word level, e.g. multiple code words being decoded simultaneously} [2013-01]
{Structural properties of the code parity-check or generator matrix} [2013-01]
{Algebraically constructed LDPC codes, e.g. LDPC codes derived from Euclidean geometries [EG-LDPC codes] (H03M 13/116, H03M 13/1174 take precedence)} [2013-01]
{Low-density parity-check convolutional codes [LDPC-CC]} [2013-01]
{Low-density generator matrices [LDGM]} [2013-01]
{Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices} [2013-01]
{Array based LDPC codes, e.g. array codes} [2013-01]
{QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]} [2013-01]
{wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices} [2013-01]
{Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes} [2013-01]
{Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes} [2016-08]
{Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively} [2013-01]
{Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure (H03M 13/1165 takes precedence)} [2013-01]
{wherein the structure of the parity-check matrix is obtained by reordering of a random parity-check matrix} [2013-01]
{wherein the parity-check matrix comprises a part with a double-diagonal} [2013-01]
{wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three} [2013-01]
{Codes on graphs other than LDPC codes} [2013-01]
{Repeat-accumulate [RA] codes} [2013-01]
{Irregular repeat-accumulate [IRA] codes} [2013-01]
Linear codes [2013-01]
{Algebraic geometric codes, e.g. Goppa codes} [2019-01]
{Non-binary linear block codes not provided for otherwise} [2013-01]
{Reed-Muller [RM] codes} [2013-01]
{Codes linear in a ring, e.g. Z4-linear codes or Nordstrom-Robinson codes} [2013-01]
Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes (H03M 13/17 takes precedence) [2013-01]
{Golay Codes} [2019-01]
{using error location or error correction polynomials} [2013-01]
{Reed-Solomon codes} [2019-01]
{Bose-Chaudhuri-Hocquenghem [BCH] codes} [2013-01]
{Determination and particular use of error location polynomials} [2013-01]
{using the Berlekamp-Massey algorithm} [2013-01]
{using the Euclid algorithm} [2013-01]
{Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial} [2013-01]
{Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial} [2013-01]
{Shortening or extension of codes} [2013-01]
{Pipelined decoder implementations} [2013-01]
{Encoding or decoding using time-frequency transformations, e.g. fast Fourier transformation} [2013-01]
{Decoding beyond the bounded minimum distance [BMD]} [2013-01]
{Polynomial evaluation, i.e. determination of a polynomial sum at a given value} [2013-01]
{Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance} [2013-01]
{Finite field arithmetic processing} [2019-01]
{Determination of error values} [2013-01]
{Remainder calculation, e.g. for encoding and syndrome calculation} [2019-01]
{Parallel or block-wise remainder calculation} [2013-01]
Burst error correction, e.g. error trapping, Fire codes [2013-01]
{Error trapping or Fire codes} [2019-01]
Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes [2019-01]
Non-linear codes, e.g. m-bit data word to n-bit code word [mBnB] conversion with error detection or error correction [2018-05]
using convolutional codes, e.g. unit memory codes [2013-01]
{Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding} [2019-01]
Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] {(modulation codes H03M 13/31)} [2013-01]
{with block coding} [2013-01]
{with concatenated codes} [2013-01]
{with Low Density Parity Check [LDPC] codes} [2013-01]
{with trellis coding, e.g. with convolutional codes and TCM} [2013-01]
{with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]} [2013-01]
using interleaving techniques [2013-01]
{the interleaver involving at least two directions} [2013-01]
{Simple row-column interleaver, i.e. pure block interleaving} [2013-01]
{Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations} [2013-01]
{Turbo interleaver for 3rd generation partnership project [3GPP] universal mobile telecommunications systems [UMTS], e.g. as defined in technical specification TS 25.212} [2013-01]
{the interleaver involves 3 or more directions} [2013-01]
{the interleaver involves a diagonal direction, e.g. by using an interleaving matrix with read-out in a diagonal direction} [2013-01]
{Turbo interleaver for 3rd generation partnership project 2 [3GPP2] mobile telecommunication systems, e.g. as defined in the 3GPP2 technical specifications C.S0002} [2013-01]
{Helical type interleaver} [2013-01]
{Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver} [2016-08]
{Interleaver using powers of a primitive element, e.g. Galois field [GF] interleaver} [2013-01]
{Permutation polynomial interleaver, e.g. quadratic permutation polynomial [QPP] interleaver and quadratic congruence interleaver} [2013-01]
{Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators} [2013-01]
{S-random interleaver} [2013-01]
{Interleaver wherein the permutation pattern is obtained using a congruential operation of the type y=ax+b modulo c} [2013-01]
{Almost regular permutation [ARP] interleaver} [2013-01]
{Interleaver with an interleaving rule not provided for in the subgroups H03M 13/2703 - H03M 13/2753} [2013-01]
{Interleaving address generation} [2013-01]
{Circuits therefore} [2013-01]
{Interleaver wherein the permutation pattern or a portion thereof is stored} [2013-01]
{Internal interleaver for turbo codes (H03M 13/2714 and H03M 13/2725 take precedence)} [2013-01]
{Contention or collision free turbo code internal interleaver} [2013-01]
{Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices} [2013-01]
{Interleaver implementations, which reduce the amount of required interleaving memory} [2013-01]
{Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location} [2013-01]
{Interleaver providing variable interleaving, e.g. variable block sizes} [2013-01]
{Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing} [2013-01]
{Two or more interleaving operations are performed jointly, e.g. the first and second interleaving operations defined for 3GPP UMTS are performed jointly in a single interleaving operation} [2013-01]
combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes [2013-01]
{Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes} [2019-01]
{using block codes (H03M 13/2957 takes precedence)} [2013-01]
{Product codes} [2019-01]
{omitting parity on parity} [2013-01]
{with an error detection code in one dimension} [2013-01]
{with error correction codes in three or more dimensions, e.g. 3-dimensional product code where the bits are arranged in a cube} [2013-01]
{wherein error correction coding involves a diagonal direction} [2013-01]
{Cross interleaved Reed-Solomon codes [CIRC]} [2013-01]
{Decoding strategies} [2013-01]
{with erasure setting} [2013-01]
{using a block and a convolutional code (H03M 13/2957 takes precedence)} [2019-01]
{comprising an outer Reed-Solomon code and an inner convolutional code} [2013-01]
{using convolutional codes (H03M 13/2957 takes precedence)} [2013-01]
{wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits} [2013-01]
{using at least three error correction codes (H03M 13/2957 takes precedence)} [2013-01]
{Iterative decoding (H03M 13/2957 takes precedence)} [2013-01]
{using iteration stopping criteria} [2013-01]
{using Picket codes or other codes providing error burst detection capabilities, e.g. burst indicator codes and long distance codes [LDC]} [2013-01]
{Turbo codes and decoding} [2013-01]
This group covers also aspects when a component code is replaced by a non-coded constraint, e.g. like in joint turbo decoding and detection
{Particular turbo code structure} [2013-01]
this group covers hybrid parallel and serial concatenated turbo code structures and other unusual code structures that do not fit into H03M 13/2963 - H03M 13/2972
{Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes} [2013-01]
{Turbo codes concatenated with another code, e.g. an outer block code} [2013-01]
{Non-binary turbo codes} [2013-01]
{Serial concatenation using convolutional component codes} [2013-01]
{Judging correct decoding, e.g. iteration stopping criteria} [2019-01]
{Particular arrangement of the component decoders} [2013-01]
{using as many component decoders as component codes} [2013-01]
{using less component decoders than component codes, e.g. multiplexed decoders and scheduling thereof} [2013-01]
{using more component decoders than component codes, e.g. pipelined turbo iterations} [2013-01]
{Turbo codes with short blocks} [2013-01]
{Implementing the return to a predetermined state, i.e. trellis termination} [2013-01]
{Tail biting} [2013-01]
combining coding for error detection or correction and efficient use of the spectrum (without error detection or correction H03M 5/14 {, H03M 5/145}) [2017-08]
Synchronisation based on error coding or decoding [2019-01]
Groups H03M 13/333 - H03M 13/336 are not complete pending reclassification; see also this group
{Synchronisation on a multi-bit block basis, e.g. frame synchronisation} [2019-01]
{Phase recovery} [2013-01]
Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics [2013-01]
{Adaptation to the channel} [2019-01]
{Unequal error protection [UEP]} [2013-01]
Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M 13/03 - H03M 13/35 [2016-05]
{Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code} [2019-01]
{Adaptation to the number of estimated errors or to the channel state} [2013-01]
{using means or methods for the initialisation of the decoder} [2013-01]
{with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes} [2013-01]
{with judging correct decoding} [2013-01]
{with iterative decoding} [2013-01]
{using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes} [2013-01]
{using symbol combining, e.g. Chase combining of symbols received twice or more} [2013-01]
{using a re-encoding step during the decoding process} [2013-01]
{for soft-output decoding of block codes} [2013-01]
{for decoding of real number codes} [2013-01]
Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes [2013-01]
{Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding} [2021-01]
{Correction factor, e.g. approximations of the exp(1+x) function} [2021-01]
{for block codes using a trellis or lattice} [2021-01]
{Add-Compare-Select [ACS] operation in forward or backward recursions} [2021-01]
{Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs} [2021-01]
{Decoding in probability domain} [2021-01]
{Tail-biting (H03M 13/2996 takes precedence)} [2021-01]
{for block codes, especially trellis or lattice decoding thereof} [2019-01]
{using a collapsed trellis, e.g. M-step algorithm, radix-n architectures with n>2} [2013-01]
{using a trellis with a reduced state space complexity, e.g. M-algorithm or T-algorithm} [2013-01]
{Arrangements of methods for branch or transition metric calculation} [2013-01]
{based on architectures providing a highly parallelized implementation, e.g. based on systolic arrays} [2013-01]
{using sliding window techniques or parallel windows} [2013-01]
{using sequential decoding, e.g. the Fano or stack algorithms} [2013-01]
{for non-binary convolutional codes} [2013-01]
{for rate k/n convolutional codes, with k>1, obtained by convolutional encoders with k inputs and n outputs} [2013-01]
{using state pinning or decision forcing, i.e. the decoded sequence is forced through a particular trellis state or a particular set of trellis states or a particular decoded symbol} [2013-01]
using the Viterbi algorithm or Viterbi processors [2013-01]
{implementing add, compare, select [ACS] operations} [2013-01]
{list output Viterbi decoding} [2013-01]
{implementing the return to a predetermined state} [2013-01]
{tail biting Viterbi decoding} [2013-01]
{soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions} [2013-01]
{soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding} [2013-01]
{two-step SOVA decoding, i.e. the soft-output is determined by a second traceback operation after the determination of the hard decision like in the Berrou decoder} [2013-01]
{implementing path management} [2013-01]
{using traceback (H03M 13/4192 takes precedence)} [2013-01]
{using a plurality of RAMs, e.g. for carrying out a plurality of traceback implementations simultaneously} [2013-01]
{using register-exchange (H03M 13/4192 takes precedence)} [2013-01]
{using combined traceback and register-exchange} [2013-01]
Majority logic or threshold decoding [2013-01]
Soft decoding, i.e. using symbol reliability information (H03M 13/41 takes precedence) [2013-01]
{using a set of candidate code words, e.g. ordered statistics decoding [OSD]} [2019-01]
{wherein the candidate code words are obtained by an algebraic decoder, e.g. Chase decoding} [2013-01]
{using a set of erasure patterns or successive erasure decoding, e.g. generalized minimum distance [GMD] decoding} [2013-01]
{wherein all the code words of the code or its dual code are tested, e.g. brute force decoding} [2013-01]
{by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result} [2013-01]
Error detection, forward error correction or error protection, not provided for in groups H03M 13/01 - H03M 13/37 [2016-05]
Unidirectional error detection or correction [2013-01]
Constant weight codes; n-out-of-m codes; Berger codes [2013-01]
Codes using Fibonacci numbers series [2013-01]
{Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise} [2019-01]
{Specific encoding aspects, e.g. encoding by means of decoding} [2013-01]
{Aspects specific to channel or signal-to-noise ratio estimation (H03M 13/63 takes precedence)} [2013-01]
{Use of the dual code} [2013-01]
{Use of computational or mathematical techniques} [2013-01]
{Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations} [2013-01]
{Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials} [2013-01]
{Shortening and extension of codes} [2013-01]
{Joint error correction and other techniques (H03M 13/31 and H03M 13/33 take precedence)} [2013-01]
{Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy (H03M 13/3761, H03M 13/3769 and H03M 13/635 take precedence)} [2019-01]
{Error control coding in combination with data compression} [2013-01]
{using variable length codes} [2013-01]
{Error control coding in combination with demodulation} [2013-01]
{Error control coding in combination with equalisation} [2013-01]
{Error control coding in combination with channel estimation} [2013-01]
{Error control coding in combination with techniques for partial response channels, e.g. recording} [2013-01]
{Error control coding in combination with rate matching} [2013-01]
{by repetition or insertion of dummy data, i.e. rate reduction} [2013-01]
{by puncturing} [2013-01]
{using rate compatible puncturing or complementary puncturing} [2013-01]
{Rate compatible punctured convolutional [RCPC] codes} [2013-01]
{Rate compatible punctured turbo [RCPT] codes} [2013-01]
{Complementary punctured convolutional [CPC] codes} [2013-01]
{Rate compatible low-density parity check [LDPC] codes} [2013-01]
{Purpose and implementation aspects} [2013-01]
{Reduction of hardware complexity or efficient processing} [2013-01]
{Memory efficient implementations} [2013-01]
{Flexibility, adaptability, parametrability and configurability of the implementation} [2013-01]
{Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding} [2013-01]
{Support of multiple code types, e.g. unified decoder for LDPC and turbo codes} [2013-01]
{Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields} [2013-01]
{Support of multiple transmission or communication standards} [2013-01]
{Intended application, e.g. transmission or communication standard} [2013-01]
{3GPP LTE including E-UTRA} [2013-01]
{IEEE 802.11 [WLAN]} [2013-01]
{3GPP HSDPA, e.g. HS-SCCH or DS-DSCH related} [2013-01]
{ITU 992.X [ADSL]} [2013-01]
{GSM GPRS} [2013-01]
{ATSC VBS systems} [2013-01]
{DVB-H and DVB-M} [2013-01]
{IEEE 802.16 (WIMAX and broadband wireless access)} [2013-01]
{TCP, UDP, IP and associated protocols, e.g. RTP} [2013-01]
{UWB OFDM} [2013-01]
{DVB-T2} [2013-01]
{DVB-C2} [2013-01]
{3GPP2} [2013-01]
{Parallelized implementations} [2013-01]
{Implementations using multi-port memories} [2013-01]
{Implementations concerning memory access contentions} [2013-01]
{Implementation on processors, e.g. DSPs, or software implementations} [2013-01]
{Implementations using a tree structure, e.g. implementations in which the complexity is reduced by a tree structure from O(n) to O (log(n))} [2013-01]
{Implementations based on combinatorial logic, e.g. Boolean circuits} [2019-01]
{Representation or format of variables, register sizes or word-lengths and quantization} [2013-01]
{Scaling by multiplication or division} [2013-01]
{Normalization other than scaling, e.g. by subtraction} [2013-01]
{Modulo/modular normalization, e.g. 2's complement modulo implementations} [2013-01]
{Compression or short representation of variables} [2013-01]
{Truncation, saturation and clamping} [2013-01]
{Non-linear quantization} [2013-01]
{Implementations using analogue techniques for coding or decoding, e.g. analogue Viterbi decoder} [2013-01]
Subject matter not provided for in other groups of this subclass [2013-01]