diagnostic informations are available via SPI.
Programmable soft start function to drive loads with higher inrush current .
pins of GND must be externally connected.
pins of OUT11 must be externally connected.
GND to output). This output is over-current and open load protected.
Power supply voltage (external reverse protection required.
pins of VS must be externally connected.
significant bit (LSB, bit 0) is transferred first.
Chip select not input/test mode.
to CSN pin the L9950 will be switched into a test mode.
Half bridge output 4,5,6: see OUT1 (pin 3).
pins of OUT4 (OUT5, respectively) must be externally connected.
OUT11 by an external PWM signal.
Program and other relevant quality document.
1. HBM according to CDF-AEC-Q100-002.
2. HBM with all unzapped pins grounded.
VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified.
Switching from standby to active mode.
after CSN going to high.
Value of input capacity is not measured in production test. Parameter guaranteed by design.
Tj=-40 °C/+25 °C: SPI communication @2 MHZ.
Tj=+125 °C: SPI communication @1.25 MHZ.
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
5 V) is used for the logic part and the SPI of the device.
and the status registers are cleared.
be achieved. If bit 23 is set, the device will be switched to active mode.
21 V), the outputs OUT1 to OUT11 are switched to high impedance state to protect the load.
programmed state (input register 0: bit 20=0).
a shorted output to GND and low battery voltage.
changing the mechanical/electrical state of the loads.
is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
more precise by measuring the load current. The current monitor output is bidirectional (c.f.
used to dim two lamps independently by external PWM signals.
before the opposite driver will start to conduct.
the bulb) until the load reaches operating condition.
output data is changed from the high to low transition of CLK.
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
is implemented to avoid an activation of the output stages by a wrong communication frame.
falling edge of the CLK will shift the next bit out.
falling edge of the CLK signal.
frame. Bit 1-17 controls the behavior of the corresponding driver.
frame (rising edge of CSN).
available to measure the internal bandgap voltage, the TW and TSD thresholds.
current from VS to GND.
signals to the DO output.
will be switched in active mode.
and the output is switched off.
21 of Input Data Register 0).
even if this bit is set to zero.
are controlled by PWM1 input.
Updated Table 22: PowerSSO-36 mechanical data.