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Modeling concepts for digital and analog hardware. Co-modeling of software and hardware. Hardware description languages - VHDL, SystemVerilog, SystemC - description styles, simulation engines, synthesizability. Digital systems synthesis at different abstraction levels. Simulation and synthesis using modern design tools.
Annotatsioon - Digitaal- ja analoogriistvara modelleerimise alused. Tark- ja riistvara koos-modelleerimine. Riistvara kirjelduskeeled - VHDL, SystemVerilog, SystemC - kirjeldus-stiilid, simulatsiooniskeemid, sünteesitavus. Digitaal-süsteemide süntees erinevatel abstraktsioonitasemetel. Simuleerimine ja süntees tänapäevaste disainivahenditega.
• õpetada tööstuslike simuleerimis- ja sünteesivahendite kasutamist.
• Knowledge of phases, methods and tools of modern microchips and embedded systems design process; how to use various hardware description languages at these phases.
• Knowledge how to create models of digital systems in VHDL, SystemVerilog and SystemC, and how to use commercial simulation and synthesis tools.
• Kaasaegsete mikroskeemide ja sardsüsteemide projekteerimise põhietappide tundmine, oskus kasutada erinevaid riistvara kirjelduskeeli neil etappidel.
• Oskus luua digitaalseadmete mudeleid nii VHDL-s, SystemVerilog-s, kui ka SystemC-s, ning kasutada tööstuslikke simuleerimis- ja sünteesipakette.
To pass the course successfully, one must have basic knowledge of VHDL and C++ programming. Familiarity with UNIX/Linux environment is a plus for hands-on exercises.
Hands-on exercises - During hands-on exercises, different modeling and synthesis tasks are solved using various tools. The exercises cover the use of various hardware description languages to model digital and analog circuits. The exercises also cover synthesis of digital circuits using different technologies.
Prerequisites for the final exam - Reports of hands-on exercises must be presented and defended before exam.
Exam - On the exam, a student will answer to two questions covering all topics of the course - one question about hardware description languages and one about synthesis related issues.
Exam -- Requirement - lab reports accepted before the examination day.
Digital systems design - design-flow, automation.
Simulation of digital systems, simulation engines.
High-level synthesis - subtasks, examples.
Co-modeling and co-simulation of digital systems.
VHDL and register-transfer level synthesis.
Synthesis of digital systems at various abstraction levels.
Modeling of analog and mixed signal systems - SPICE, VHDL-AMS.
Code transformations at system and algorithmic levels.
NB! These are only some of the books at the library.
K.Tammemäe. Riistvara kirjeldamiskeel VHDL. TTÜ toimetus, 1992.
K.Tammemäe. Riistvara simuleerimisvahend - VHDL. Avutustehnika & Andmetöötlus (A&A), 4/1992.
K.Tammemäe. VLSI kõrgtaseme süntees. A&A, 1/1993.
K.Tammemäe. VHDL täna ja homme. A&A, 9/1993.
K.Tammemäe. Kas VHDL on sobiv keel sünteesiks. A&A, 7-8/1995.
P. Ellervee. Riistvara kirjelduskeel Verilog. A&A, 1/1998.
П. Н. Бибило (P.N.Bibilo). Основы VHDL языка (Osnovy VHDL jazyka). Солон-Р (Solon-R), 2000, ISBN 5-93455-056-X.
Plus newer editions of the same books, of course.
There exist hundreds of web-pages. Some to start with are below.
ModelSim PE Student Edition (Model Technology) - HDL simulator for students (limited design size but enough for term projects, Internet connection required to get license, only for MS Windows).
WebPACK (Xilinx) - tools to simulate and synthesize smaller designs (MS Windows & Linux-s).
GHDL and gtkWave - simulator and waveform viewer (MS Windows, Linux-s, etc., GPL - freeware & open-source).
Active-VHDL Simulation design environment (30-day trial license).