Configurable Graph-Based Task Solving with the Marco Multi-AI Agent Framework for Chip Design
Chip and hardware design presents numerous challenges stemming from its complexity and advancing technologies. These challenges result in longer turn-around time (TAT) for optimizing performance, power, area, and cost (PPAC) during synthesis, verification, physical design, and reliability loops.
Large language models (LLMs) have shown a remarkable capacity to comprehend and generate natural language at a massive scale, leading to many potential applications and benefits across various domains. Successful LLM-based AI agents for hardware design can drastically reduce TAT, leading to faster product cycles, lower costs, improved design reliability, and reduced risk of costly errors.
Figure 1. Marco framework overview
Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework
We introduce the proposed
Marco framework
, which encompasses graph-based task solving, agent configurations for sub-tasks, and skill/tool configurations for each AI agent in real time.
Figure 1 showed dynamic and static configurable graph-based task solving, which is flexibly integrated with chip-design knowledge (for example, circuits, timing, and so on).
In the task graph, each node represents a sub-task, and each edge represents the execution or knowledge relationship between nodes. For solving each sub-task, you use
Autogen
to configure single-AI or multi-AI agent with a knowledge database, tools, and memory.
Table 1 summarizes the task graph, agent, and LLM configurations of the Marco framework for various agents.
VerilogCoder
and the MCMM timing analysis agent use a dynamic task graph to complete the specification-to-RTL and extract key takeaways of timing reports, respectively. The timing path debug agent finds the problematic net, wire, and constraints through a static timing debugging task graph (Figure 1).
Agent works
Task category
Marco framework configuration
Task graph
Sub-task agent config.
Customized tools
RTLFixer
Code Syntax Fixing
N/A
Single-AI
RTL Syntax Error RAG Database
Standard Cell Layout Opt.
Optimization
N/A
Single-AI
Cluster Evaluator, Netlist Traverse Tool
MCMM Timing Analysis(Partition/Block-Level)
Summary & Anomaly Identification
Dynamic
Multi-AI
Timing Distribution Calculator, Timing Metric Comparator
DRC Coder
Code Generation
N/A
Multi-Modality & Multi-AI
Foundry Rule Analysis, Layout DRV Analysis, DRC Code Evaluation
Timing Path Debug(Path-Level)
Summary & Anomaly Identification
Static
Hierarchical Multi-AI
Agentic Timing Report Retrieval
VerilogCoder
Code Generation
Dynamic
Multi-AI
TCRG Retrieval Tool, AST-Based Waveform Tracing Tool
Table 1. Task graph, agent configuration, customized tool of the Marco framework for various autonomous agent implementations for hardware design tasks
In Table 1,
RTLFixer
and
Standard Cell Layout Optimization
agents (that is, a single-AI configuration) are supported using the Marco framework. The rest of the multi-AI agents are implemented on the Marco framework.
For
RTLFixer
,
LLM agent for standard cell layout optimization
, and
DRC Coder
, we used single-AI or multi-AI agent configurations with customized tools, memory, and domain knowledge.
Automated hardware description languages code generation
One key area where autonomous agents are making an impact is in the generation of hardware description languages (HDLs), such as Verilog. Due to the growing complexity of VLSI design, writing Verilog and VHDL is time-consuming and prone to bugs, necessitating multiple iterations for debugging functional correctness. Consequently, reducing design costs and designer effort for completing hardware specifications has emerged as a critical need.
LLMs can be used to generate Verilog code from natural language descriptions. However, LLMs often struggle to produce code that is both syntactically and functionally correct.
Syntax correctness
RTLFixer
uses a combination of retrieval-augmented generation (RAG) and ReAct prompting to enable LLMs to iteratively debug and fix syntax errors. RAG incorporates a database of human expert guidance to provide context for error correction. ReAct enables the LLM to reason about the error, plan a fix, and act on the plan.
Functional correctness
VerilogCoder
is a multi-agent system that incorporates a task planner and an abstract syntax tree (AST)-based waveform-tracing tool to generate and debug Verilog code. It employs a task and circuit relation graph (TCRG) to break down a task into manageable sub-tasks and link signal transitions to each step (Figure 2).
Figure 2. Task-driven circuit relation graph retrieval agent reasoning and interacting with the developed TCRG retrieval tool to enrich the task with the relevant circuit and signal descriptions
An AST-based waveform tracing tool assists the LLM agent in identifying and fixing functional errors by back-tracing signal waveforms. VerilogCoder achieves a 94.2% success rate on the VerilogEval-Human v2 benchmark, demonstrating a significant improvement over previous methods.
Video 1. Autonomously Complete Verilog Code with TCRG Planning and AST-Based Waveform Tracing Tools
In Video 1, the demonstration of VerilogCoder autonomously completes functionally correct Verilog code using TCRG planning and AST-based waveform tracing tools.
Automated DRC layout code generation
DRC-Coder
uses multiple autonomous agents with vision capabilities and specialized DRC and Layout DRV analysis tools to generate DRC code. The system interprets design rules from textual descriptions, visual illustrations, and layout representations. The multiple LLM agents include a planner that interprets design rules, and a programmer that translates the rules into executable code.
DRC-Coder incorporates an auto-debugging process, which uses feedback from the code evaluation to refine the generated code.
Video 2. A Demonstration of DRC-Coder in Chip Design
In Video 2, the demonstration of DRC-Coder generates DRC code that achieves perfect F1 scores on hundreds of testing layouts by leveraging a layout analysis tool, an auto-debugging process, and the capabilities of multi-modality and multi-AI agents.
DRC-Coder achieved a perfect F1 score of 1.000 in generating DRC codes for a sub-3nm technology node, outperforming standard prompting techniques. The proposed automated agentic approach significantly reduces the time required for DRC code generation, from weeks to an average of four minutes per design rule.
Standard cell layout optimization
LLM agent for standard cell layout optimization
proposes using the natural language and reasoning ability of an LLM to generate high-quality cluster constraints incrementally to optimize the cell layout PPA and debug the routability with ReAct prompting.
The system uses net information and cell layout analysis to group MOSFET devices into clusters. The AI agent not only achieves up to 19.4% smaller cell area, but also generates 23.5% more LVS and DRC clean cell layouts than the
Transformer-based device clustering approach
on a set of sequential cells in the industrial 2
nm
technology node.
Multi-corner multi-mode timing report debug and analysis
The multi-corner multi-mode (MCMM) timing analysis agent uses dynamic task graphs to complete the specification-to-RTL and extract key takeaways of timing reports, respectively.
The MCMM timing analysis agent achieves an average score of 8.33 out of 10, based on evaluations by experienced engineers on a set of industrial cases, and delivers approximately 60x speedups compared to human engineers (Figure 3).
Figure 3. MCMM timing analysis agent results
The timing path debug agent finds the problematic net, wire, and constraints through the static timing debugging task graph (Figure 1).
In Table 2, the timing path debug agent resolves 86% of path-level debugging tasks, whereas the standard task solving approach fails to resolve any of the tasks.
Multi Report Task Description
Required Analyzed
Sub-Tasks
Standard Task Solving
Timing Path Debug Agent
Find missing clk signals that have no rise/fall information
max, clk
X
V
Identify pairs of nets with high RC mismatch
max, wire
X
V
Detect unusual constraints between victim and its aggressors
max, xtalk, LC
X
V
Identify unusual RC values between victim and its aggressors
max, wire, xtalk, LC
X
V
Find the constraints of slowest stages with highest RC values
max, wire, xtalk, LC
X
V
Compare each timing table for number of stages, point values and timing mismatch
max
X
X
Task M2 and Task M3 for specific stages in list of paths
max, wire, xtalk, LC
X
V
Avg Pass-rate
0%
86%
Table 2. Pass-rate (%) of timing path debug agent with static task graph solving, and a naïve standard task solving without task graph information
X=Failed to solve the task. V=Solved the task successfully.
Conclusion
The proposed Marco framework enables more flexible and domain-specialized methods for real-time hardware design tasks solving. By using task graph and flexible single-AI and multi-AI agent configurations with domain-specific tools and knowledge, we developed various agents for tasks such as cell layout optimization, Verilog syntax error fixing, Verilog and DRC code generation, and timing debugging on problematic blocks, nets, and wires.
The experimental results show impressive performance and efficiency benefits on utilizing collaborative LLM-based agents for chip design.
The future directions for agent research on hardware design include the following:
Training LLMs with high-quality hardware design data
Improving LLM-based agents’ ability for hardware signal and waveform debugging
Incorporating PPA metrics into the design flow
Developing more efficient self-learning techniques and memory systems for LLM agents for solving more complex hardware tasks
For more papers and projects on electronic design automation, see the
NVIDIA Design Automation Research Group
page.
For those interested in the technologies highlighted in the post, here’s a list of relevant papers:
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
/NVlabs/RTLFixer
GitHub repo
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
/NVlabs/VerilogCoder
GitHub repo
DRC-Coder: Automated DRC Checker Code Generation using LLM Autonomous Agent
Large Language Model (LLM) for Standard Cell Layout Design Optimization
基于 Marco 多 AI 智能体框架的可配置图形任务求解在芯片设计中的应用
芯片和硬件设计因其复杂性和先进的技术而面临众多挑战。这些挑战导致在合成、验证、物理设计和可靠性循环期间优化性能、功耗、面积和成本（PPAC）的周转时间（TAT）更长。
大语言模型（LLMs）已显示出大规模理解和生成自然语言的出色能力，从而为各种领域带来许多潜在应用和优势。成功地将基于 LLMs 的 AI 智能体用于硬件设计，可以大幅减少 TAT，从而缩短产品周期、降低成本、提高设计可靠性，并降低代价高昂的错误风险。
图 1. Marco 框架概述
Marco：基于图形的可配置任务求解和多 AI 代理框架
我们介绍了拟议的 Marco 框架，其中包括基于图形的任务求解、子任务的智能体配置，以及每个 AI 智能体的实时技能/工具配置。
图 1 展示了基于动态和静态可配置图形的任务求解，可灵活集成芯片设计知识 (例如电路、定时等)。
在任务图中，每个节点代表一个子任务，每个边缘代表节点之间的执行或知识关系。为了解决每个子任务，您可以使用
Autogen
配置具有知识数据库、工具和内存的单个 AI 或多个 AI 代理。
表 1 总结了各种代理的 Marco 框架的任务图形、代理和 LLM 配置。
VerilogCoder
和 MCMM 时序分析代理使用动态任务图形分别完成对 RTL 的规范和提取时序报告的关键要点。定时路径调试代理通过静态定时调试任务图 (图 1) 查找有问题的网络、线和约束。
代理作品
任务类别
Marco 框架配置
任务图
子任务代理配置。
定制工具
RTLFixer
代码语法固定
不适用
单 AI
RTL 语法错误 RAG 数据库
Standard Cell Layout Opt.
优化
不适用
单 AI
Cluster Evaluator, Netlist Traverse Tool
MCMM 定时分析 (Partition/Block-Level)
总结和异常识别
动态
多 AI
Timing Distribution Calculator，Timing Metric Comparator
DRC Coder
代码生成
不适用
多模态和多 AI
Foundry Rule Analysis，Foundry 规则分析，Layout DRV Analysis，布局 DRV 分析，DRC Code Evaluation，DRC 代码评估
Timing Path Debug(Path-Level)
总结和异常识别
静态
分层多 AI
代理定时报告检索
VerilogCoder
代码生成
动态
多 AI
TCRG 检索工具，AST-Based Waveform Tracing Tool
表 1、任务图、代理配置、Marco 框架的定制工具，用于硬件设计任务的各种自主代理实现
在表 1 中，使用 Marco 框架支持
RTLFixer
和标准单元布局优化代理 (即单 AI 配置)。其余的多 AI 代理均在 Marco 框架上实施。
对于 RTLFixer、用于标准单元布局优化的 LLM 代理和 DRC Coder，我们使用了具有定制工具、内存和域知识的单 AI 或多 AI 代理配置。
自动硬件描述语言代码生成
自主智能体产生影响的一个关键领域是硬件描述语言（HDL）的生成，例如 Verilog。由于 VLSI 设计的复杂性与日俱增，编写 Verilog 和 VHDL 非常耗时且容易出现错误，因此需要进行多次迭代来调试功能正确性。因此，降低设计成本和设计师完成硬件规格的工作量已成为一项迫切需求。
LLM 可用于根据自然语言描述生成 Verilog 代码。但是，LLM 通常难以生成语法和功能上都正确的代码。
语法正确性
RTLFixer
结合使用检索增强生成 (RAG) 和 ReAct 提示，使 LLM 能够迭代地调试和修复语法错误。RAG 整合了人类专家指导数据库，为纠错提供上下文。ReAct 启用 LLM 进行错误推理、计划修复并采取行动。
功能正确性
VerilogCoder
是一个多代理系统，包含任务规划器和基于抽象语法树（AST）-based 波形追踪工具，用于生成和调试 Verilog 代码。它使用任务和电路关系图（TCRG）将任务分解为可管理的子任务，并将信号转换链接到每个步骤（图 2）。
图 2、任务驱动的电路关系图检索代理推理，并与开发的 TCRG 检索工具交互，通过相关的电路和信号描述丰富任务
基于 AST 的波形追踪工具通过回溯信号波形来协助 LLM 代理识别和修复功能错误。与之前的方法相比，VerilogCoder 在 VerilogEval-Human v2 基准测试中的成功率为 94.2％。
视频1. 使用 TCRG 规划和基于 AST 的波形追踪工具自动完成 Verilog 代码
在视频 1 中，VerilogCoder 演示使用 TCRG 规划和基于 AST 的波形追踪工具自动完成功能正确的 Verilog 代码。
自动生成 DRC 布局代码
DRC-Coder 使用多个具有视觉功能的自主代理以及专门的 DRC 和布局 DRV 分析工具来生成 DRC 代码。该系统从文本描述、视觉插图和布局表示中解释设计规则。多个 LLM 代理包括一个解释设计规则的规划器和一个将规则转换为可执行代码的程序员。
DRC-Coder 包含自动调试流程，该流程利用代码评估的反馈来优化生成的代码。
视频 2、用于芯片设计的 DRC-Coder 演示
在视频 2 中，DRC-Coder 演示会生成 DRC 代码，通过利用布局分析工具、自动调试流程以及多模态和多 AI 代理的功能，在数百个测试布局中实现完美的 F1 分数。
DRC-Coder 在为低于 3nm 的技术节点生成 DRC 代码时，达到了完美的 F1 评分 (达到 1.000 分)，优于标准提示技术。拟议的自动化代理方法可显著缩短 DRC 代码生成所需的时间，即每个设计规则从数周缩短到平均 4 分钟。
标准单元布局优化
用于标准单元布局优化的 LLM 智能体建议使用 LLM 的自然语言和推理能力逐步生成高质量集群约束，以优化单元布局 PPA，并使用 ReAct 提示调试可路由性。
该系统使用网络信息和单元布局分析将 MOSFET 设备分组到集群中。与在工业
2nm
技术节点中的一组顺序单元上采用基于 Transformer 的设备集群方法相比，AI 智能体不仅可将单元面积减少多达 19.4%，而且还可生成多 23.5% 的 LVS 和 DRC 清洁单元布局。
多角度多模式时序报告调试与分析
多角多模 (MCMM) 时序分析代理使用动态任务图形分别完成从规范到 RTL 的规范，并提取时序报告的关键要点。
根据经验丰富的工程师对一组工业案例的评估，MCMM 时序分析代理的平均分为 8.33 分 (满分 10 分)，与人类工程师相比，速度提高了约 60 倍 (图 3)。
图 3、MCMM 时序分析代理结果
定时路径调试代理通过静态定时调试任务图 (图 1) 查找有问题的 net、wire 和约束。
在表 2 中，定时路径调试代理可解析 86% 的路径级调试任务，而标准任务求解方法无法解析任何任务。
多报告任务说明
所需的分析结果
子任务
标准任务求解
定时路径调试代理
查找没有上升/下降信息的缺失 clk 信号
max、clk
X
V
识别 nets 对的 RC 不匹配率高
Max、Wire
X
V
检测受害者与侵犯者之间的异常约束
Max、xtalk、LC
X
V
识别牺牲者与侵犯者之间的异常 RC 值
Max、wire、xtalk、LC
X
V
查找具有最高 RC 值的最慢阶段的限制
Max、wire、xtalk、LC
X
V
比较每个 timing table，了解阶段数、点值和 timing mismatch
最大值
X
X
任务 M2 和任务 M3，用于路径列表中的特定阶段
Max、wire、xtalk、LC
X
V
平均通过率
0%
86%
表 2、具有静态任务图求解功能的定时路径调试代理的通过率 (%)，以及无任务图信息的朴素标准任务求解
X = 无法解决任务
。V = 成功完成任务。
结束语
拟议的 Marco 框架为实时硬件设计任务求解提供了更灵活、更领域更专业的方法。通过使用任务图形、灵活的单 AI 和多 AI 代理配置以及特定领域的工具和知识，我们为单元布局优化、Verilog 语法错误修复、Verilog 和 DRC 代码生成以及问题块、网络和线缆的定时调试等任务开发了各种代理。
实验结果表明，在芯片设计中使用基于 LLM 的协作式智能体可获得惊人的性能和效率优势。
硬件设计智能体研究的未来方向包括：
使用高质量的硬件设计数据训练 LLMs
提升基于 LLM 的智能体的硬件信号和波形调试能力
将 PPA 指标纳入设计流程
为 LLM 代理开发更高效的自学习技术和内存系统，以解决更复杂的硬件任务
有关电子设计自动化的更多论文和项目，请参阅
NVIDIA Design Automation Research Group
页面。
如果您对本文中重点介绍的技术感兴趣，以下是相关论文列表：
RTLFixer：使用大语言模型自动修复 RTL 语法错误
/NVlabs/RTLFixer
GitHub repo
VerilogCoder：采用基于图形的规划和基于抽象语法树（AST）的波形追踪工具的自主 Verilog 编码代理
/NVlabs/VerilogCoder
GitHub repo
DRC-Coder：使用 LLM 自主代理自动生成 DRC 检查器代码
用于优化标准单元布局设计的大语言模型（LLM）