1. Field of the Invention
The present invention relates to a ferroelectric memory device employing ferroelectric capacitors, and more particularly, to a ferroelectric memory device where ROM data stored at a manufacturing process can be retained. Especially, the ferroelectric memory device according to the present invention is more suitable a non-volatile memory provided in a micro controller, for example.
2. Description of the Related Art
In recent years, a ferroelectric memory device employing ferroelectric capacitors has been proposed as a non-volatile memory. The ferroelectric memory device stores and reads data by employing its hysteresis characteristic and residual polarization action included in a ferroelectric film of the ferroelectric capacitor. By applying an electric field to the ferroelectric capacitor in one direction, the ferroelectric capacitor becomes a polarizing state in one direction. Alternatively, by applying an electric field to the ferroelectric capacitor in the other direction, the ferroelectric capacitor becomes a polarizing state in the reversed direction. Such the polarizing state may be retained as a residual polarization even after an electric field applied to the ferroelectric capacitor is extinct. Therefore, the ferroelectric memory device is used as a non-volatile memory where data can be retained, even if a power is OFF.
FIG. 9 is a circuitry diagram of a ferroelectric memory cell according to the prior art. The structure of a memory cell MC of FIG. 9 is called a 2T2C structure, in which one pair of transistors Q1, Q2 and one pair of ferroelectric capacitors C1, C2, connected to each of the transistors are included. Each of the transistors Q1, Q2 has a gate connected to a word line WL, a source or drain electrode to which one of bit line pairs BL, /BL is respectively connected. Additionally, the ferroelectric capacitors C1, C2 are connected to a plate line PL. A sense amplifier 10 is connected to a bit line pairs BL, /BL. Data is recorded by polarizing one capacitor pair C1, C2 of the memory cell MC shown in FIG. 9, and the recorded data is read out in the later-explained method.
FIG. 10 shows a hysteresis curve of the ferroelectric film. FIG. 10 shows an applied electric field or voltage on the abscissa axis and a polarization charge on the ordinate axis. In the hysteresis curve, the polarizing state of the ferroelectric film is changed from a point K, for example, and is returned to the point K through points L, M, N.
FIG. 11 illustrates a definition of a polarizing direction of the ferroelectric capacitor in this description. In FIG. 11, each polarizing states K, L, M, N shown in FIG. 10 are shown. A hysteresis characteristic of the ferroelectric film will be now explained according to FIGS. 10 and 11.
As shown in FIG. 11, when applying a downward electric field Ek to the ferroelectric capacitors C1, C2 by applying a voltage of 5V, for example, a downward polarization charge -qs of FIG. 11 is generated on the capacitors C1, C2. When the voltage applied between the capacitors C1, C2 are removed from this state K, after that, the state is moved to the state L and the polarization charge -qs remains on the capacitors C1, C2. On the other hand, when a voltage of 5V is applied for the ferroelectric capacitors C1, C2, in the upward direction of FIG. 11, the upward electric field Em is applied and the status becomes a polarizing state M of the polarization charge +qs. Even if the voltage application to the capacitor is removed from this state M, the polarizing status of polarization charge +qs can be retained on the capacitors as the state N.
Therefore, in this description, the state K or M where the electric field or voltage is applied to the capacitors is shown by a bold arrow line, and the state L or N of residual polarization where there is no potential difference in the capacitor and the electric field is not applied is shown by a broken arrow line. The direction of arrow indicates each polarizing direction.
FIG. 12 is a timing chart of writing and reading data to the memory cell having a 2T2C structure according to the prior art. In this timing chart, a word line WL, a plate line PL, a sense amplifier operation, a bit line pairs BL, /BL, each polarizing direction of capacitors C1, C2 are shown. FIG. 12 shows the time on the abscess axis.
Data writing and reading operation modes to the memory cell of FIG. 9 will be explained in accompanying with FIGS. 10 and 12. At first, it is assumed that data written in the ferroelectric memory cell is indefinite at time Wt0 of a write cycle. The bit line pairs BL, /BL are reset to an intermediate potential between levels H and L, and the word line WL and the plate line PL are set to L level. When the word line WL is driven to H level at time Wt1, the transistors Q1, Q2 of the memory cell become conductive, and one capacitor pair C1, C2 are respectively connected to the bit line pair BL, /BL. Then, at time Wt2, the sense amplifier 10 is activated according to the written data to set the bit lines BL and /BL respectively to H and L levels. As a result, the downward electric field is applied to the ferroelectric capacitor C1 and the state becomes the state K, which is the downward polarizing state. Then, no electric field is applied to the other ferroelectric capacitor C2 so that the polarizing direction is not changed.
When the plate line PL is driven to H level at time Wt3, the capacitor C2 that is connected to the bit line /BL of L level is polarized in the other direction reversed to the capacitor C1. In other words, the capacitor C2 becomes the state M, and the capacitor C1 becomes the state L. After the plate line PL is returned to L level and the capacitor C1 is polarized again, then, the word line WL is returned to L level and the cell transistors Q1, Q2 are OFF at time Wt5. For the reason, the capacitor C becomes the downward polarizing state L, and the capacitor C2 becomes the upward polarizing state N. The polarization states are remained and are retained, even when the power is OFF.
In the reading operation mode, the bit line pair BL, /BL are pre-charged to 0V at time Rt0. When the word line WL is driven to H level at time Rt1 and the plate line PL is driven to H level, then, the state of the capacitor C1 is moved from the state L to the state M and its polarization is reversed. On the other hand, the state of the capacitor C2 is moved from the state N to the state M. As a result, the ferroelectric capacitor C1, of which polarization is reversed, emits more charge than that of the ferroelectric capacitor C2, of which polarization is not reversed, to each bit line, thus a predetermined potential difference is generated between the bit line pair BL, /BL.
At time Rt2,the plate line PL is set to L level. As a result, although the potential of the bit line pair BL, /BL is slightly pull down, the above-described potential difference can be retained. At time Rt3, the potential difference between the bit line pair BL and /BL can be detected and be amplified by activating the sense amplifier 10. As a result, the data stored in the ferroelectric capacitor can be read out through each bit line.
Since both of the capacitors C1, C2 are in the upward polarizing state at time Rt1, the stored data is broken. Therefore, the result of amplifying the sense amplifier 10 is given to the ferroelectric capacitors C1, C2 and data is rewritten by driving the plate line PL to H and L level respectively at each time Rt4 and Rt5. When the word line WL is set to L level at time Rt6, then, a residual polarizing state according to the stored data may be retained in the capacitors of the memory cell.
The above-described ferroelectric memory device is used by building in a micro controller and is used as a rewritable ROM, for example. There are some cases where a program, in which a procedure of activating the micro controller is written, because the ferroelectric memory device is non-volatile. A CPU built in the micro controller executes required operations according to the program written in the ferroelectric memory.
However, when using the ferroelectric memory device instead of the ROM built in the conventional micro controller, the following inconvenience will be brought.
Immediately after finishing a manufacturing process, data in a memory becomes indefinite in a ferroelectric memory device. Therefore, data should be written to a memory in some kinds of methods. Although a write-only device can be used as this writing method, a special circuit such that the data transmitted from the write-only device is stored in the ferroelectric memory should be provided in a micro controller. Therefore, there is a demand that desired data can be pre-recorded at the manufacturing process like the conventional ROM.
On the other hand, once desired data is written at the manufacturing process in the conventional ROM, the data can not be rewritten after that. Therefore, when a program is recorded in a ROM of a micro controller, the program can not be changed after that. However, since the stored data can be freely changed in the ferroelectric memory device, the use of the ferroelectric memory device instead of the conventional ROM makes it possible to change the program. Conversely speaking, freely program change means that data stored at the manufacturing process may be lost, and therefore, it is also required that the lost data can be restored or recovered.


1. Field of the Invention
The present invention relates to a semiconductor chip package, and relates more particularly to a stacked multichip package.
2. Description of the Related Art
Integration of multiple stacked chips into a single package can increase electronic component package density and reduce the signal distances between electronic components. In other words, the integration technique can not only decrease the total volume required to prepare for individual chips, but can also improve the integral performance of the chips. Among the techniques for packaging multiple stacked chips, the package technique for multiple stacked chips of the same size is one of the most common package techniques.
In the package technique for multiple stacked chips of the same size, a plurality of chips of the same size are stacked one upon another on a substrate and the active surfaces of the chips usually face upward for convenient to wire bond. To prevent bonding wires of a lower chip from being damaged or shorted by an upper chip, interposers are provided between the chips. The height of each interpose should be greater than the loop heights of the corresponding bonding wires. Conventionally, the interposer can be a polyimide tape, a dummy chip, a metal piece, etc.
However, using interposers requires additional processes such as, for example, a chip attach adhesive coating process, a chip mounting process, and a curing process. Such additional processes increase manufacturing cost and risk lowering manufacturing yield.
Specifically, manufacturing yield is an important consideration in the production of multiple chip packages. When multiple chips are packaged into an encapsulation body, the result of composite manufacturing yields greatly influences manufacturing cost. In particular, when the encapsulation body includes a high-priced chip, the risk of low manufacturing yield is more important. If a low price chip in the encapsulation body malfunctions or if a chip is damaged during the chip stacking process, the high-priced chip will have to be discarded with the nonfunctional chip, and such discard causes serious impact to the manufacturing cost.
Thus, in light of the trend of multiple chip package development and the high cost risk of multiple chip packages, a low cost and high manufacturing yield multichip package structure is required by the packaging industry.


German publication no. DE 10 2012 206 443 A1 (Biermann et al.) discloses a planetary gear differential transmission for a motor vehicle, the planetary gear differential transmission comprising a driving gear, by means of which the torque can be introduced into the transmission; comprising a first output member and a second output member, by means of which the torque can be outputted from the transmission; comprising a differential cage, which is designed to transmit the torque from the driving gear to the first output member, wherein the differential cage is attached to the driving gear in a rotationally fixed manner; and the first output member is arranged in such a way that it can be rotated in relation to the differential cage; and comprising a rolling bearing with a bearing shell, which is attached to the differential cage in a rotationally fixed manner.
For example, DE 10 2011 085 119 B3 (Martini et al.), discloses differential transmissions. Thus, this document discloses a spur gear differential, comprising a planetary gear carrier and two sun gears, which can be rotated relative to the planetary gear carrier, at least one friction disk and at least one spring means, which biases the sun gears relative to the planetary gear carrier. The spring means is spring-mounted, on the one hand, against a sun gear or the planetary gear carrier and, on the other hand, against an axial bearing. The geometrical and functional features, which are disclosed in DE 10 2011 085 119 B3 (Martini et al.), shall be incorporated by reference in its entirety.


Many electronic devices include operating systems that can execute applications. As the popularity of applications increases, more and more developers are attracted to create applications for various platforms. Some platforms now have applications numbering in the millions.


An apparatus 22 for double-side polishing semiconductor wafers as shown in FIGS. 4 to 7, wherein only the main functional members are shown in FIG. 4, is well known as an apparatus for polishing the two sides of each of semiconductor wafers W at the same time.
The apparatus 22 shown in FIG. 4 comprises a lower polishing turn table 24 and upper polishing turn table 26 both of which are arranged in a face to face relation with each other. Lower and upper polishing pads 24a, 26a are fixedly applied on the upper face of the lower polishing turn table 24 and the lower face of the upper polishing turn table 26 respectively. The lower and upper polishing turn tables 24, 26 are respectively rotated in opposed directions by a driving means which is not shown for clarity.
A sun gear 28 is at the center of the lower polishing turn table 24 and held on the surface thereof and an internal gear 30 in an annular shape is located near the outside of the periphery thereof. Each of wafer carriers 32 has the shape of a disc and lies between the upper surface of the lower polishing pad 24a and the lower surface of the upper polishing pad 26a. The wafer carriers 32 are moved around in a space between the lower and upper polishing pads 24a, 26a, while each of the wafer carriers 32 turns not only about its own center but revolves around the centers of the polishing pads 24a, 26a by the actions of the sun gear 28 and internal gear 30. Each of the carriers 32 has a plurality of carrier holes 34 and semiconductor wafers W to be polished are placed in the respective carrier holes 34. In polishing the wafers W, polishing slurry is supplied between a wafer W and each of the polishing pads 24a, 26a through a hole 38 communicating between the upper and lower surfaces of the upper polishing turn table 26 from a nozzle 36. As a wafer carrier 32 turns about its center and at the same time revolves around the centers of the lower and upper polishing turn tables 24, 26, the wafers W placed in the carrier holes 34 turn about the respective centers of their own and at the same time revolve around not only the centers of the polishing turn tables 24, 26 but also the center of the carrier 32, so that the wafers W are moved around between the lower and upper polishing pads 24a, 26a and the two sides of each wafer W are polished at the same time.
The inner peripheral edge of a carrier hole 34 has an annular member A secured along the same edge for the purpose of preventing cracking or chipping of the edge of a semiconductor wafer W. The annular member A is produced by injection molding of plastics or it may be produced from glass fiber reinforced epoxy resin composite. Structures similar to or same as the wafer carrier 32 including the annular member A are respectively disclosed in laid open publications of Japanese Utility Model Application No. 57-177641, 58-4349 and 58-59559, and laid open publication of Japanese Patent Application No. 6-226618.
When double-side polishing of a semiconductor wafer W is conducted by the use of the conventional apparatus 22 for double-side polishing semiconductor wafers above mentioned, a surface of a peripheral portion of an edge of the wafer W can be polished by the function of an annular member A as a polishing buff because of a relative rotational speed of the wafer W to the carrier hole 34 due to the rotation of the wafer W within the carrier hole 34, but the upper and lower chamfered portion of the edge of the wafer W remain unpolished. Therefore, generation of particles from such portion of the edge of the wafer W cannot be prevented in the conventional double-side polishing operation. In light of the problem, it is required that the whole edge portions are polished in double-side polishing. There are additional other problems in realizing the perfect polishing of the whole edge portions in double-side polishing that the perfect edge polishing as an additional process step is a costly operation because of its technical difficulty and moreover, the main surfaces of the wafer W are contaminated during edge polishing process.


Monitoring littoral seas without being detected can be desirable in times of conflict. In such cases, autonomous submersible monitoring and communications systems can provide much needed intelligence. While such devices can be deployed without detection, communicating the results of monitoring by devices submerged in the sea is problematic. Sonar provides low bandwidth over short ranges and radio communications, at all but the highest powers and lowest data rates, are blocked by salt water. Effective communication requires therefore that an antenna be raised above the sea. A variety of systems have been described for raising an antenna above the sea, but they are either expensive, impractical, or readily detected, making them unsuitable for exporting information without being detected.


The computation of the adaptive weight vectors is one of the most difficult of signal processing algorithms used to implement large scale adaptive processing systems. This is due to extremely high computation rates, large dynamic range, and low latency requirements imposed on these systems. For typical adaptive systems, the computation of the adaptive weights requires 50 to 150 GFLOPS of computational throughput. This type of high-throughput adaptive processing calls for special purpose hardware to achieve high efficiency that fully exploits the parallel nature of the adaptive weight computation process.
Current adaptive signal processing research focuses on what is known as the optimal least squares solution to the general adaptive array nulling problem. It is estimated that signal processing for the least squares problem will dominate all other functional requirements for adaptive radar systems in the near future. This dominance occurs as a direct result of the algorithm throughput requirement, which is proportional to the cube of the number of sensor elements in the system. It is estimated that, in many systems, over 90% of the total signal processing load will be dedicated to this function alone. No currently available general purpose signal processing devices or architectures will provide the throughput without the penalty of large card or module counts.
A key application of adaptive least squares computation is in the calculation of beamforming weight vectors for optimal interference suppression (i.e., jamming, multipath) in advanced multi-channel radar, sonar, and adaptive communications systems. However, the same technology is generally applicable to any system that must quickly generate large sample covariance matrices and perform large-scale matrix inversion operations (Least Squares applications).
Previous techniques for finding solutions for these systems have used either a hardwired, non-programmable systolic array approach, or more commonly, programmable digital signal processor (DSP) or microprocessor approaches. The hardwired logic methods can be very efficient, but are quite inflexible. Approaches using multiple programmable DSP devices (such as those from Texas Instruments, Motorola, etc.) are very flexible, but suffer from poor efficiency and high computation latencies, primarily due to the large number of DSP devices that must be utilized to achieve the necessary arithmetic throughput. Although a processor embodying the present invention can be implemented as a highly optimized systolic array, it retains much of the flexibility of a programmable data-flow system, allowing efficient implementation of algorithm variations.
A version of a hardwired linear systolic array of processors, called MUSE, was developed at Massachusetts Institute of Technology Lincoln Laboratory, as described in "MUSE--A Systolic Array for Adaptive Nulling with 64 Degrees of Freedom, Using Givens Transformations and Wafer Scale Integration," Technical Report 886, 18, May 1990. The MUSE array specializes in real-time adaptive antenna nulling computations for a 64 degree-of-freedom ("DOF") sidelobe canceller radar system. The MUSE architecture consists of a linear systolic array of vector rotation cells that perform voltage domain Cholesky factorization of a sample covariance matrix using a series of Givens transformations. The MUSE then partially backsolves the Cholesky factor for an adaptive weight vector using a fixed sidelobe canceller steering constraint.
Although the MUSE architecture does attack the side-lobe canceller problem, there are some limitations that prohibit its use in a more general RLS and signal processing applications. The MUSE architecture uses a fixed steering constraint, specific to a sidelobe canceller radar system, for the computation of adaptive weights. In addition, MUSE only partially solves for these adaptive weights, requiring external processing hardware to compute the final result. Further, the MUSE architecture operates only on a fixed 64 degree-of-freedom problem size, and cannot be used efficiently on other problem sizes. In order to solve general linear system problems, a method of computing weights from a general constraint is needed. If these weights could be computed within the systolic array, the dependency on external processing could be eliminated.
Another limitation of the MUSE architecture is its inability to perform Cholesky factor downdating. Downdating consists of subtracting off contributions of old data samples from the Cholesky factor as new ones are added. This is useful for implementing sliding window functions on the input data, a function necessary in many signal processing applications. The MUSE architecture operates in a mode where the Cholesky factor is continuously updated. A constant forgetting factor is implemented that acts as an exponentially decaying window on the input data. Although this performs adequately in some applications, it imposes limitations on the types of processing that can be performed.


A dynamic random access memory (DRAM) cell typically comprises a charge storage capacitor coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the capacitance C=εεo A/d, where ε is the dielectric constant of the capacitor dielectric, εo is the vacuum permittivity, A is the electrode (or storage node) area, and d is the interelectrode spacing. The conditions of DRAM operation, such as operating voltage, leakage rate and refresh rate, will in general mandate that a certain minimum charge be stored by the capacitor.
In the continuing trend to higher memory capacity, the packing density of storage cells must increase, yet each must maintain required capacitance levels. This is a crucial demand of DRAM fabrication technologies if future generations of expanded memory array devices are to be successfully manufactured. Nevertheless, in the trend to higher memory capacity, the packing density of cell capacitors has increased at the expense of available cell area. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area.
Several techniques have been developed to increase the capacitance of the cell capacitor without significantly affecting the cell area. For example, capacitor electrodes having textured surface morphology have been introduced to increase the interfacial area between the dielectric thin film and the adjacent electrode and, therefore, to increase the capacitance. For example, in conventional dual-sided (or double-sided) container capacitors, hemispherical grain polysilicon (HSG) has been introduced as the material of choice for the double-sided electrode because the increased surface area of the HSG electrode and of its respective interfacial area is directly proportional to the cell capacitance. However, current technologies for the formation of a double-sided HSG electrode involve using HSG on the outside of the capacitor plate. Accordingly, when two neighboring dual-sided HSG capacitors are fabricated on a DRAM memory circuit, for example, a short circuit between the two dual-sided HSG capacitors may occur and thus, may negatively affect the characteristics of the device.
Accordingly, as memory cell density continues to increase, there is a need for an improved method for forming a dual-sided HSG container capacitor having increased capacitance per cell and low leakage, as well as a method of forming a capacitor structure that achieves high storage capacitance without increasing the size of the capacitor and without a short circuit between the capacitor structure and an additional adjacent capacitor.


1. Field
The following description relates to a network device, more particularly, to a method of searching for a signature in a payload of a packet received through a network line.
2. Description of the Related Art
Recently, following the ever increasing distribution of high-speed internet networks, the need for improved performance of security device performances is increasing. Conventional network devices detect intrusion and filter packets using specific signature matching in a packet. Such detection and filtering functions of the network devices can be implemented in a hardware manner, in a software manner, or in a combined hardware and software manner. In addition, a variety of requirements for signature matching increases as the network speed becomes faster and invasion methods become more and more diverse. In particular, high-speed signature matching technologies and signature matching technologies using a specific location and a specific range in a packet are increasingly required, and thus research on various methods that can satisfy such requirements has been conducted.
In a high-speed packet processing system such as a firewall and an intrusion detection system, a hardware-based technology such as a ternary content addressable memory (TCAM) is used to detect a match of a packet with a security policy at high speed. TCAM is used for high-speed signature searching in a payload of a packet. The high-speed signature matching is implemented by setting a signature in a TCAM and matching a header and the payload of the packet. Based on the signature matching result, a signature range searching process is performed in hardware and software manners to determine whether the matched signature is located on a specific position in the packet or within a specific range in the packet. Due to the signature range searching process after the TCAM matching, it takes a substantial amount of time for this process, thus impeding high-speed performance of a network device.


1. Field of the Invention
The present invention relates to power-on detection circuits, and more particularly to power-on detection circuits for detecting a minimum operational frequency required to power-on a device.
2. Description of the Prior Art
Most circuits require certain minimum power levels for operation. It is therefore necessary to have some form of power detection circuit that can detect when this power level is reached, thereby determining that power-on is possible. If the power level detected is too low then the circuit will be unable to operate. If the power level detected is too high then some potential operational time, energy, and potential for lower voltage operation will have been wasted.
Please refer to FIG. 1. FIG. 1 is a diagram of a conventional power detection circuit 100. The circuit 100 comprises a first resistor R1 (12) coupled to a voltage supply, a second resistor R2 (14) coupled between R1 and ground, and a transistor 16 where the gate of the transistor 16 is coupled between R1 and R2. The source of the transistor 16 is coupled to a third resistor R3 (18) and an output device 20 and the drain of the transistor 16 is coupled to ground. The circuit 100 works by utilizing a ratio of the first resistance to the second resistance (R1/R2). When the ratio is above a certain voltage Vt it will power-on the transistor 16, causing the transistor 16 to pull down against the resistor R3, thereby generating a signal in the output device 20 that signifies that power is sufficient for power-on.
As the circuit 100 utilizes a ratio of two resistors, the level at which it is determined that power-on is possible is not as precise as desired. It is the aim of the present invention to provide a circuit and a method of power detection that can determine a minimum power required for power-on with a high level of accuracy.


1. Field of the Invention
The present invention relates to adhesive tape dispensing technology and more particularly, to a trigger-operated adhesive tape dispenser.
2. Description of the Related Art
When using a conventional adhesive tape dispenser, it is to adhere one end of the adhesive tape of the loaded adhesive tape roll to the surface area of the object to the packed, and then move the adhesive tape dispenser to pull the adhesive tape out of the adhesive tape roll subject to the desired length. During rotation of the tae holder wheel to let off the adhesive tape of the adhesive tape roll, the adhesive tape is smoothly adhered to the surface of the object. At final, use the cutter blade to cut off the applied adhesive tape. Thus, the use of the adhesive tape dispenser can effectively simplify the packing process and enhance the packing efficiency.
However, before cutting off the applied adhesive tape, the user must rotate the tape dispenser and apply a certain amount of downward pressure to the adhesive tape dispenser to force the roller against the adhesive tape and to increase the tension of the adhesive tape that is been pulled out, enabling the cutter blade to cut off the applied adhesive tape. If the downward pressure applied to adhesive tape dispenser is insufficient or the direction of the applied downward pressure is not correct, the applied adhesive tape will not be easily cut off by the cutter blade. When this problem occurs, the user must repeatedly adjust the applied pressure and angle till that the adhesive tape can be smoothly cut off, Thus, the operation of the aforesaid conventional adhesive tape dispenser is inconvenient and requires much effort.


In recent years, demands for a high-resolution and high-quality image have increased in various fields of applications. As an image has a higher resolution and higher quality, an amount of data on the image increases more and more. Accordingly, when video data is transferred using media such as existing wired or wireless broadband lines or video data is stored in existing storage media, the transfer cost and the storage cost of data increase.
In order to effectively transfer, store, and reproduce information on high-resolution and high-quality video, high-efficiency video compressing techniques can be utilized.
In order to enhance video compression efficiency, a method of predicting information of a current block using information of neighboring blocks of the current block without transferring the information of the current block can be used.
Inter prediction and intra prediction can be used as the prediction method.
In the inter prediction, pixel values of a current picture are predicted with reference to information of other pictures. In the intra prediction, pixel values of a current picture are predicted using inter-pixel relationships in the same picture.
When the inter prediction is performed, information indicating a reference picture and information indicating a motion vector from the neighboring blocks in an inter prediction mode can be utilized to designate a part of another picture to be used for the prediction.


Zinc, aluminium and/or combinations of aluminium and zinc (Al/Zn), are widely used as surface coatings, particularly but not exclusively for steel for protection against rust and corrosion. In practice, however, the zinc or Al/Zn coatings are susceptible to white rust or black rust respectively when exposed to the atmosphere due to reactions with moisture. Such rust is detrimental to the surface and generally makes coated steel substrates unsaleable despite the fact that the overall service life of the coated steel may remain the same and the formation of rust generally interferes with finishing operations. The ability to resist such corrosion is referred to herein as wet stack performance.
In order to inhibit the formation of rust on coated surfaces it is generally accepted that the treatment of a surface with a chromate imparts anti corrosive properties and this type of treatment is generally referred to as chromate passivation. However chromate is highly toxic to exposed workers and due to its high toxicity, disposal of chromium residues is difficult. Further in various markets the yellow discolouration of the treated coated surfaces is considered to be an unacceptable product attribute.
In order to overcome the problems associated with chromate passivation, phosphate coatings have been used. However the anticorrosion properties of phosphate have been found to be far inferior to the above mentioned chromate treatment.
U.K. Patent Application No. 2,070,073 discloses an anti corrosive treatment for preventing white rust on galvanized steel comprising applying to the surface of a galvanized steel sheet an acidic solution containing molybdic acid or a molybdate in a concentration of 10-200 g/l calculated as molybdenum and adjusted to a pH of 1 to 6 by addition of an organic or inorganic acid. However, it has been found that the corrosion resistance of aluminium and aluminium alloy surfaces treated with the above solution is inferior to the chromate treated substrates under certain conditions and the treated surfaces suffer from an undesirable degree of discolouration. Moreover modybdate treated surfaces have been shown to change from a pale yellow/blue to a strong green colour when stored for periods of time in excess of 24 hours.
Accordingly it is an object of the present invention to provide means for avoiding and/or ameliorating at least some of the above discussed disadvantages of the prior art.


This invention relates to the field of ink jet printers. More particularly, this invention relates to an improved ink jet printer cartridge and a manufacturing method therefor.
Ink jet printers require an ink supply to be in fluid contact with an ink drop ejecting device which precisely ejects ink onto a recording media. The ink supply must be maintained at a relatively constant pressure to keep the ink from discharging from the ejecting device at the wrong time or in an undesired amount. There are several methods and devices for maintaining a constant negative back-pressure including capillary fibers or foam, bladder-type configurations and lung-type configurations.
Bladder and lung configurations are preferred since they may be configured to provide a smaller volume ink reservoir for the same quantity of ink contained in a foam or fiber filled reservoir. Such bladder and lung devices may consist of a rigid frame with either one or two side panels made of a thin plastic laminate material. Both configurations depend on a flexing of the side panels which is resisted by a biasing member located either between the side panels (bladder configurations) or between one of the side panels and a rigid panel attached to the frame (lung configurations). The side panels are typically heat welded or adhesively attached to a substantially rigid frame. While heat welding is an effective, less time consuming and less costly method of attaching the flexible panels to a rigid frame, improvements in heat welding techniques are needed to increase useable product yield and provide a less fragile lung or bladder construction.
The foregoing and other needs are provided by an improved ink cartridge for an ink jet printer and improved manufacturing method therefor. According to the invention, a method for manufacturing a pressure control device for an ink jet cartridge is provided. The method includes providing a thermoplastic, flexible web having an edge portion, a first side and a second side and providing a substantially inflexible frame member having at least one peripheral edge. The first side of the flexible web is disposed adjacent the peripheral edge of the frame, thereby defining a substantially closed cavity. The edge portion of the web and peripheral edge of the frame are heat welded to one another using a heated platen, the heated platen having a heating surface and the peripheral edge having a bonding surface. The heat welding step is preferably conducted with a structure selected from the group consisting of an angled platen for heat welding the web and peripheral edge, a conventional platen for heat welding an angled peripheral edge and an angled platen for heat welding an angled peripheral edge whereby a bond is formed between the flexible web and the bonding surface at a temperature and pressure which minimizes thinning of the flexible web on the bonding surface at least adjacent the substantially closed cavity and wherein an angle providing the angled platen or angled peripheral edge relative to a plane defined by the flexible web ranges from about 5 to about 45 degrees.
In another aspect the invention provides an ink jet pen for use in an ink jet printer. The pen includes an ink jet cartridge body and ink jet cartridge attached to the cartridge body. The ink jet cartridge contains ink and a pressure control device is disposed therein for maintaining a substantially constant pressure in the ink jet cartridge. The ink jet cartridge includes a substantially inflexible frame having at least one peripheral edge. At least one thermoplastic, flexible web is provided having an edge portion, a first side and a second side. The edge portion of the first side of the flexible web is heat welded to the peripheral edge of the frame thereby defining a substantially closed cavity. The edge portion and peripheral edge are heat welded to one another at a temperature and pressure sufficient to provide a reinforced web edge portion. The heat welded flexible web is preferably provided by a heat welding structure selected from the group consisting of an angled platen for heat welding the web and peripheral edge, a conventional platen for heat welding an angled peripheral edge and an angled platen for heat welding an angled peripheral edge and wherein an angle providing the angled platen or angled peripheral edge relative to a plane defined by the flexible web ranges from about 5 to about 45 degrees.
By heat welding the edge portion of the flexible web and peripheral edge of the frame to one another with an angled heated platen, an angled peripheral edge, or both an angled platen and angled peripheral edge, the edge portion of the web is substantially reinforced with respect to the frame. As compared to a pressure control device for an ink jet cartridge made with a standard, non-angled platen and/or peripheral edge, the pressure control device made according to the invention withstands mishandling to a greater degree thereby providing a higher yield of usable parts. The ink cartridges containing such pressure control devices are also substantially more reliable for long term use due to less thinning of the web edge portion adjacent the closed cavity during the welding or bonding process.


1. Field of the Invention:
The invention relates to an integrated circuit for detecting a received signal, which can be used, for example, in radio receivers and in particular in mobile radio receivers, as well as a circuit configuration with an integrated circuit.
Voltage-controlled oscillators (VCO) which are tuned with a phase locked loop (PLL) have become established in radio reception technology. The oscillator frequency of the voltage-controlled oscillator is tuned using the phase locked loop with a specific step size, for example with a frequency step size of 100 KHz in frequency-modulated radio in Europe. During the transmitter search run, the entire FM band (87.5 MHz to 108 MHz) is preferably scanned in 100 KHz increments. The oscillator frequency of the voltage-controlled oscillator fOSC is typically 10.7 MHz above the input frequency to be received, that is to say between 98.2 MHz and 118.7 MHz.
During the transmitter search run, as far as possible all the transmitters which are worth receiving are to be found and their input frequency or the corresponding oscillator frequency fOSC of the voltage-controlled oscillator are to be stored. If a transmitter is detected at any particular reception frequency, the phase locked loop is stopped at the a instantaneous value by the microcontroller. The corresponding values are stored in the microcontroller so that these transmitter stations which are determined can be set directly at a later time. In order to be able to detect the transmission stations, one orxe2x80x94for sake of increased detection precisionxe2x80x94a plurality of criteria are required in order to stop the voltage-controlled oscillator at the corresponding oscillator frequency. It is therefore necessary to use one, or preferably a plurality of, evaluation criteria in the receiver in order to to detect unambiguously the presence of an input signal which is worth receiving.
In order to increase the reliability with which a transmitter can be detected unambiguously, it is possible to use not only the field-strength signal (level of the received signal) but also the multipath signal which indicates whether the received signal is scattered by multipath reception. To do this, the field-strength signal and the multipath signal are fed to a microprocessor which digitizes these signals and evaluates them through the use of criteria which are predefined in the microprocessor. Finally, in the microprocessor it is decided whether the transmitter is one which is worth receiving. The disadvantage of such a circuit configuration is that a plurality of lines are required from the receiver module to the microprocessor and unavoidable data traffic occurs on the data bus during the transmitter search run. However, this not only unnecessarily severely loads the microprocessor but the data traffic also constitutes a permanent source of interference in the sensitive reception system. In order to keep the data traffic as low as possible, the transmitter search criterion of intermediate frequency counting is therefore frequently not included, which however has the disadvantage of less precise transmitter identification. In many cases, for a more reliable search run stop it is not sufficient to evaluate only one of the search run stop criteria including the field-strength signal, multipath signal, zero crossover of the S curve and the limited intermediate frequency transmitted from the input mixer to the intermediate frequency amplifier. It is difficult to reliably detect weakly receivable transmitters only through the use of the field-strength.
European Patent Application No. EP 0 430 469 A2 discloses a circuit for detecting a received signal for FM receivers. The detector contains an intermediate frequency detector, a field-strength comparator and a noise signal detector whose output signals are combined with one another in a logic switching element to form a signal path. A microprocessor is driven as a function of this.
Patent Abstracts of Japan, Volume 009, No. 248 (E-347), Oct. 4, 1985 (JP-A-60-096913) discloses how to use a noise detector to detect noise on the basis of multipath signals.
European Patent Application No. EP 0 335 141 A2 discloses a configuration for detecting various reception characteristic variables including a multipath reception, the outputs of which are coupled to a logic element.
It is accordingly an object of the invention to provide an integrated circuit for detecting a received signal which overcomes the above-mentioned disadvantages of the heretofore-known circuits of this general type and which permits a transmitter identification as quickly and reliably as possible while avoiding interference.
With the foregoing and other objects in view there is provided, in accordance with the invention, in combination with a microprocessor, an integrated circuit for detecting a received signal, including:
an intermediate frequency detector configured to detect an intermediate frequency and supplying a first search run stop signal if the intermediate frequency is within a given range;
a field-strength comparator configured to supply a second search run stop signal if a field-strength of the received signal exceeds a field-strength setpoint value;
a multipath comparator configured to supply a third search run stop signal if a multipath signal exceeds a given multipath setpoint valve;
a logic component operatively connected to the intermediate frequency detector, the field-strength comparator, and the multipath comparator, the logic component logically combining the first, second and third search run stop signals with one another and forming a binary stop signal, the logic component having an output and providing the binary stop signal as a statically present signal at the output of the logic component, and the microprocessor receiving, as an input signal, the binary stop signal provided at the output of the logic component;
a first analog/digital converter connected upstream of the field-strength comparator, the first analog/digital converter digitizing a field-strength signal;
a first serial/parallel converter connected between the first analog/digital converter and the field-strength comparator;
a second analog/digital converter connected upstream of the multipath comparator, the second analog/digital converter digitizing the multipath signal; and
a second serial/parallel converter connected between the second analog/digital converter and the multipath comparator.
In other words, the integrated circuit according to the invention for detecting a received signal has an intermediate frequency detector which supplies a first search run stop signal if the intermediate frequency lies within a specific range. Furthermore, the integrated circuit has a field-strength comparator which supplies a second search run stop signal if the field-strength of the received signal exceeds a field-strength setpoint value. The invention additionally has a multipath comparator which supplies a third search run stop signal if the multipath signal exceeds a specific multipath setpoint value. Furthermore, a logic component is provided which logically combines the three search run stop signals with one another to form a binary stop signal which is statically present at the output of the logic component and is made available to a microprocessor as its input signal.
The data traffic between the microprocessor and the integrated circuit is reduced, which results in a severe reduction in interference.
The integrated circuit has the advantage that the overall space required for the radio receiver can be reduced as a result of the integration of a first analog/digital converter, which is connected upstream of the field-strength comparator and serves to digitize the field-strength signal, into the integrated circuit. Likewise, the external electrical lines, which therefore run outside the integrated circuit, can therefore be reduced, which also reduces the susceptibility to interference.
A second analog/digital converter which is connected upstream of the multipath comparator and which serves to digitize the multipath signal also entails the aforementioned advantages.
The integrated circuit has the advantage that accelerated signal processing is possible in the field-strength comparator by virtue of a first serial/parallel converter which is connected between the first analog/digital converter and the field-strength comparator.
This advantage also applies if a second serial/parallel converter is connected between the second analog/digital converter and the multipath comparator.
According to another feature of the invention, the integrated circuit can advantageously be adapted to the ambient conditions by setting the field-strength setpoint value and the multipath setpoint value to lower values in areas or conditions with weak reception than in areas or conditions with strong reception, so that rapid transmitter signal detection is still possible.
In an advantageous embodiment of the integrated circuit according to the invention, the field-strength setpoint value, the multipath setpoint value and the range within which the intermediate frequency is to lie are determined by the microprocessor. This permits a flexible, rapid and simple adaptation of the setpoint values to the ambient conditions without the computing capacity of the microprocessor being appreciably restricted thereby.
According to another feature of the invention, a third serial/parallel converter having an output side coupled to the field-strength comparator and to the multipath comparator is provided, the third serial/parallel converter receiving the field-strength setpoint value and the multipath setpoint value in a serial manner.
With the objects of the invention in view there is also provided, a circuit configuration, including:
a microprocessor having a microprocessor input terminal and at least one microprocessor output terminal, the microprocessor input terminal having a single line; and
a detection circuit including:
at least one detection circuit input terminal;
a detection circuit output terminal connected to the single line of the microprocessor input terminal;
an intermediate frequency detector configured to detect an intermediate frequency and supplying a first search run stop signal if the intermediate frequency is within a given range;
a field-strength comparator configured to supply a second search run stop signal if a field-strength of a received signal exceeds a field-strength setpoint value;
a multipath comparator configured to supply a third search run stop signal if a multipath signal exceeds a given multipath setpoint valve;
a logic component operatively connected to the intermediate frequency detector, the field-strength comparator, and the multipath comparator, the logic component logically combining the first, second and third search run stop signals with one another and forming a binary stop signal as a statically present output signal, the logic component providing the binary stop signal to the detection circuit output terminal, the at least one microprocessor output terminal being connected to the at least one detection circuit input terminal for transmitting the field-strength setpoint value and the multipath setpoint value as a serial data word, and the given range within which the intermediate frequency is to be;
a first analog/digital converter connected upstream of the field-strength comparator, the first analog/digital converter digitizing a field-strength signal;
a first serial/parallel converter connected between the first analog/digital converter and the field-strength comparator;
a second analog/digital converter connected upstream of the multipath comparator, the second analog/digital converter digitizing the multipath signal; and
a second serial/parallel converter connected between the second analog/digital converter and the multipath comparator.
In other words, a circuit configuration according to the invention includes an integrated circuit and a microprocessor in which the integrated circuit has an output terminal for the binary stop signal which is connected to an input terminal of the microprocessor which includes a single line and in which the microprocessor has at least one output terminal which is connected to at least one input terminal of the integrated circuit in order to transmit over it the field-strength setpoint value and the multipath signal value as a serial data word, and the range within which the intermediate frequency is to lie.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit for detecting a received signal and a corresponding circuit configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.


Solid polyethylene glycols (PEGs) are used in many pharmaceutical preparations as water soluble/absorbable excipients. However, because of their relatively lower molecular weight as compared to absorbable thermoplastic polyesters, commercially available PEGs, having a molecular weight of 10,000 or less are not suitable for use in preparing molded, or extruded, biomedical devices with high mechanical integrity, including high fracture resistance and flexural strength. Similarly, the commercially available PEGs cannot be used to form medical device coatings with sufficient flexibility and resistance to fracture to be clinically acceptable. On the other hand, exceptionally high molecular analogs of PEG, namely, polyethylene oxides having a molecular weight of 100,000 Da or more, can be used as tough coating, extrusion, or molding materials. Unfortunately, if such polyethylene oxides are used as soluble/absorbable implants, they are not fully excreted since their molecular weights exceed the cut-off molecular weight of 45,000 Da for passing through the kidneys. Other applications of polyethylene oxides having molecular weights exceeding 100,000 Da include their use (1) as highly water absorbent, swellable implants; and (2) in preparing highly viscous aqueous solutions at relatively low concentration. Once again, these applications cannot be associated with the use of these polymers as an absorbable/soluble implantable device, part of an absorbable implant, or a vehicle for a parenteral pharmaceutical formulation that are expected to absorb/biodegrade to extractable by-products. This situation evoked the need for a new approach to preparing derivatives of PEG, and allied polyalkylene glycols, that can be used effectively as coating or molded articles while allowing the release of molecular species having molecular weights that can be easily excreted through the kidneys. Accordingly, this invention deals with high to ultrahigh molecular weight derivatives of solid PEGs and allied polyalkylene glycols that can be readily absorbed and excreted.


As an information recording medium that record various contents such as movies, DVDs (Digital Versatile Discs) and BDs (Blu-ray (registered trademark) Discs) are mostly used.
An image, a voice, a caption, other graphic data and the like are recorded on each of the discs in a prescribed data recording format.
On the other hand, a display device, such as a television set, which displays images recorded on these discs, has been improved in resolution because of increase in the number of pixels in recent years.
For example, the television in the past has the number of pixels represented as the number of horizontal pixels × the number of vertical pixels=720 × 480. And the television in the past can display only SD (Standard Definition) images.
On the other hand, the Hi-vision television which is now widespread has the number of pixels represented as the number of horizontal pixels × the number of vertical pixels=1920 × 1080. And the Hi-vision television can display HD (High Definition) images (HD contents).
In addition, recently, the 4K television having four times the number of pixels in the HD image, i.e., having, for example, the number of horizontal pixels × the number of vertical pixels=4096 × 2160, and capable of displaying an image according to the so-called 4K standards (4K format) has been developed and now in a spreading stage.
The 4K television includes a display unit having the number of horizontal pixels × the number of vertical pixels=4096 × 2160, and is capable of displaying an image (4K image (4K contents) that is four times the HD image in resolution. In addition, a display device that displays an 8K image of a high resolution is also being studied.
As for contents having images of these resolutions, prescriptions in international standards (ITU) are provided with respect to a color space to be used. In other words, a color space corresponding to a color that can be output is prescribed.
As regards the SD image and the HD image, it is prescribed to make contents according to the following color space.
For the SD image, BT. 601, and
for the HD image, BT. 709.
In addition, as for the 4K image, it is demanded to support two color spaces: BT. 2020 and BT. 709. In other words, it is demanded to make contents capable of outputting colors corresponding to at least one of these two color spaces.
Note that, BT. 709 prescribes a color space having a wider color area as compared with BT. 601. In addition, BT. 2020 prescribes a wider color space as compared with BT. 709. The color space prescribed by BT. 2020 is nearly close to a color space observed by naked eyes, and output of natural colors with a higher precision is implemented.
Note that, display of contents having these color spaces is stated in, for example, PTL 1 (JP 2010-263598A) and the like.


The use of implantable stents in the vasculature and other body conduits has become commonplace since first proposed by Dotter in the 1960's. These devices were required to have a small, compacted diameter for insertion into the intended body conduit and transport, typically via a catheter, to a desired site for deployment, at which site they were expanded to a larger diameter as necessary to fit interferably with the luminal surface of the body conduit. They developed into balloon expandable stents that were expanded by plastically deforming the device with an inflatable balloon on which the expandable stent was mounted in the compacted state, the balloon being attached to the distal end of the catheter and inflated via the catheter. Self-expanding stents subsequently evolved, these devices being forcibly compacted to a small diameter and restrained at that diameter by a sleeve or other means. Following delivery to a desired site for deployment, they are released from the restraint and spring open to meet the luminal surface of the body conduit. These devices are typically made from nitinol metal alloys and typically rely on the superelastic and biocompatible character of this metal. Nitinol stents that rely on the shape memory attributes of that material are also known.
The evolution of implantable stents included the use of a tubular covering fitted to the stent, either to the outer or the luminal surface (or both surfaces) of the stent. These covered stents have generally come to be referred to as stent-grafts. The coverings were generally of a polymeric biocompatible material such as polyethylene terephthalate (PET) or polytetrafluoroethylene (PTFE). See, for example, U.S. Pat. No. 4,776,337 to Palmaz. This patent also describes that the covering may be optionally provided with perforations if desired for particular applications. Because of the open area provided by the perforations, such devices having perforated coverings may be considered to be a sort of hybrid stent and stent-graft, as are devices that include stent frame having metallic stent elements and polymeric elements connecting, covering or other otherwise being attached to the stent elements. The presence of the polymeric elements reduces the otherwise open space between the adjacent metallic stent elements, either very slightly or very substantially depending on the intended application and mechanical design.
Generally, a fully covered stent-graft can be considered to have a surface area (hereinafter Amax) equal to the circumference of the expanded stent multiplied by the length of the stent. For a conventional, open frame stent (as opposed to a stent-graft), the surface area represented by all of the stent elements is only a small portion of the maximum surface area Amax. The actual surface area covered by the stent, meaning the area covered by all components of the stent (including connecting elements) in their deployed state, is Astent. The porosity index, or P.I., describes the open area (the portion of the maximum surface area not covered by all components of the stent assembly) as a percentage of maximum surface area, wherein:P.I.=(1−(Astent/Amax))×100%.
The open area may be a continuous single space, such as the space between windings of a single helically wound stent element. Likewise the open area may be represented by the space between multiple individual annular or ring-shaped stent elements. The open area may also be represented by the total area of multiple apertures provided by either a single stent element (e.g., as shown by FIGS. 1B and 2B of U.S. Pat. No. 4,776,337) or by multiple stent elements providing multiple apertures. If multiple apertures are provided they may be of equal or unequal sizes. The use of a perforated graft covering or of polymeric elements in addition to metallic stent elements may also reduce the open area.
Stents having a porosity index of greater than 50% are considered to be substantially open stents.
In addition to the porosity index, the size of any aperture providing the open area must be considered if it is intended to cover only a portion of a stent area for a specific stent application. For multiple apertures, often the consideration must be for the largest size of any individual aperture, particularly if the apertures are to provide for a “filtering” effect whereby they control or limit the passage of biologic materials from the luminal wall into the flow space of the body conduit.
Various stent devices combining metallic stent elements with polymeric connecting elements are known; see, for example U.S. Pat. No. 5,507,767 to Maeda et al. Another is a stent provided with a flexible knitted sleeve having small open apertures in the fashion of chain link fencing, from InspireMD Ltd. (4 Derech Hashalom St., Tel Aviv 67892 Israel). Perforated stent-grafts are also known; see, for example WO00/42949.


Conventionally, forming of outer panel components of an automobile and the like have been carried out by press forming, in which a work is press processed using a press die. Generally, it is preferred that a press die used in a press process be such that the die surface, which is a contact surface with a work in the press die, be smoothed. By smoothing the die surface, it is possible to increase surface precision of a work (outer panel components) formed.
As a method for smoothing a die surface, the applicant proposes a processing method of a die surface and a die for which the processing method has been applied (see Patent Document 1) in which, first, a forming surface of a die is formed by a cutting process, then a synthetic resin is applied to the formed die surface, and next shot blasting is performed for smoothing a shape of the die surface. According to a method described in Patent Document 1, by a cutting process, it is possible effectively to grind high spots that are leftover from cutting generated on a die surface, thereby efficiently carrying out smoothing of a die surface.
Patent Document 1: Japanese Examined Patent Application Publication No. Hei 8-263


1. Field of the Invention
The present invention relates to a system for collecting scraps produced when various materials such as metals and plastics are processed by processing machines such as pressing machines and lathes and, more particularly, relates to a system which can efficiently collect scraps by the use of a suction force generated by a flow of high-pressure air.
2. Statement of the Prior Art
Heretofore, two typical systems have been used to collect scraps produced from a pressing machine, i.e. a press, which is one example of a machine for processing materials, when punching is carried out thereby.
In the first system, scraps are collected by simply receiving them as they fall due to their own weight. In this case, a box for collecting scraps is placed below the punching tool of the pressing machine, and scraps produced by punching of sheets fall due to their own weight and are received in the box and collected.
The second system is a dust collector. One example of such a dust collector system is disclosed in, e.g., Japanese Utility Model Laid-Open No. 61-24157. This system is designed as a dust collector for a portable air grinder, and is characterized by having an air ejector fixedly provided on a lid member of a cylindrical tank, an air filter provided in the tank at the downstream end of a suction pipe leading to the air ejector, a compressed-air inlet passage in the ejector connected with an air supply pipe through a valve, said lid member being provided with a dust collection opening, and a dust suction duct for connecting an abrasive wheel cover of the grinder to the dust collection opening. The air supply line to the grinder is connected by a T-joint to the compressed air inlet passage.
However, such conventional scrap collection systems have the following disadvantages. A problem with the first system which simply collects falling scraps is that scraps are often prevented from falling because instead they are unintentionally deposited in a mold or the like, and are responsible for making dents in the products molded thereby, thus resulting in an increase in the number of defective products, a shortening in the service life of tools and a lowering of the efficiency of the system.
A problem with the second system, namely the dust collector, is that the size of the duct collector becomes very large, so that not only is there a need to provide a space sufficient for its installation, but the complicated equipment also leads to an increased cost. Another problem is that as the sharpness of the processing tools deteriorates, scraps are likely to ascend while sticking to the punches because of a lack of suction force of the dust collector, or holes or openings are clogged by scraps.


1. Field of the Invention
The present invention relates to a balanced filter having the function of a balun performing conversion between unbalanced and balanced signals and the function of a filter performing band control, and more particularly to a balanced filter effective in reducing a filter size.
2. Description of the Related Art
Radio communication equipment comprises various RF (radio frequency) devices, such as an antenna, a filter, an RF switch, a power amplifier, an RF-IC, and a balun. Among these parts, resonance devices, such as an antenna and a filter, handle an unbalanced signal on the basis of the ground potential, while an RF-IC for producing and processing an RF signal handles a balanced signal. A balun functioning as an unbalance-balance transformer is therefore used when those two types of parts are connected to each other.
That type of balun is disclosed, for example, in the following Patent Documents:                Patent Document 1: Japanese Unexamined Patent Application Publication No. 2000-134009        Patent Document 2: Japanese Unexamined Patent Application Publication No. 2001-36310
The baluns disclosed in those Patent Documents are of the type that an unbalanced line and a balanced line are coupled through a coupling line. In the structures of those baluns, as shown in FIG. 3 of Patent Document 2, the unbalanced line and the balanced line are formed on one substrate, and the coupling line is formed on another substrate. The coupling line is laid over both the unbalanced line and the balanced line so that the unbalanced line and the balanced line are coupled to each other.
In a coupling mode of the balun thus constructed, as shown in FIG. 8 and explained in paragraph 0016 of Patent Document 2, “an unbalanced signal inputted from an unbalanced signal terminal 3 is propagated in the order of a first coupling line 101, a second coupling line 102, and a third coupling line 103”.
With the balun structures disclosed in Patent Documents 1 and 2, however, a resulting frequency characteristic is as shown in FIG. 4 of Patent Document 2. Accordingly, the disclosed structures are usable as a balun, but they have a difficulty in ensuring a band characteristic required for the filter.
On the other hand, many balanced filters each comprising a balun and a filter combined into an integral unit have recently been devised with the intent to reduce the size of radio communication equipment. That type of balanced filter is disclosed, for example, in the following Patent Document:                Patent Document 3: Japanese Unexamined Patent Application Publication No. 2003-087008
The balanced filter disclosed in Patent Document 3 has a structure in which a filter and a balun each designed using a ¼-wavelength resonator are combined on a dielectric substrate. A dielectric layer constituting the filter and a dielectric layer constituting the balun are formed one above the other in an integral structure.
Also, Patent Document 3 discloses a structure in which a DC power supply layer is formed in the balun, for making the balanced filter adaptable for the case where the RF-IC requires a balanced signal superimposed on a DC component. This structure is intended to realize a further reduction of the filter size.
However, the structure in which a balun section and a filter section are separately formed and integrated together has the problem as follows. When the filter function with a high attenuation is demanded, the filter section is required to have a multistage structure. Therefore, satisfactory flexibility in design cannot be ensured in a limited space, and a reduction of the size is very difficult to realize.


Field of the Invention
The present invention relates to a scintillator which emits light when radiation is applied thereto, and a radiation detector using the scintillator.
Description of the Related Art
In a flat panel detector (FPD) used in clinical practice or the like, X-rays which pass through a subject are received by a scintillator, and light emitted from the scintillator is detected by light receiving elements serving as a detector. The light receiving elements are arranged as a two-dimensional array. Japanese Patent Application Laid-Open No. 2001-58881 discloses a scintillator which exhibits an optical waveguide property in order to prevent light emitted by the scintillator from spreading to an adjacent light receiving element under such circumstances. Japanese Patent Application Laid-Open No. 2001-58881 discloses a technology in which, after sacrificial fibers aligned in a direction in which light is sought to he waveguided and scintillator powder are sintered, the sacrificial fibers are removed to obtain a porous scintillator, and pores therein are filled with an absorbing member or the like.


The invention relates to semiconductor memory devices and, more particularly, to a method for fabricating a non-volatile memory device with a charge trapping layer.
Non-volatile memory devices, which are electrically programmable and erasable devices, are used mainly in electronic components that require data retention even when no power is supplied. Such non-volatile memory devices typically have a floating gate structure. According to the existence or nonexistence of charges in a floating gate, a program operation or an erase operation is performed. As the degree of integration of semiconductor memory devices has increased, non-volatile memory devices with new cell structures have been required. Such non-volatile memory devices with new cell structures include non-volatile memory devices with a charge trapping layer. Such non-volatile memory devices with a charge trapping layer are classified as silicon-oxide-nitride-oxide-silicon (SONOS) structures and metal-aluminum oxide-nitride-oxide-silicon (MANOS) structures, depending on the characteristics of the charge trapping layer. According to a bias voltage applied to non-volatile memory devices with such structures, charges are stored in or discharged from the charge trapping layer to electrically perform a program operation or an erase operation.
FIG. 1 illustrates a cross-sectional view of a conventional non-volatile memory device with a charge trapping layer 110. Referring to FIG. 1, the non-volatile memory device with the charge trapping layer 110 includes a tunneling layer 105, the charge trapping layer 110, a blocking layer 115, and a control gate electrode 120 stacked on a semiconductor substrate 100. The blocking layer 115 is disposed between the control gate electrode 120 and the charge trapping layer 110 and generally comprises an aluminum oxide (Al2O3) film. Since the quality of the aluminum oxide (Al2O3) film is not high and a grain size of the aluminum oxide (Al2O3) film is small, a leakage current may occur. When the non-volatile memory device is fabricated with the quality of the film not being sufficiently high, characteristics of data retention may be adversely affected. To address this limitation, a thermal treatment process is performed to increase (i.e., “densify”) the quality of the film of the blocking layer 115, after the blocking layer 115 is deposited. A method for the film of the blocking layer 115 includes a process of depositing the blocking layer 115 at a high temperature ranging from approximately 600° C. to approximately 800° C., or a thermal treatment process performed at a high temperature after a deposition process. However, the thermal treatment process performed at the high temperature adversely affects a layer deposited below the blocking layer 115 or a profile of an impurity region formed in the semiconductor substrate 100. Also, temperature and run time of the thermal treatment process are limited to obtain the desired high-quality of the blocking layer 115 using the process of depositing the blocking layer 115 at the high temperature or the thermal treatment process after the deposition process. To address these limitations, a method is required, which can improve the characteristics of the film quality of the blocking layer 115 without affecting a layer below the blocking layer 115 or the semiconductor substrate 100, thereby improving the characteristics of the non-volatile memory device.


In a MOS transistor that amplifies radio frequency signals in, for example, WiMAX, a reduction in the size of each element is required. Thus, for example, the width and length of the gate of an amplifying MOS transistor are subject to variation during manufacturing. Thus, when MOS transistors are cascaded, and amplification is performed, necessary gain may not be achieved under the influence of a variation in gain. Gain “gain” of a MOS transistor can be expressed by equation 1 described below. In equation 1, R represents resistance associated with a MOS transistor, and gm represents mutual conductance.gain=gm·R  [equation 1]
According to the foregoing equation, the gain of a MOS transistor may be maintained constant by compensating for the mutual conductance gm. Thus, hitherto, a mutual conductance compensation circuit that compensates for the mutual conductance of a MOS transistor has been provided in an amplifier circuit.
FIG. 1 indicates the components of an amplifier circuit provided with mutual conductance compensation circuits. The amplifier circuit includes an amplifier unit 9, a first mutual conductance compensation circuit 7, a second mutual conductance compensation circuit 8, and MOS transistors 4, 5, and 6 for connecting the circuits to each other.
The amplifier unit 9 includes a first MOS transistor 1, a second MOS transistor 2, a third MOS transistor 3, a first inductor 15, and a second inductor 16. One end of each of the first inductor 15 and the second inductor 16 is connected to a drain-side voltage source AVD. The other ends of the first inductor 15 and the second inductor 16 are connected to the drains of the second MOS transistor 2 and the third MOS transistor 3, respectively. The source of each of the second MOS transistor 2 and the third MOS transistor 3 is connected to the drain of the first MOS transistor 1. Input signals are input to the gate of each of the second MOS transistor 2 and the third MOS transistor 3. The source of the first MOS transistor 1 is connected to a ground AVS.
One end of the first mutual conductance compensation circuit 7 is connected to the drain-side voltage source AVD. The first mutual conductance compensation circuit 7 is a circuit that generates current for controlling mutual conductance so that the mutual conductance is maintained constant. The other end of the first mutual conductance compensation circuit 7 is connected to the drain of the fourth MOS transistor 4. The source of the fourth MOS transistor 4 is connected to the ground AVS. The gate of the fourth MOS transistor 4 is connected to the drain of the MOS transistor 4. Moreover, the gate of the fourth MOS transistor 4 is connected to the gate of the first MOS transistor 1.
One end of the second mutual conductance compensation circuit 8 is connected to the drain-side voltage source AVD. The second mutual conductance compensation circuit 8 is a circuit that generates current for controlling mutual conductance so that the mutual conductance is maintained constant. The other end of the second mutual conductance compensation circuit 8 is connected to the drain of the fifth MOS transistor 5. The source of the fifth MOS transistor 5 is connected to the drain of the sixth MOS transistor 6. The source of the sixth MOS transistor 6 is connected to the ground AVS. The gate of the sixth MOS transistor 6 is connected to the gate of the first MOS transistor 1 and the gate of the fourth MOS transistor. The gate of the fifth MOS transistor 5 is connected to the drain of the fifth MOS transistor 5. Moreover, the gate of the fifth MOS transistor 5 is connected to the respective gates of the second MOS transistor 2 and the third MOS transistor 3 via resistors 17 and 18.
The first mutual conductance compensation circuit 7 generates current such that the mutual conductance gm of the first MOS transistor 1 is maintained constant and mirrors bias to the first MOS transistor 1, using the fourth MOS transistor 4.
The second mutual conductance compensation circuit 8 generates current such that the mutual conductance gm of the second MOS transistor 2 and the third MOS transistor 3 is maintained constant and mirrors bias to the second MOS transistor 2 and the third MOS transistor 3, using the fifth MOS transistor 5.
As a MOS transistor becomes smaller, manufacturing errors in the width and length of the gate of a MOS transistor become large, resulting in a difference in the mutual conductance gm, as indicated in FIG. 2. FIG. 2 indicates characteristics of a circuit in FIG. 1. In FIG. 2, a maximum value characteristic Max represents a MOS transistor having the largest mutual conductance. A minimum value characteristic Min represents a MOS transistor having the smallest mutual conductance. Reference letter Typ represents a MOS transistor having mutual conductance of a standard value characteristic. The standard value characteristic Typ is a characteristic based on the gate electrode width and the gate electrode length set in the design stage. It is assumed here that overdrive voltage Vod=gate-source voltage Vgs−threshold voltage Vth.
In FIG. 2, in order to compensate for the gain of a MOS transistor the mutual conductance gm of which is lower than that in the standard value characteristic Typ, as indicated by the minimum value characteristic Min, the overdrive voltage Vod needs to be increased. In order to compensate for the mutual conductance gm of each MOS transistor only by bias, Vgs needs to be increased until Vod=Vod0. However, even when Vgs is increased until Vod=Vod0, as indicated in FIG. 2, in a MOS transistor having the minimum value characteristic Min, in which the mutual conductance gm is far less than that in the standard value characteristic Typ, Vgs cannot be increased until the mutual conductance gm reaches mutual conductance gm1 in the standard value characteristic Typ. Thus, when the mutual conductance gm decreases, it may be impossible to compensate for the gain only by controlling the gate-source voltage Vgs of a MOS transistor.
On the other hand, in the case of a MOS transistor the mutual conductance gm of which is higher than that in the standard value characteristic Typ, as indicated by the maximum value characteristic Max, in order to compensate for the gain, the gate-source voltage Vgs needs to be controlled to be decreased so that Vod=Vod2. In this case, the mutual conductance gm can be compensated for. However, the overdrive voltage Vod decreases, and thus the amplitude of an input signal that can be linearly amplified decreases. That is, the linearity is deteriorated by compensating for the mutual conductance gm.
When variations occur in elements under the influence of the manufacturing process, the compatibility of compensation for the gain of a MOS transistor with compensation for the linearity cannot be achieved only by controlling the gate-source voltage Vgs.
Japanese Laid-open Patent Publication No. 2000-174568 is known as a technique for bias control for a variation in the gain of the amplifier unit 9.


Recent advances in both solid-state lighting and rechargeable batteries, has enabled the generation of energy-efficient, compact portable lighting devices that people can carry with them. A portable lighting device is a lighting device that can provide its illumination function without a wired power supply, typically being battery powered by means of a battery on board the lighting device, or potentially instead being powered by another type of on-board power supply such as a manual dynamo, or even being powered using a wireless power transfer (WPT) technique based on radiative electromagnetic induction. A portable lighting device can thus be taken by the user from one location to the next. For instance, a portable lighting device may be taken from a living room to a garden terrace or to a bathroom to create a cozy or romantic ambience.
Typically the light emitted by known portable lighting devices can be controlled using one or more switches located on the portable lighting. Other portable lighting devices include touch-sensitive surfaces that may be at least partially capacitive. A user's touch may be detected based on a change in that capacitance, and light emitted by one or more light sources of the portable lighting device may be altered based on the nature of the user's touch.


1. Field of the Invention
This invention relates to semi-polar optoelectronic devices and methods of fabrication thereof, and in particular, semi-polar III-nitride optoelectronic devices on m-plane substrates with miscuts less than +/−15 degrees in the c-direction.
2. Description of the Related Art
(Note: This application references a number of different publications as indicated throughout the specification by one or more reference numbers within brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications is incorporated by reference herein.)
The anticipated high commercial demand for next-generation display technologies, such as miniature mobile projectors and high-definition fly-spot displays, has significantly accelerated the development of direct-emission green laser diodes (LDs). Technical criteria for such applications require LDs to have high efficiency, reliability, compactness, and modulation response capabilities [1]. While the wurtzite (Al,Ga,In)N-based material system is largely agreed upon as the leading candidate for green optoelectronic devices, a general consensus behind which crystal plane is optimal for epitaxial growth has yet to be reached.
Continuous-wave (CW) operation of LDs in the green spectral region has been demonstrated for devices grown on the conventional c-plane of GaN [2-4]. These devices, however, suffer from parasitic internal electric fields that give rise to the quantum-confined stark effect (QCSE) which decreases the quantum-well (QW) radiative recombination rate, and causes a blue-shift in emission wavelength with increasing carrier injection [5]. In addition, QCSE becomes more significant for long wavelength optoelectronic devices due to the increased lattice mismatch between the In-rich InGaN QWs and the barrier [2].
To circumvent polarization effects, researchers have demonstrated operation of LDs grown on the nonpolar m-plane orientation of the wurtzite crystal [6]. While a promising candidate for high power blue LDs, m-plane LDs has so far been limited to 500 nm lasing emission due to the formation of stacking faults in the active region [7-11].
Various semi-polar (or semipolar) planes, such as (10-11) and (11-22), have been also investigated as alternative growth planes [12-13]. Recently, researchers have reported lasing in the green spectral region from high quality InGaN QWs grown on the semi-polar (20-21) plane [14-15]. Further studies have shown that green emitting QWs grown on (20-21) exhibit high compositional homogeneity with localization energy values lower than that reported for c-plane [16]. However, quaternary AlInGaN cladding layers were needed in (20-21) LDs to achieve sufficient modal confinement without generating strain-induced misfit dislocations (MDs) [17]. While the use of quaternary AlInGaN cladding layers presents a solution for semi-polar planes with low critical thickness, a simple AlGaN cladding-free structure with high composition InGaN waveguides would be much more attractive from a mass-production point of view [7, 15, 18].
What is needed are improved methods for optoelectronic device growth. The present invention satisfies this need.


Users of a multimedia content distribution network (MCDN) may be provided a wide range of video assets to select from. A service provider operating the MCDN may be faced with various quality control issues related to the video assets and the performance of MCDN equipment. Feedback about MCDN performance issues are typically obtained via information gleaned from user support requests and/or costly support visits to user locations.


The present invention relates to a method for manufacturing a dynamic quantity detection device that is formed by bonding a semiconductor chip that includes a detection element for detecting a dynamic quantity to a stand using a bonding layer.
The publication JP-A-2000-241273 discloses such a method in the manufacturing process of a discrete pressure detection device 100 shown in FIGS. 3A and 3B.
As shown in FIGS. 3A and 3B, the discrete pressure detection device 100 includes a metal stem 20, a discrete semiconductor chip 30, and a glass layer 40. The metal stem 20 includes a disk-like diaphragm 10. The semiconductor chip 30 is bonded to the diaphragm 10 with the glass layer 40. The discrete semiconductor chip 30 is in contact with the glass layer 40 at a first surface 31 of the discrete semiconductor chip 30. The diaphragm 10 is in contact with the glass layer 40 at a first surface 11 of the diaphragm 10. The discrete semiconductor chip 30 includes four gauges (detection elements) 51, 52, 53, 54, or four piezo resistors 51, 52, 53, 54. The gauges 51, 52, 53, 54 are located in a second surface 32 of the chip 30, which is opposite to the first surface 31. The glass layer 40 is, for example, made of a low melting point glass.
When a medium that transmits pressure to be detected is introduced into the stem 20 to apply the pressure to a second surface 12 of the diaphragm 10, which is opposite to the first surface 11, the diaphragm 10 strains and the discrete semiconductor chip 30 also strains synchronously to change the resistances of the gauges 51, 52, 53, 54. The resistance changes are processed by a processing circuit, which is not shown in the figure, in order to detect the pressure. The processing circuit is provided in another chip outside the discrete semiconductor chip 30 and includes processing circuit elements such as a bipolar transistor and a trimming resistor.
Because the processing circuit is located in another chip, the system that includes the discrete pressure detection device 100 and the chip including the processing circuit is relatively bulky. To address the issue of the bulkiness of the system, the inventors of the present invention attempted to integrate gauges 51, 52, 53, 54 and processing circuit elements for making up a processing circuit equivalent to the foregoing processing circuit in an intelligent semiconductor chip 33 and to form an intelligent pressure detection device 101, which is shown in FIGS. 4A and 4B. The processing circuit elements are included in a processing circuit area 70.
However, it turned out that the following issue was caused when the intelligent pressure detection device 101 was manufactured using the intelligent semiconductor chip 33. When the discrete pressure detection device 100 of FIGS. 3A and 3B is manufactured, the discrete semiconductor chip 30 is normally bonded to the metal stem 20 by sintering the glass layer 40 at a temperature of approximately 500° C. However, when the glass layer 40 was sintered at a temperature of approximately 500° C. the characteristics of a bipolar transistor, which is included in the processing circuit area 70 as a processing circuit element, changed.
The characteristics change of the bipolar transistor may be caused by the following mechanism. Although not shown in the figure, the intelligent semiconductor chip 33 includes a substrate, which is made of silicon. Wiring lines, which electrically interconnect elements such as a bipolar transistor located in a surface of the substrate, an oxide film, which insulates the wiring lines, and a passivation film, which protects the wiring lines and the oxide film, are located on the surface of the substrate. The oxide film and the passivation film are formed in the atmosphere that contains hydrogen in the wafer manufacturing process, in which a wafer is processed for manufacturing the intelligent semiconductor chip 33.
When the oxide film and the passivation film are formed, the hydrogen in the atmosphere is absorbed into the oxide film and the passivation film as hydrogen ions. The dangling bonds of the silicon atoms located at the interface between the surface of the substrate and the oxide film are terminated by the hydrogen ions. At a subsequent step in the wafer manufacturing process, the wafer is heated at a high temperature in the atmosphere that contains hydrogen. During the step, the amount of hydrogen ions in the oxide film and the passivation film can increase as hydrogen in the atmosphere is absorbed, and the bonds between the hydrogen-terminated silicon atoms and the terminating hydrogen atoms at the interface between the surface of the substrate and the oxide film may be broken due to the high temperature.
At a later step, the wafer is diced to form the intelligent semiconductor chip 33. Because no heat is applied to the intelligent semiconductor chip 33 during the dicing step, the characteristics of the bi-polar transistor such as current amplification factor in the wafer manufacturing process is substantially determined by the concentration of the hydrogen ions resulting from the above high temperature treatment.
However, when the glass layer 40 is sintered for bonding the intelligent semiconductor chip 33 to the metal stem 20, the processing circuit area 70 is heated. As a result, the hydrogen atoms bonded to the silicon atoms at the interface between the surface of the substrate and the oxide film move away from the silicon atoms, and the hydrogen ions absorbed in the oxide film migrate toward the passivation film or get outgassed into the atmosphere.
As a result, electrons trapped by the hydrogen atoms included in the oxide film are released above the surface of the bipolar transistor located in the processing circuit area 70, and the transistor injection efficiency increases. Consequently, the base current increases, and the collector current also increases among the currents that flow through the base, the emitter, and the collector of the bipolar transistor. Thus, the current amplification factor, which is one of the characteristics of the bipolar transistor, increases.