The invention relates to an expansion joint for part of a railway track disposed on a foundation which has a stock rail with a stock rail head, web and foot and a tongue movable with respect to and along said stock rail, upon which tongue at least one fastening means acts to press it onto the head of the stock rail.
In known expansion joints, also designated as expansion devices and permitting a movement between the structure and the rail in the vicinity of bridges, for example, a positive connection is made to permit movement of the tongue relative to the stock rail. To this end, a tongue of solid rail profile can be fixed between the stock rail and a clamming jaw disposed stationarily on the opposite side. The foot of the tongue and that of the stock rail are disposed on a common foundation at the same level. As a result, the stock rail is supported substantially on the foundation only by the stock rail half facing away from the tongue. Instabilities are compensated for by the stock rail being attached with supports and angle pieces. This entails additional maintenance work.
A conventional rail joint is described in DE 30 16 492 A1, for example. There is a slight clearance between the clamping jaws and the facing web surface of the tongue, permitting the requisite movability of the tongue in relation to the stock rail. This too can led to tipping of the tongue or the rail.


The following includes information that may be useful in understanding the present invention(s). It is not an admission that any of the information provided herein is prior art, or material, to the presently described or claimed inventions, or that any publication or document that is specifically or implicitly referenced is prior art.


The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs and the IC is then referred to as a complementary MOS or CMOS circuit. Certain improvements in performance of FET ICs can be realized by forming the FETs in a thin layer of semiconductor material overlying an insulator layer. Such semiconductor on insulator (SOI) FETs, for example, exhibit lower junction capacitance and hence can operate at higher speeds. It is advantageous in certain applications, however, to fabricate at least some devices in the semiconductor substrate that supports the insulator layer. The devices formed in the substrate, for example, may have better thermal properties and can support higher voltages than devices formed in the thin semiconductor layer.
As the complexity of the integrated circuits increases, more and more MOS transistors are needed to implement the integrated circuit function. As more and more transistors are designed into the IC, it becomes important to shrink the size of individual MOS transistors so that the size of the IC remains reasonable and the IC can be reliably manufactured. Shrinking the size of an MOS transistor implies that the minimum feature size, that is, the minimum width of a line or the minimum spacing between lines, is reduced. MOS transistors have now been aggressively reduced to the point at which the gate electrode of the transistor is less than or equal to 45 nanometers (nm) in width. Methods previously used to fabricate devices in the substrate of an SOI structure, however, have not be able to achieve the same minimum feature size in substrate devices as are realized in the devices formed in the thin semiconductor layer.
Accordingly, it is desirable to provide a method for fabricating SOI devices having minimum feature size. In addition, it is desirable to provide a self aligned method for fabricating SOI devices having minimum feature size substrate devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.


In order to explain the background of the present invention in detail, reference will be made to FIG. 1, which shows a circuit diagram of a prior art semiconductor memory device. There are provided enhancement type MOS field-eeffect transistors 1,2,3 and 4, hereinafter referred to as MOSFETs. The drains of the P-channel MOSFET 1 and N-channel MOSFET 2 are connected to each other, and the gates thereof are connected to each other. The source of the MOSFET 1 is connected to a power supply terminal 5, and that of the MOSFET 2 is connected to ground, thus constituting a complementary MOS (hereinafter referred to as CMOS) inverter 30a. Likewise, the P-channel MOSFET 3 and the N-channel MOSFET 4 constitute a CMOS inverter 30b. With these two inverters 30a and 30b a bistable circuit, that is, a flip-flop, is formed. More particularly, the outputs of the two inverters 30a and 30b are connected to the inputs of the mating inverters 30b and 30a. In other words, the drains of the P-channel MOSFETs 1 and 3, and of the N-channel MOSFETs 2 and 4 are connected to the gates of the N-channel MOSFETs 4 and 2, and of the P-channel MOSFETs 3 and 1, respectively. In this way a one bit memory cell 30 is constructed.
The N-channel MOSFETs 6 and 7 which are used for transfer gates to control the writing-in and the reading-out operation, have drains (or sources) connected to the drain of the MOSFETs 1 and 2, and that of the MOSFETs 3 and 4, respectively, and have sources (or drains) connected to bit lines 8 and 9 respectively, which function as information lines for writing-in as well as reading-out. The gates of the N-channel MOSFETs 6 and 7 are connected to a word line 10 which functions as a selector line for writing-in as well as reading-out.
The sources and gates of the N-channel MOSFETs 11 and 12 are connected to power supply terminals 5, and their drains are connected to the bit lines 8 and 9. An information input signal line 13 is connected to the gates of the P-channel MOSFET 14 and N-channel MOSFET 15, which constitute a writing-in circuit 40. In addition, the information input signal line 13 is connected to the drain (or source) of the N-channel MOSFET 16, which is used for a gate to control the information to be written in. The source (or drain) of the MOSFET 16 is connected to the bit line 9, and its gate is connected to a writing-in control signal line 17 which is designed to control the writing operation of the memory cell 30. The drains of the MOSFETs 14 and 15 are connected to the drain (or source) of the N-channel MOSFET 18, which is used for a gate to control the data to be written in. The source (or drain) of the N-channel MOSFET 18 is connected to the bit line 8, and its gate is connected to the writing-in control signal line 17. In this way the MOSFETs 16 and 18 can transmit the output from the writing-in circuit 40 to the bit lines 8 and 9 through between the drain and source thereof.
In operation, the memory cells 30 and the MOSFETs 6, 7 are arrayed in matrix in plurality. A desired memory cell is directly selected by the random access method, in or from which memory cell the data is written or read out. While the memory cell stores data, the word line 10 is kept at almost zero voltage, thereby turning off the MOSFETs 6 and 7. The memory cell 30 constituted by the MOSFETs 1, 2, 3 and 4 is electrically separated from the bit lines 8 and 9. The memory cell 30 is in one of two stable states when the gates of the MOSFETs 1 and 2 are kept "L" (low). At this time the MOSFET 1 is in ON state with its drain being kept "H" (high). Accordingly, the gates of the MOSFETs 3 and 4 become "H", thereby turning on the MOSFET 4 with placing its drain "L".
When the memory cell 30 is in this stable state, information can be written therein by applying voltage corresponding to the information to the bit lines 8 and 9, and applying the voltage "H" to the word line 10 so as to address the memory cell 30.
Now, suppose that the logic "1" is to be written in the memory cell 30. The voltage "H" is applied to the writing-in control signal line 17, thereby turning on the MOSFETs 16 and 18, and the voltage "H" corresponding to the logic "1" is applied to the information input signal line 13. In this way the bit line 9 is kept "H" through the MOSFET 16. In addition, the gates of the MOSFETs 14 and 15 are kept "H", thereby turning off the MOSFET 14 and turning on the MOSFET 15. Thus the drains of the MOSFETs 14 and 15 become "L", thereby placing the bit line 8 "L" through the MOSFET 18.
At this stage, when the word line 10 is placed "H", the MOSFETs 6 and 7 are turned on, thereby enabling the potentials in tne bit 1ines 8 and 9 to be impressed on the memory cell 30. As a result, the MOSFET 1 is turned off whereas the MOSFET 2 is turned on, thereby reversing the states of the MOSFETs 1, 2, and 3, 4. In this way the memory cell 30 enter into the other stable state which means storing the information "1". Subsequently, the word line 10 and the writing-in control signal line 17 are returned to "L". With this, the writing operation ends.
When information is to be read out from the memory cell 30, voltage of the same amplitude as that applied while writing-in operation, is impressed on the word line 10, thereby turning on the MOSFETs 6 and 7. This ensures that the electric charges stored in the bit lines 8 and 9 through the MOSFETs 11 and 12 are absorbed by the information stored in the memory cell 30, whereby a potential difference is given to between the bit lines 8 and 9 in accordance with the information stored in the memory cell 30. In this way the stored information is transmitted to the bit lines 8 and 9, and thereafter it is amplified as by a sense amplifier, and is output to the outside.
When this reading operation is to be performed, it is the common practice to charge up the bit lines 8, 9 previously up to the "H" voltage through the MOSFETs 11, 12. This is important in preventing an erroneous writing of the information in the bit lines onto the memory cell, which is likely to occur when the MOSFETs 6, 7 are turned on in a situation where the bit lines having a large parasitic capacity have information opposite to that stored in the memory cell.
Under the prior art semiconductor memory device mentioned above, the bit lines are constantly charged in spite of the fact that the charging-up is required only when a reading-out operation is to be performed. As a result, the writing information and the electric charges in the bit lines come into collision when information is to be written in. This increases the consumption of electricity, and slows down the operational speeds.
One of prior art methods of controlling the writing and the reading operation is a technique disclosed in the article entitled "A 4K Static 5V RAM" by Jeffrey M. Schlageter, Nagab Jayakumar, Joseph H. Kroeger and Vahe Sarkissian, which was prepared for the 1976 International Solid-State Circuit Conference. The article teaches that by disabling the Chip Enable signal, the bit and data lines are equalized to an intermediate voltage of the power supply voltage.


In an inkjet recording device comprising a recording head for separately discharging ink for primary colors of cyan, magenta, and yellow and black in response to a recording signal based on image data, there are problems that (1) a secondary color of red, green, or blue is difficult to represent by adjusting primary colors and that (2) a good image cannot be obtained because of severe color mixing at the boundary between different secondary colors. To alleviate these problems, there is an inkjet recording device comprising a recording head for separately discharging ink for seven colors of cyan, magenta, yellow, black, red, green, and blue in response to a recording signal based on image data (see Patent Document 1).
According to the technique disclosed in Patent Document 1, ink per se can be adjusted without complex color processing, and the secondary colors of red, green, and blue are recorded with ink of red, green, and blue, respectively. This can reduce ink injection quantity and prevent the occurrence of blur at the boundary between different colors, which would otherwise cause problems especially in secondary colors.    [Patent Document 1] JP 8-244254 A


1. Field of the Invention
The present invention relates to a method for fabricating a FinFET transistor device, and more particularly to a method of fabricating a double gate MOSFET with a capability of inhibiting the depletion effect of the conductive gate while operating this device, which can hence elevate the device drive-on currents.
2. Description of the Prior Art
In the past several years, significant progress has been made for the scaling of classical planar MOSFET (metal-oxide-semiconductor field effect transistor) structure to the gate lengths below 65 nm. Despite difficulties in fabrication, sub-20 nm physical gate length MOSFETs have recently been demonstrated. However, further scaling of the planar structure below 50 nm becomes increasingly challenging due to excess leakage, degradation in mobility, and a variety of difficulties within the device processing. Therefore, alternative MOSFET structures and new process technologies need to be explored. The effective control of leakage in nano-scale transistors will be extremely important for high-performance densely packed chips such as microprocessors.
The double gate MOSFET, featuring excellent short-channel behavior and relaxed requirements for aggressive scaling of gate dielectrics and junction depths, is attractive for high-performance low power applications. Fully-depleted vertical double gate devices with symmetric gate structures feature a low vertical electrical field in the channel which is favorable to carrier transport. The FinFET is a promising vertical double gate structure, which has been demonstrated in the last few years at gate lengths ranging from 100 nm to 10 nm. Unlike other reported vertical double gate structures, the FinFET can be fabricated with minimal deviation from the industry standard CMOS process.
The FinFET transistors were fabricated on SOT (silicon-on-insulator) wafers with a modified planar CMOS process. FIG. 1A to FIG. 1F is an illustration of the general process flow for fabricating the FinFET transistor. At first, referring to FIG. 1A, a substrate such as a silicon on insulator (SOI) structure is provided, including a silicon substrate 10, a buried oxide layer (BOX) 11 and a silicon layer 12 on the buried oxide layer 11. A cap oxide layer 13 was thermally grown on the silicon layer 12 to relieve the stress between the ensuing nitride hard mask and the silicon layer 12. A silicon nitride layer 14 was deposited on the cap oxide layer 13, to serve as a hard mask.
After the hard mask deposition, a photoresistor 15 is applied to define the hard mask through use of optical lithography, electron beam lithography, X-ray lithography, or other conventional means to produce a chemical etchant mask. Then, referring to FIG. 1B, after the mask definition, an etch process is used to pattern the hard mask and the device fin structure including a silicon drain region (not shown) and a silicon source region (not shown) connected by a silicon fin or channel 12, and thereafter the photoresistor 15 is removed. Referring to FIG. 1C, a thin sacrificial oxidation process maybe used to form a sacrificial oxide 16 on the two parallelly opposing sidewalls of the silicon fin 12 to repair any damage done to the fin surface during the etch process. Oxidation may also be used to reduce the fin width, thereby allowing sub-lithography dimensions to be achieved. The threshold (Vt) implants of NMOS and PMOS can be subsequently proceeded. Referring to FIG. 1D, the hard mask of the silicon nitride layer 14 and the thin sacrificial oxide 16 are removed to retain the cap oxide layer 13 on the silicon fin 12. Referring to FIG. 1E, a gate oxide 17 is grown or deposited on the two opposing sidewalls of the silicon fin 12. Then, referring to FIG. 1F, a polysilicon gate material is deposited over the surface of the silicon fin 12, a gate mask is defined on the polysilicon gate material and then the underlying gate material is etched to form a polysilicon gate 18 with the etching stopping on the cap oxide 13 and the buried oxide layer 11. An ion implantation process is performed to implant dopants in the polysilicon gate 18 for a desired threshold voltage Vth. Referring to FIG. 2, the source/drain regions 12A and 12B are also doped to make them electrically conductive electrodes in the subsequent source/drain ion implantations. Referring to FIG. 1F again, however, the distribution of the dopants in the polysilicon gate 18 is a gaussian distribution along the depth of the polysilicon gate 18. The portions of the polysilicon gate 18 nearby the bottom corners contained between the gate oxide 17 and the buried oxide layer 11 would have been more lightly doped, and have a larger resistance. Furthermore, upon operating the FinFET transistor, a depletion of the polysilicon gate 18 easily occurs, which in turn thickens the equivalent oxide thickness (EOT) of the gate dielectric 17, resulting in the reduction of the drive current of the FinFET transistor.
Accordingly, it is an intention to provide a method of fabricating a FinFET transistor device, which can alleviate the problem encountered in the conventional process for fabricating the FinFET transistor.


The present invention relates to a method for wave soldering printed circuit boards wherein a solder coating is applied only where needed.
A usual automatic wave soldering apparatus includes a pair of endless chain conveyors driven to advance a printed circuit board at a constant speed from the entrance to exit ends of the apparatus. With the printed circuit board held by gripping fingers, the board is first carried to a fluxer where a foam or spray of flux is applied to the underside of the board. The printed circuit board is then carried over preheaters where the temperature of each board is elevated to approximately 110° C. to 130° C. so as to evaporate excess flux solvent, activate the flux and minimize thermal shock to the printed circuit board. After the printed circuit board is brought to such a preheat temperature, the board is passed over a solder reservoir to receive solder. The board is finally transported to a cool down zone where the solder is cooled to solidify.
Typically, pin grid alley modules and dual in-line packages are loaded onto one side of a printed circuit board, with their terminals or leads projecting downwardly through apertures in the printed circuit board. To increase packaging density, a number of surface mounted devices and connectors are loaded onto the other, underside side of the printed circuit board. Problems have arisen from wave soldering such a printed circuit board. Too much heat occurs on the underside of the board, when contacted with a solder wave, and tends to damage the surface mounted devices.
Attempts have been made to locally apply solder to preselected conductor areas on a printed circuit board, but not to those areas where surface mounted devices and connectors are mounted. In one known method, flux is locally spayed onto preselected conductor areas on a printed circuit board. The fluxed board is then preheated by a stream of warm gas to evaporate flux solvent. Thereafter, the board is positioned over a plurality of solder wave nozzles arranged within a solder reservoir. At this time, the solder wave nozzles are brought into alignment with a plurality of sets of preselected areas on the printed circuit board. A pump is arranged within the solder reservoir to force heated molten solder to flow upwardly through the solder wave nozzles so as to form solder waves. The preselected areas on the printed circuit board are contacted with the respective solder waves to make soldered joints. The height of the solder waves is then lowered until it becomes equal to the surface level of the molten solder within the solder reservoir. The position of the board is maintained until the solder solidifies. Finally, the board is delivered to a cool down zone wherein the printed circuit board is cooled.
This known method has proven to be effective for eliminating heat damage to sensitive electronic components such as surface mounted devices, but the method suffers from certain disadvantages. One problem is the attachment of solder oxides, better known as dross, and carbonized flux to soldered joints on a printed circuit board. Part of the molten solder tends to remain on the inner wall of the solder wave nozzles when the molten solder is immediately returned to the solder reservoir. The solder, typically composed of tin and lead, has a tendency to oxidize in the atmosphere. The resulting oxides are detrimental to the quality of the soldered joints. Also, part of the flux which has previously been applied to the soldered joints could be attached to the inner wall of the solder wave nozzles. This flux is carbonized by the heat from the molten solder. The resulting carbide could be attached to the inner wall of the solder wave nozzles. The oxides and the carbide will be separated from the inner wall of the solder wave nozzles when the molten solder within the solder reservoir is pumped up through the solder wave nozzles to process a next printed circuit board. The oxides and the carbide could be attached to soldered joints formed on the next printed circuit board. Another problem is the formation of icicles, solder bridges and other imperfections in the solder. When the conductor areas on the board are not sufficiently preheated, the solder solidifies before the conductor areas are completely wetted. This results in faulty solder connections. Also, such imperfections occurs when the solder wave is detached from the printed circuit board too fast.
Accordingly, it is an object of the present invention to provide a method for locally applying solder to preselected conductor or solderable areas on a printed circuit board, which prevents the occurrence of icicles, bridges and other solder imperfections, and which can force solder into through holes and other hard-to-reach areas to be soldered.


1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device capable of increasing an effective channel length and width, which has a plurality of grooves and a method of fabricating the same.
2. Description of the Related Art
As semiconductor memory devices are highly integrated, a width of a gate electrode of a MOS transistor is reduced to about 0.1 μm and a channel length of the MOS transistor must be reduced. With reduced channel length, electrons can easily pass a gate insulating layer of the MOS transistor, and the so called “hot carrier effect” occurs because an electric field between a source and a drain of the MOS transistor is strengthen by the reduced channel length, causing flow of leakage current. Thus, the short channel effect from a reduced channel length of the MOS transistor adversely affects characteristics of the MOS transistor.
One way to alleviate the short channel effect is by elongating the channel length without changing a design rule of the gate electrode.
FIGS. 1A to 1C are cross-sectional views of structures illustrating a conventional fabricating method of a semiconductor device having grooves for elongation of effective channel length.
Referring to FIG. 1A, nitride layer patterns 12 are formed on a semiconductor substrate 10 having a device isolation layer (not shown) to expose a channel region of a MOS transistor. Next, insulating layer spacers 14 are formed on both lateral sides of the nitride layer patterns 12. Then, a thermal oxide layer 16 is formed on an exposed semiconductor substrate 10 by a thermal oxidation process.
Referring to FIG. 1B, the thermal oxide layer 16 and the insulating spacers 14 are removed by a wet etching process to form a groove 18. Next, ions 20 are implanted on the semiconductor substrate 10 adjacent to the groove 18 for controlling a threshold voltage. Next, a gate insulating layer 22 is deposited on the semiconductor substrate 10 having the groove 18 at a predetermined thickness, and a polysilicon layer 24 is deposited on the semiconductor substrate 10 having the gate insulating layer 22 to fully fill the groove 18 between the nitride layer patterns 12. The polysilicon layer 24 is planarized to form a gate electrode 24 by a chemical mechanical polishing (CMP) process until the nitride layer pattern 12 is exposed.
Referring to FIG. 1C, the nitride layer pattern 12 formed on both lateral sides of the gate electrode 24 is removed, and spacers 28 are formed on both lateral sides of the gate electrode 24. Conjunction regions 26 and 30 having a lightly doped drain (LDD) are formed beneath the spacers 28 and adjacent to the bottom of the spacers 28. As a result, a channel is formed under the gate electrode 24. The channel is formed to be elongated since the bottom surface of the gate electrode has a groove.
However, as design rule of the gate electrode 24 is about 0.1 μm, the distance between the nitride patterns 12 should be within the design rule. During the thermal oxidation process for forming the thermal oxide layer 16, the semiconductor substrate 10 is subject to severe stress because of the nitride layer pattern 12, even if the spacers 14 are formed. Further, when the thermal oxidation process is partially performed, a bird's beak can be easily formed, thereby making difficult the forming of a delicate groove. Thus, there still continues to be a need for an improved fabricating method for elongating an effective channel length and width to improve current characteristics of a semiconductor device.


Production of pharmaceutically bioactive peptides and proteins in large quantities has become feasible (Biomacromolecules 2004; 5:1917-1925). The oral route is considered the most convenient way of administering drugs for patients or an animal subject. Nevertheless, the intestinal epithelium is a major barrier to the absorption of hydrophilic drugs such as peptides and proteins (J. Control. Release 1996; 39:131-138). This is because hydrophilic drugs cannot easily diffuse across the cells through the lipid-bilayer cell membranes. Attentions have been given to improving paracellular transport of hydrophilic drugs (J. Control. Release 1998; 51:35-46). However, the transport of hydrophilic molecules via the paracellular pathway is, however, severely restricted by the presence of tight junctions that are located at the luminal aspect of adjacent epithelial cells (Annu. Rev. Nutr. 1995; 15:35-55). These tight junctions form a barrier that limits the paracellular diffusion of hydrophilic molecules. The structure and function of tight junctions is described, inter alia, in Ann. Rev. Physiol. 1998; 60:121-160 and in Ballard T S et al., Annu. Rev. Nutr. 1995; 15:35-55. Tight junctions do not form a rigid barrier but play an important role in the diffusion through the intestinal epithelium from lumen to bloodstream and vice versa.
Movement of solutes between cells, through the tight junctions that bind cells together into a layer such as the epithelial cells of the gastrointestinal tract, is termed paracellular transport. Paracellular transport is passive. Paracellular transport is dependent on electrochemical gradients generated by transcellular transport and solvent drag through tight junctions. Tight junctions form an intercellular barrier that separates the apical and basolateral fluid compartments of a cell layer. Movement of a solute through a tight junction from apical to basolateral compartments depends on the permeability of the tight junction for that solute.
Polymeric nanoparticles have been widely investigated as carriers for drug delivery (Biomaterials 2002; 23:3193-3201). Much attention has been given to the nanoparticles made of synthetic biodegradable polymers such as poly-ε-caprolactone and polylactide due to their biocompatibility (J. Drug Delivery 2000; 7:215-232; Eur. J. Pharm. Biopharm. 1995; 41:19-25). However, these nanoparticles are not ideal carriers for hydrophilic drugs because of their hydrophobic property. Some aspects of the invention relate to a novel nanoparticle system, composed of hydrophilic chitosan and poly(glutamic acid) hydrogels; the nanoparticles are prepared by a simple ionic-gelation method. This technique is promising as the nanoparticles are prepared under mild conditions without using harmful solvents. It is known that organic solvents may cause degradation of peptide or protein drugs that are unstable and sensitive to their environments (J. Control. Release 2001; 73:279-291).
Following the oral drug delivery route, protein drugs are readily degraded by the low pH of gastric medium in the stomach. The absorption of protein drugs following oral administration is challenging due to their high molecular weight, hydrophilicity, and susceptibility to enzymatic inactivation. Protein drugs at the intestinal epithelium cannot partition into the hydrophobic membrane, leaving only the epithelial barrier via the paracellular pathway. However, the tight junction forms a barrier that limits the paracellular diffusion of hydrophilic molecules.
Chitosan (CS), a cationic polysaccharide, is generally derived from chitin by alkaline deacetylation (J. Control. Release 2004; 96:285-300). It was reported from literature that CS is non-toxic and soft-tissue compatible (Biomacromolecules 2004; 5:1917-1925; Biomacromolecules 2004; 5:828-833). Additionally, it is known that CS has a special property of adhering to the mucosal surface and transiently opening the tight junctions between epithelial cells (Pharm. Res. 1994; 11:1358-1361). Most commercially available CSs have a quite large molecular weight (MW) and need to be dissolved in an acetic acid solution at a pH value of approximately 4.0 or lower, which is somewhat impractical. However, there are potential applications of CS in which a low MW would be essential. Given a low MW, the polycationic characteristic of CS can be used together with a good solubility at a pH value close to physiological ranges (Eur. J. Pharm. Biopharm. 2004; 57:101-105). Loading of peptide or protein drugs at physiological pH ranges would preserve their bioactivity. On this basis, a low-MW CS, obtained by depolymerizing a commercially available CS using cellulase, is disclosed herein to prepare nanoparticles of the present invention.
Thanou et al. reported chitosan and its derivatives as intestinal absorption enhancers (Adv Drug Deliv Rev 2001; 50:S91-S101). Chitosan, when protonated at an acidic pH, is able to increase the paracellular permeability of peptide drugs across mucosal epithelia. Co-administration of chitosan or trimethyl chitosan chloride with peptide drugs were found to substantially increase the bioavailability of the peptide in animals compared with administrations without the chitosan component.
The γ-PGA, an anionic peptide, is a natural compound produced as capsular substance or as slime by members of the genus Bacillus (Crit. Rev. Biotechnol. 2001; 21:219-232). γ-PGA is unique in that it is composed of naturally occurring L-glutamic acid linked together through amide bonds. It is reported from literature that this naturally occurring γ-PGA is a water-soluble, biodegradable, and non-toxic polymer. A polyamino carboxylic acid (complexone), such as diethylene triamine pentaacetic acid, has showed enzyme resistant property. It is clinical beneficial to incorporate a PGA-complexone conjugate as a negative substrate and chitosan as a positive substrate in a drug delivery nanoparticle formulation for better absorption performance with reduced enzymatic effect.


FIG. 1 shows a prior art six transistor static read/write memory cell 710 such as is typically used in high-density static random access memories (SRAMs). A static memory cell is characterized by operation in one of two mutually-exclusive and self-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a "high" voltage to indicate a "set" operating state. The memory cell output produces a "low" voltage to indicate a "reset" operating state. A low or reset output voltage usually represents a binary value of zero, while a high or set output voltage represents a binary value of one.
Static memory cell 710 generally comprises first and second inverters 712 and 714 which are cross-coupled to form a bistable flip-flop. Inverters 712 and 714 are formed by n-channel driver transistors 716 and 717, and p-channel load transistors 718 and 719. Driver transistors 716 and 717 are typically n-channel metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate. P-channel transistors 718 and 719 are typically thin film transistors formed above the driver transistors.
The source regions of driver transistors 716 and 717 are tied to a low reference or circuit supply voltage, labelled V.sub.ss and typically referred to as "ground." Load transistors 718 and 719 are connected in series between a high reference or circuit supply voltage, labelled V.sub.cc, and the drains of the corresponding driver transistors 716 and 717. The gates of load transistors 718 and 719 are connected to the gates of the corresponding driver transistors 716 and 717.
Inverter 712 has an inverter output 720 formed by the drain of driver transistor 716. Similarly, inverter 714 has an inverter output 722 formed by the drain of driver transistor 717. Inverter 712 has an inverter input 724 formed by the gate of driver transistor 716. Inverter 714 has an inverter input 726 formed by the gate of driver transistor 717.
The inputs and outputs of inverters 712 and 714 are cross-coupled to form a flip-flop having a pair of complementary two-state outputs. Specifically, inverter output 720 is cross-coupled to inverter input 726, and inverter output 722 is cross-coupled to inverter input 724. In this configuration, inverter outputs 720 and 722 form the complementary two-state outputs of the flip-flop.
A memory flip-flop such as that described typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 730 and 732, are used to selectively address and access individual memory elements within the array. Access transistor 730 has one active terminal connected to cross-coupled inverter output 720. Access transistor 732 has one active terminal connected to cross-coupled inverter output 722. A plurality of complementary column line pairs, such as the single pair of complementary column lines 734 and 736 shown, are connected to the remaining active terminals of access transistors 730 and 732, respectively. A row line 738 is connected to the gates of access transistors 730 and 732.
Reading static memory cell 710 involves activating row line 738 to connect inverter outputs 720 and 722 to column lines 734 and 736. Writing to static memory cell 710 involves first placing selected complementary logic voltages on column lines 734 and 736, and then activating row line 738 to connect those logic voltages to inverter outputs 720 and 722. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
FIG. 2 shows an alternative four transistor, dual wordline, prior art static read/write memory cell 750 such as is typically used in high density static random access memories. Static memory cell 750 comprises n-channel pull-down (driver) transistors 780 and 782 having drains respectively connected to pull-up load elements or resistors 784 and 786. Transistors 780 and 782 are typically metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate.
The source regions of transistors 780 and 782 are tied to a low reference or circuit supply voltage, labelled V.sub.ss and typically referred to as "ground." Resistors 784 and 786 are respectively connected in series between a high reference or circuit supply voltage, labelled V.sub.cc, and the drains of the corresponding transistors 780 and 782. The drain of transistor 782 is connected to the gate of transistor 780 by line 776, and the drain of transistor 780 is connected to the gate of transistor 782 by line 774 to form a flip-flop having a pair of complementary two-state outputs.
A memory flip-flop, such as that described above in connection with FIG. 2, typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 790 and 792, are used to selectively address and access individual memory elements within the array. Access transistor 790 has one active terminal connected to the drain of transistor 780. Access transistor 792 has one active terminal connected to the drain of transistor 782. A plurality of complementary column line pairs, such as the single pair of complementary column lines 752 and 754 shown, are connected to the remaining active terminals of access transistors 790 and 792, respectively. A row line 756 is connected to the gates of access transistors 790 and 792.
Reading static memory cell 750 involves activating row line 756 to connect outputs 768 and 772 to column lines 752 and 754. Writing to static memory cell 750 involves first placing selected complementary logic voltages on column lines 752 and 754, and then activating row line 756 to connect those logic voltages to outputs 768 and 772. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
A static memory cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The two possible output voltages produced by a static memory cell correspond generally to upper and lower circuit supply voltages. Intermediate output voltages, between the upper and lower circuit supply voltages, generally do not occur except for during brief periods of memory cell power-up and during transitions from one operating state to the other operating state.
The operation of a static memory cell is in contrast to other types of memory cells such as dynamic cells which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than very short time periods.
A dynamic memory cell has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the four or more transistors typically required in a static memory cell. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along generally different paths than has the design of dynamic memories.
FIG. 3 illustrates a typical top view of a prior art layout of portions of the FIG. 2 SRAM schematic pertinent to this disclosure. Such an SRAM cell employs two Vcc lines which are labeled respectively as Vcc(A) and Vcc(B). Lines 790a and 792a constitute the gate or wordlines of access devices 790 and 792, respectively. The two shaded areas 784 and 786 comprise the described pull-up resistors which are substantially horizontally formed as shown within the SRAM cell. Such horizontal positioning consumes considerable area within an individual SRAM cell, thus countering a desired goal of maximizing circuit density. Other examples of such similarly situated resistors can be found in U.S. Pat. No. 4,178,674 to Liu et al. and U.S. Pat. No. 4,828,629 to Akeda et al. Vertically oriented pull-up resistor constructions in SRAM cells have been proposed, such as is disclosed in our U.S. Pat. No. 5,177,030.
This invention concerns improved SRAM construction employing vertically elongated pull-up resistors in SRAMs.


A DRAM is a commonly used semiconductor device comprising a capacitor and a transistor. A continuous challenge in the semiconductor industry is to decrease the vertical and/or horizontal size of semiconductor devices, such as DRAMs and capacitors. A limitation on the minimal horizontal footprint of capacitor constructions is impacted by the resolution of a photolithographic etch during fabrication of the capacitor constructions. Although this resolution is generally improving, at any given time there is a minimum photolithographic feature dimension of which a fabrication process is capable. It would be desirable to form capacitors at least some portions of which have a cross-sectional minimum dimension of less than the minimum capable photolithographic feature dimension of a given fabrication process.
A problem in the semiconductor industry is mask misalignment. Mask misalignment during device fabrication can lead to inoperative devices. Accordingly, it is desirable to design device-fabrication processes which can compensate for mask misalignment.


In the broadband communication system such as a TV tuner, a highly linear variable-gain low noise amplifier is arranged in upstream of a mixer. Generally, the highly linear variable-gain low noise amplifier is implemented according to a current steering topology.
FIG. 1A is a schematic circuit diagram illustrating a conventional highly linear variable-gain amplifier. This highly linear variable-gain amplifier is disclosed in IEEE J. Solid-State Circuits, vol. 26, pp. 1673-1680, November 1991. As shown in FIG. 1A, a first transistor Q1 and a second transistor Q2 are connected with each other to define a differential pair. The bases of the first transistor Q1 and the second transistor Q2 serve as the differential signal input terminals of the amplifier to receive an input signal vi. The first terminals of two emitter resistors Re are respectively connected to the emitters of the first transistor Q1 and the second transistor Q2. The second terminals of the two emitter resistors Re are collectively connected to a node “a”. A current source (Is) is interconnected between the node “a” and a ground terminal Gnd.
The bases of a third transistor Q3 and a fourth transistor Q4 serve as the gain control terminals of the amplifier for receiving a current steering control signal Vctrl. The collector of the third transistor Q3 is connected to a voltage source Vcc. The emitter of the third transistor Q3 is connected to the collector of the first transistor Q1. A first collector resistor Rc1 is interconnected between the voltage source Vcc and the collector of the fourth transistor Q4. The emitter of the fourth transistor Q4 is connected to the collector of the first transistor Q1. The base of a fifth transistor Q5 is connected to the base of the fourth transistor Q4. The base of a sixth transistor Q6 is connected to the base of the third transistor Q3. The collector of the sixth transistor Q6 is connected to the voltage source Vcc. The emitter of the sixth transistor Q6 is connected to the collector of the second transistor Q2. A second collector resistor Rc2 is interconnected between the collector of the fifth transistor Q5 and the voltage source Vcc. The emitter of the fifth transistor Q5 is connected to the collector of the second transistor Q2. The collectors of the fourth transistor Q4 and the fifth transistor Q5 serve as differential signal output terminals of the amplifier for generating an output signal vo.
The current source (Is) may provide DC bias voltages to all transistors of the amplifier. The two emitter resistors Re may offer good linearity of the amplifier. In addition, the resistance of the first collector resistor Rc1 is identical to that of the second collector resistor Rc2.
In response to a change of the current steering control signal Vctrl, the bias currents flowing through the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5 and the sixth transistor Q6 are varied, and thus the gain value of the amplifier are adjustable. Moreover, the above amplifier may acquire a high gain control range.
Generally, the noise figure (NF) of the highly linear variable-gain amplifier is varied with the gain value. FIGS. 1B and 1C are schematic diagrams illustrating the relationship between the gain and the noise figure (NF) of the conventional highly linear variable-gain amplifier. As can be seen from FIGS. 1B and 1C, as the gain value of the amplifier is increased, the noise figure is decreased. Whereas, as the gain value of the amplifier is decreased, the noise figure is increased. That, when the gain value of the amplifier is adjusted according to the current steering control signal Vctrl, the noise figure is increased at nearly the same rate as the gain value is decreased.
In a case that the magnitude of the input signal vi is very low, the gain value of the amplifier is usually adjusted to the maximum value, and thus the noise figure is not too large. In a case that the magnitude of the input signal vi is relatively larger, the gain value needs to be reduced. In this situation, the noise figure of the amplifier is increased, and the signal is also amplified. In other words, the magnitude of the output signal vo allows for providing a sufficient signal-to-noise ratio (SNR). However, in the broadband communication application, the interference and noise are sometimes greater than the useful signal. For preventing the electronic components of the amplifier from entering the saturation region, the gain value of the amplifier needs to be decreased. If the increase of the noise figure is too obvious, however, the magnitude of the output signal vo fails to provide a sufficient signal-to-noise ratio (SNR), and thus the baseband circuit fails to effectively restore the signal. That is, when the amplifier has a low gain, low noise figure (NF) is very critical.
FIG. 2 is a schematic circuit diagram illustrating another conventional highly linear variable-gain low noise amplifier. The highly linear variable-gain low noise amplifier is disclosed in for example U.S. Pat. No. 6,100,761. As shown in FIG. 2, a first transistor 1Q1 and a second transistor 1Q2 are connected with each other to define a differential pair. The base of the first transistor 1Q1 is connected with a base voltage Vb through a first base resistor 1Rb1. The base of the second transistor 1Q2 is connected with the base voltage Vb through a second base resistor 1Rb2. The bases of the first transistor Q1 and the second transistor Q2 serve as the differential signal input terminals (IN+ and IN−) of the amplifier.
The first terminals of two variable emitter resistors (1Re) 40 are respectively connected to the emitters of the first transistor 1Q1 and the second transistor 1Q2. The second terminals of two variable collector resistors (1Rc) 30 are respectively connected to a collector voltage Vc. Moreover, the collectors of the first transistor Q1 and the second transistor Q2 serve as the differential signal output terminals (− OUT +) of the amplifier.
In the amplifier of FIG. 2, the gain value of the amplifier is adjusted by changing the resistances of the variable emitter resistors (1Re) 40 and the variable collector resistors (1Rc) 30. The changes of the variable emitter resistors (1Re) 40, however, may deteriorate the linearity of the amplifier.


1. Field
Embodiments of the disclosure relate generally to the field of aircraft flight instrumentation and more particularly to a system for notifying pilots of an off ground flight condition resulting from a landing bounce which incorporates landing gear extension/compression measurement and pilot indicators.
2. Background
Aircraft operating in high winds or other adverse environmental conditions during landing or landing with improperly serviced landing gear shock struts may encounter the runway surface with sufficient force to induce a bounce (rebound off the runway) causing the aircraft to again become airborne. Premature rapid de-rotation (pitching the nose down) without the main landing gear firmly planted on the runway has been cited as one of the contributing elements for aircraft undesired landing incidents. Due to the size and cockpit positioning in large commercial aircraft, if an airplane bounces off the runway after touchdown, the flight crew may not recognize that the airplane has bounced due to the difference between the cockpit movement and the airplane main landing gear position relative to the ground; i.e. the cockpit may be moving up or down while the main gear are coming off the ground. If the airplane derotation is performed while the main gear are off the ground, it could lead to a nose landing gear only landing that could cause significant structural damage to the airplane.
It is therefore desirable to provide an Airplane Off Ground Advisory System (AOGAS) which will provide an indication to the flight crew positively identifying the aircraft has bounced after initial contact with the runway so that the crew can take appropriate action to make a safe landing or perform a go-around operation.


MIMO (multi-input multi-output) technology corresponds to a technology for increasing data transmission and reception efficiency using a plurality of transmission antennas and a plurality of reception antennas instead of using a single transmission antenna and a single reception antenna. If a single antenna is used, a receiving end receives data through a single antenna path. On the contrary, if multiple antennas are used, the receiving end receives data through several paths, thereby enhancing transmission speed and transmission capacity and increasing coverage.
A single-cell MIMO operation can be divided into a single user-MIMO (SU-MIMO) scheme that a single user equipment (UE) receives a downlink signal in a single cell and a multi user-MIMO (MU-MIMO) scheme that two or more UEs receive a downlink signal in a single cell.
Channel estimation corresponds to a procedure of restoring a received signal by compensating a distortion of the signal distorted by fading. In this case, the fading corresponds to a phenomenon of rapidly changing strength of a signal due to multi-path time delay in wireless communication system environment. In order to perform the channel estimation, it is necessary to have a reference signal known to both a transmitter and a receiver. The reference signal can be simply referred to as an RS (reference signal) or a pilot depending on a standard applied thereto.
A downlink reference signal corresponds to a pilot signal for coherently demodulating PDSCH (physical downlink shared channel). PCFICH (physical control format indicator channel), PHICH (physical hybrid indicator channel). PDCCH (physical downlink control channel) and the like. A downlink reference signal can be classified into a common reference signal (CRS) shared by all UEs within a cell and a dedicated reference signal (DRS) used for a specific UE only. Compared to a legacy communication system supporting 4 transmission antennas (e.g., a system according to LTE release 8 or 9 standard), a system including an extended antenna configuration (e.g., a system according to LTE-A standard supporting 8 transmission antennas) is considering DRS-based data demodulation to efficiently manage a reference signal and support an enhanced transmission scheme. In particular, in order to support data transmission through an extended antenna, it may be able to define a DRS for two or more layers. Since a DRS and data are precoded by a same precoder, it is able to easily estimate channel information, which is used for a receiving end to demodulate data, without separate precoding information.
Although a downlink receiving end is able to obtain precoded channel information on an extended antenna configuration through a DRS, it is required for the downlink receiving end to have a separate reference signal except the DRS to obtain channel information which is not precoded. Hence, it is able to define a reference signal for obtaining channel state information (CSI), i.e., a CSI-RS, at a receiving end in a system according to LTE-A standard.


1. Field of the Invention
This invention relates to frequency and award redemption program. More particularly, the present invention relates to an on-line, interactive frequency and award redemption program which is fully integrated.
2. Description of Related Art
Frequency programs have been developed by the travel industry to promote customer loyalty. An example of such a program is a “frequent flyer” program. According to such a program, when a traveler books a flight, a certain amount of “mileage points” are calculated by a formula using the distance of the destination as a parameter. However, the mileage points are not awarded until the traveler actually takes the flight.
When a traveler has accumulated sufficient number of mileage points, he may redeem these points for an award chosen from a specific list of awards specified by the program. Thus, for example, the traveler may redeem the points for a free flight ticket or a free rental car. In order to redeem the accumulated points, the traveler generally needs to request a certificate, and use the issued certificate as payment for the free travel.
While the above program may induce customer loyalty, it has the disadvantage that the selection of prizes can be made only from the limited list of awards provided by the company. For example, a traveler may redeem the certificate for flights between only those destinations to which the carrier has a regular service. Another disadvantage is that the customer generally needs to plan ahead in sufficient time to order and receive the award certificate.
According to another type of frequency and award program, a credit instrument is provided and credit points are accumulated instead of the mileage points. In such programs, bonus points are awarded by using a formula in which a price paid for merchandise is a parameter. Thus, upon each purchase a certain number of bonus points are awarded, which translate to dollar credit amount. According to these programs, the customer receives a credit instrument which may be acceptable by many enrolled retailers, so that the selection of prizes available is enhanced. An example of such a program is disclosed in E.P.A. 308,224. However, while such programs may enhance the selection of prizes, there is still the problem of obtaining the credit instrument for redeeming the awarded points. In addition, the enrollee must allow for processing time before the bonus points are recorded and made available as redeemable credit. Thus, the immediacy effect of the reward is lacking in these conventional incentive programs.


U.S. Pat. No. 5,306,305 (=WO 95/19152) discloses an in vitro method for producing an implant device by coating a gel containing osteoblast cells onto a porous metal surface and then incubating the gel in a growth medium. A repeatedly renewed minimal essential medium (MEM) is used for about 3 weeks for cell multiplication, followed by a medium containing .beta.-glycerophosphate and ascorbic acid for another 1-2 weeks. The cells may originate from the patient's own bone fragments. The gel (e.g. 0.5% gelatin) is used to hold the cells to the substrate surface.
DE-A-3810803 discloses a method of producing living bone substitute materials by in vitro culturing autologous bone cells from human bone fragments in a repeatedly renewed culture medium, followed by deposition of the cultured cells in a porous calcium phosphate matrix and additional culturing. The composite material can be reimplanted.
WO 94/04657 discloses a bioactive porous glass which is pretreated in such a way that it cannot raise the pH of a tissue medium contacted with the glass. It also reports the seeding of the pretreated porous glass with osteoblasts.
These prior art methods of in vitro production of bone tissue for implanting purposes have not yet been put into practice, probably because fixation of the resulting implant in the body and thus functioning of the implant are insufficient due to limitations in the applying techniques. No biological effect of using a particular culture method was described in the prior art. Furthermore, these prior methods necessitate the introduction of a bone defect (a lesion) in the patient in order to obtain the required bone cells.


The present invention relates generally to an apparatus for the distribution and delivery of video in a digital system and, in particular, to a method and apparatus that rapidly changes the channel in such a system.
In a typical analog cable system all of the channels or services ordered by the subscriber are delivered to each subscriber""s home. In order to ensure that each subscriber receives only the channels for which he has paid, the cable television providers encrypt or xe2x80x9cscramblexe2x80x9d the premium channels (HBO, CINEMAX, DISNEY, etc.). The cable television providers also may scramble many of the xe2x80x9cbasicxe2x80x9d channels (local stations, ESPN, MTV, VH1, TNT, DISCOVERY, etc.). Therefore, even though virtually all television sets sold today are cable-ready, most subscribers still need a set-top unit (sometimes referred to as a cable box in the cable television environment) to descramble the signals. The set-top units are located proximate a television and are also used to change the channel that is viewed on the television.
Subscribers, especially residential subscribers, are demanding that large amounts of information and more choices of services be brought into their homes. Switched video for viewing on a subscriber""s television and high-speed Internet access are two services highly desired by subscribers. In order to meet the demand, and to accommodate the recently approved high-definition television standards, the new services will likely have to be capable of handling digital signals.
In addition to the emerging technologies, entry of the Regional Bell Operating Companies (RBOCs) have made digital delivery systems economically feasible. A typical digital video delivery system includes a means for receiving the video signals from various broadcast sources, a means for delivering the signals to a plurality of subscribers, and a means of transmitting the signals between the receiving means and delivering means. The means for receiving the video signals may include a broadband digital terminal (BDT) located in a central office. The delivering means may be a broadband network unit (BNU) located preferably on a telephone pole or other convenient location proximate a number of subscribers. Cable or optical fiber connects the BDT to the BNU. A second cable (or a twisted wire pair) connects the set-top units (and, if required, the various other units in the subscriber""s home) with the BNU.
In a typical digital video system, all of the video services offered by the video service company are again delivered to the set-top unit. When selecting a new channel, the set-top unit performs the actual switching and also descrambles the digital signals.
Even though the premium channels are scrambled, delivering all of the video signals into a subscriber""s home makes the video services susceptible to theft. Accordingly, more complexxe2x80x94and expensivexe2x80x94steps must be taken to further secure the transmission and delivery of the video services.
A solution to the theft problem is to perform the channel switching xe2x80x9cupstreamxe2x80x9d from the subscriber at a facility controlled by the video provider (in a digital system at the BDT, for, example), and only delivering one channel at a time to the subscriber""s set-top unit. Another advantage of moving the switching upstream is that the bandwidth requirements of the overall video delivery system are greatly reduced. However, a drawback of this system is that the subscriber experiences a time delay between the period of time it takes for the subscriber to select a channel and for the newly selected channel to be viewed on the television.
The reason for this time delay is that the subscriber""s request must first travel upstream to the BDT; next, the BDT must acknowledge the request, then synchronize and xe2x80x9clock onxe2x80x9d to the desired video service; finally, the BDT must transmit the desired video service back downstream to the subscriber. The overall delay between each channel change can take over a second.
A significant portion of the delay is caused by the time it takes for the video signal to synchronize. This portion accounts for about half of the overall delay (i.e., about a half second). Many subscribers find the delay in such video delivery systems annoying since they are accustomed to seeing the broadcast signal immediately after selecting a new channel. Most subscribers find that a one second delay is unacceptable, which would make such a system competitively unattractive.
The present invention relates to a method and apparatus for rapidly changing the channel in a digital video delivery system. The rapid channel changer will be preferably located in the central office with the broadband digital terminal (BDT) and indexes the xe2x80x9cstartxe2x80x9d or synchronization frame of each video channel received at the BDT.
Each digital video signal includes a synchronization frame. The subject channel changer captures the multiple compressed video signals and stores each signal in a cache buffer. A, processor is used to index or xe2x80x9cpoint toxe2x80x9d the respective synchronization frames for each buffered signal.
When a subscriber requests a specific channel or video service, the processor can immediately access the requested video signal at a synchronization frame and direct the video stream to the subscriber since the processor already has the position of the synchronization frame of each video signal. Accordingly, the period of time that the subscriber previously had to wait for the synchronization frame is eliminated.
These and other features and objects of the invention will be more fully understood from the following detailed description of the preferred embodiments which should be read in light of the accompanying drawings.


In wafer inspection systems which utilize two dimensional imaging, the inspection speed is determined, among other things, from parameters including field of view size, and time between imaging sequential images. Generally speaking, a larger field of view, or a shorter time between sequential images will increase the inspection speed.
Decreasing the time between imaging may be complicated and expensive. For instance, decreasing the time between images can require very fast detectors (much faster above normal 30 Hz detectors), fast illumination (for example, repetitive laser with hundreds of pulses per second), and a fast stage or other suitable components for generating relative motion between the wafer and imaging components to change which portion(s) of the wafer are in view for imaging.
A more preferable approach in some circumstances is to enlarge the field of view. However, when fine resolution is required (pixel size in the wafer plane is below 0.5 microns), the detector must contain a numerous pixels. For example, using 0.2 micron pixel, and a conventional commercial detector with 2K×2K pixels, the field of view is only 0.4 mm×0.4 mm. An enlarged field of view may also require a faster stage or other suitable components for providing relative motion between the imaging components and the wafer.
The image view can be increased by using multiple two dimensional detectors to obtain an image, with the image divided amongst the detectors. Some currently-existing systems split an image before the focal plane of the other optics used to obtain the image using, for instance, beam splitters and/or mirrors. See, for instance, U.S. patent application Ser. No. 10/345,097, filed Jan. 15, 2003, and published as U.S. Patent Application Publication No., 20040146295 which are each incorporated by reference in their entireties herein. However, splitting an image by a mirror or other element(s) before the focal plane may be problematic in some instances. The problems may include, for example, reductions in intensity and/or non-uniform intensity.
FIG. 9 illustrates an example wherein the intensity in some parts of a split image is reduced when some rays are reflected back from the mirror and do not actually reach the focal plane, since the actual splitting of the image occurs prior to the focal plane. As shown in FIG. 9, three rays (R1, R2 and R3) from the imaging optics 18 of an inspection system reach point A in the focal plane FP18 of the imaging optics if no splitting mirror is used (i.e., if the mirror shown in FIG. 9 is disregarded, all three rays reach point A). However, when the splitting mirror comprising reflective planes 902 and 904 is used, only two rays (R2 and R3) reach the detectors 908-1 and 908-2 in the split focal plane. The top ray (R1) is reflected back from the mirror.
FIG. 9 also illustrates an example of non uniform intensity that may result from splitting. The intensity reduction is position dependent—a given portion of the image that is closer to the splitting point will have a reduced intensity relative to a portion of the image far from the splitting point. In FIG. 9, point B′ gets only about half of the rays (i.e. rays generally emanating from the bottom half part of the imaging optics), while point A′, for example, gets more (about two thirds: from ray R2 to R3).
An example hypothetical intensity distribution in detector 908-1 and 908-2 imaging a uniform input image (I and II) is shown in FIG. 10. The image is darker at points closer to the splitting point, with denser cross-hatching representing progressively darker portions of the image (becoming darker from left to right in 908-2 and right to left in 908-1).
The angular distribution of the image is not preserved when an image is split in this manner. For a wafer inspection system, the angular distribution of the scattered or reflected light from the wafer contains information regarding the wafer characteristics. Using splitting mirrors before the focal plane changes the angular distribution since it blocks a range of ray angles and thus may result in reduced inspection accuracy.
When splitting by beam splitters, some of the rays (usually 50%) are reflected from the beam splitter while the rest of the rays are transmitted. This way does not break the uniformity or the angular distribution, but the intensity is reduced by 50%. When using more than one splitter to split an image into more than two portions, the intensity can be reduced even more.


1. Field of the Invention
The present invention relates to a display panel drive circuit and display panel and, more particularly, to a display panel drive circuit and display panel in which thin film transistors for the display panel drive circuit can be prevented from deteriorating.
2. Description of Related Art
In recent years, there have been proposals for LCD (liquid crystal display) panels utilizing low-temperature polysilicon TFTs (thin film transistors). Such display panels can be formed, on one common substrate, not only together with pixel transistors but also with peripheral drive circuits, such as scanning shift registers and sampling circuits. Accordingly, display can be by mere external connection with reduced number of signal lines, reducing the number of parts and improving reliability. Large display panels of an approximately 20-40 type are under considerations.
There are recently found cases where a large color liquid crystal panels is equipped on a camera-integrated video tape recorder (VTR) in order for use as monitors or finders. Of these camera-integrated VTRs, there are structures that a display panel is arranged to rotate about a horizontal axis to shift its position. In such a case, horizontal and vertical scanning directions has to be changed depending upon the panel direction so that display is properly viewed when the panel is rotated. Due to this, the scanning shift register includes a scanning direction control circuit using, for example, an analog switch circuit.
A display panel having a drive circuit for controlling the scanning direction, as mentioned above, was formed on one substrate, for conducting test. It was confirmed that deterioration is encountered in the TFTs of a signal input circuit to which scanning start pulses are externally applied, causing a problem that initial failure occurs resulting in impossibility of scanning.
The cause of such deterioration in the signal input circuit TFTs externally applied by scanning start pulses is to be presumed as follows. That is, the start pulse drive circuit is high in deriveability, and circuit board mounting is separated from the display panel with connections to the display panel through cables, flexible circuit boards or the like. During driving or upon switching the scanning direction, a high voltage occurs due to the effect of interconnection inductance, etc., resulting in deterioration or breakage of transistors. It is also to be presumed as one of reasons for the deterioration that the analog switch circuit, to which an external start pulse is first inputted, is not configured as a gate input circuit.
Also, where the panel is made larger, a problem of time delay occurs particularly for a pixel section. In such a case, there is a necessity of forming the interconnection (gate) with using a low-resistance material such as aluminum. In the above-stated display panel, however, a pixel section and its peripheral circuits are formed by a common process so that the interconnections for the peripheral circuit are formed also by the low-resistance material. Due to this, there has been a problem that the peripheral circuit elements are liable to undergo dielectric breakdown.
Further, where using a high insulation substrate such as a glass substrate, there occurs concentration of electric fields through the interconnections during a plasma process for the TFT manufacture, resulting in a problem that so-called plasma antenna effects occur, i.e., the elements connected to these interconnections undergo damage. This phenomenon is liable to occur, particularly, at end portions of an interconnection pattern, at discontinuous portions or at large electrode areas. This condition is met by a start pulse input terminal pattern.
It is an object of the present invention to solve the above-stated problems as encountered in the prior art, and to provide a display panel drive circuit and display panel which is simple in structure but is free from occurrence of initial failure leading to impossibility of scanning.
A display panel drive circuit according to the present invention is characterized in that: thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits.
In the present invention, only a circuit to which signals are externally applied or thin film transistors of the same circuit is formed by a structure to withstand high voltage, whereby they operate in a manner preventing against deterioration and hence occurrence of initial failure.


(Not Applicable)
(Not Applicable)
The present invention generally relates to an illumination head for printed circuit board verification and more particularly to an illumination head that may be disposed a prescribed distance above the printed circuit board in order to facilitate rework thereon.
In order to inspect printed circuit boards, it is desirable to illuminate the same with an illumination source. Typical illumination sources include rings of light and/or spotlights which direct light onto a top surface of the printed circuit board. In this regard, once the top surface of the printed circuit board is illuminated, the printed circuit board may be inspected through the use of a video camera and/or automated inspection technique.
It is desirable to illuminate the top surface of the printed circuit board such that shadows and/or glare which can impair inspection are eliminated. Therefore, in the prior art, the illumination head for an inspection station is disposed in close proximity to the top surface of the printed circuit board.
It is undesirable to have the illumination head disposed in close proximity to the top surface of the printed circuit board because reworking of a defective circuit board is difficult. Specifically, during inspection of the printed circuit board, the operator of the inspection station must determine where imperfections in the printed circuit board exist. Upon identifying such imperfections, the operator marks the imperfections and then removes the printed circuit board from the inspection station in order to rework the circuit board. Because the illumination head is positioned in close proximity to the top surface of the printed circuit board, the operator of the inspection station cannot effectuate repairs to the printed circuit board. Accordingly, the operator must mark and remove defective printed circuit boards in order to rework the same. Once the defect has been marked, rework on the printed circuit board is effectuated on another machine.
The present invention addresses the above-mentioned deficiencies in inspection stations by providing an illumination head for an inspection station that may be disposed 4 to 6 inches above the top surface of the printed circuit board and still generate a clear image of the inspected part. In this respect, reworking of the printed circuit board may be accomplished at the inspection station which includes the illumination head of the present invention. Accordingly, an operator using an inspection station having an illumination head of the present invention may find defects on the top surface of the printed circuit board and rework the same without removing the printed circuit board from the inspection station.
An illumination head for an inspection and rework station. The illumination head has an optical axis and is operative to illuminate a part. The illumination head comprises a backlight having an aperture formed therein which is coaxially aligned with the optical axis of the illumination head. Further, the illumination head comprises at least one lightline disposed adjacent to the backlight. The backlight is operative to direct light onto the part along the optical axis and the lightline is operative to direct light onto the part at an angle incident to the optical axis. Accordingly, the illumination head may be disposed a prescribed distance above the part (i.e., typically four to six inches).
In accordance with the present invention, the aperture of the backlight may be circularly configured and the illumination head may further comprise an annular ringlight disposed between the backlight and the lightline. The ringlight is coaxially aligned with the aperture and operative to direct light onto the part along the optical axis. The lightline typically comprises two lightlines disposed on opposite sides of the illumination head. The illumination head may further comprise an iris coaxially aligned with the optical axis and configured to selectively regulate the level of illumination directed onto the part.
The illumination head constructed in accordance with the present invention may further include a viewing device coaxially aligned with the optical axis and operative to generate an image of the part through the aperture of the backlight. The viewing device may be a CCD camera.
In the preferred embodiment, the backlight is a translucent sheet configured to transmit light. The backlight is in optical communication through at least one optical fiber with a light source operative to illuminate the backlight. Similarly, the lightline may comprise a plurality of optical fibers disposed in substantially parallel relation to one another and operative to direct light upon the part at an angle incident to the optical axis.
In accordance with the present invention, there is provided a method of illuminating a part with an illumination head having an optical axis, a lightline, and a backlight. The method comprises illuminating the part with light directed at an angle incident to the optical axis with the lightline and illuminating the part with light directed along the optical axis with the backlight such that the illumination head is disposed a prescribed distance above the part. The method further may include coaxially aligning the aperture with the optical axis prior to illuminating the part.
In accordance with the present invention, the illumination head may further comprise an annular ringlight coaxially aligned with the aperture such that the method further comprises illuminating the part with light directed along the optical axis with the ring light. Additionally, the illumination head may further comprise an iris coaxially aligned with the aperture such that the method comprises controlling an amount of illumination from the backlight and the ringlight with the iris.


The present disclosure generally relates to enabling devices within an industrial automation system to become aware of certain attributes pertaining to the industrial automation system or a part of the industrial automation system, in which the devices are located. More specifically, the present disclosure relates to systems and methods for industrial automation devices to analyze its received data with respect to various parts of the industrial automation system or the industrial automation system as a whole.


The present invention relates to turbomachinery and vanes for guiding air flow through a turbomachine. More particularly, this invention relates to a fan outlet guide vane frame comprising sectors of outlet guide vanes formed of different materials, in which some of the sectors are load-bearing and others are not.
High-bypass turbofan engines are widely used for high performance aircraft that operate at subsonic speeds. As schematically represented in FIG. 1, a high-bypass turbofan engine 10 includes a large fan 12 placed at the front of the engine 10 to produce greater thrust and reduce specific fuel consumption. The fan 12 serves to compress incoming air 14, a portion of which flows into a core engine (gas turbine) 16 that includes a compressor section 18 containing low and high pressure compressor stages 18A and 18B to further compress the air, a combustion chamber 20 where fuel is mixed with the compressed air and combusted, and a turbine section 22 where a high pressure turbine 22A extracts energy from the combustion gases to drive the high pressure stages 18A of the compressor section 18 and a low pressure turbine 22B extracts energy from the combustion gases to drive the fan 12 and the low pressure stages 18B of the compressor section 18. A larger portion of the air that enters the fan 12 is bypassed to the rear of the engine 10 to generate additional engine thrust. The bypassed air passes through an annular-shaped bypass duct 24 that contains one or more rows of stator vanes, also called outlet guide vanes 28 (OGVs), located immediately aft of the fan 12 and its fan blades 26. The fan blades 26 are circumscribed by a fan casing 32, which in turn is surrounded by the fan cowling or nacelle 34 that defines the inlet duct 36 to the turbofan engine 10 as well as a fan nozzle 38 for the bypassed air exiting the bypass duct 24.
The outlet guide vanes 28 form part of a vane frame 40 that further includes inner and outer shrouds 42 and 44 at the radially inward and outward extents, respectively, of the guide vanes 28. A common construction is to form the vane frame 40 of segments, each comprising one or more vanes 28 connecting a pair of inner and outer shroud segments. The outer shroud 44 (formed by the assembly of the outer shroud segments) is secured to the fan casing 32, while the inner shroud 42 (formed by the assembly of the inner shroud segments) is secured to the core engine 16, and more particularly to an inner frame (not shown) of the core engine 16. The fan nacelle 34 is shown in FIG. 1 as attached to and supported by the core engine 16 through the outlet guide vanes 28. The guide vanes 28 have cambered airfoil shapes to modify the air flow through the bypass duct 24 to promote deswirling of the fan air, thus improving efficiency and reducing engine noise.
Because of its dual functions, the vane frame 40 is an important structural component whose design considerations include aerodynamic criteria as well as the ability to provide sufficient structural support and stiffness to the fan nacelle 34 for maintaining the shape of the inlet duct 36 and adequately transitioning static and dynamic loads to the engine core 16. For these reasons, it is important to select appropriate constructions, materials and assembly methods when manufacturing the vane frame 40 and its individual components, including the guide vanes 28 and inner and outer shrouds 42 and 44 and their connections to the fan casing 32 and core engine 16. Various materials and configurations for outlet guide vanes have been considered. Metallic materials, and particularly aluminum alloys, have been widely used. Composite materials have also been considered, as they offer the advantage of significant weight reduction. However, in order to be reliably capable of supporting the fan nacelle and transitioning fan nacelle loads, outlet guide vanes formed of composite materials have generally required complex attachment geometries and hardware, which increases weight and manufacturing and material costs.


In axial piston machines, at least one working piston is mounted in a longitudinally displaceable manner in a cylinder bore of a piston drum and forms a cylinder space with the cylinder bore. The cylinder space is alternately compressed and decompressed by the longitudinal movement of the working piston and, accordingly, alternately connected to a high-pressure reservoir and a low-pressure reservoir. When changing from the low-pressure reservoir connection to the high-pressure reservoir connection, pulsations occur which can result in substantial noise generation. To counteract this, so-called pre-compression volumes are used, which are formed by pre-compression spaces.
Axial piston machines having pre-compression spaces or zones are known from, the prior art, for example from DE 197 06 114 C5. In this, a pre-compression volume or a reservoir element is integrated in a control plate or in a connection plate of the axial piston machine. The pre-compression volumes known from the prior art can additionally be controlled via valve devices.
The known pre-compression spaces are sealed or closed outside the housing of the axial piston machine, which requires additional installation space. With regard to automobile applications, the installation space is an increasingly important issue for axial piston machines.
The seal of the pre-compression spaces moreover poses a technical challenge owing to the pulsation.
The object of the disclosure is to reduce the installation space for creating pre-compression spaces.


1. Field of the Invention
The present invention relates to a recording apparatus which includes a process of forming electrostatic latent images on a changed recording medium by means of irradiation of laser beams, and more particularly, to a recording apparatus which is capable of recording multi-colored information on the recording medium with a plurality of laser beams.
2. Description of the Prior Art
A recording apparatus of the above kind includes, as shown, for instance, in FIG. 73, a drum-shaped photosensitive body 100 as the recording medium. In the periphery of the photosensitive body 100 there are arranged successively along the direction of rotation shown by the arrow, a first charger 101, a first exposure unit 102, a first developing unit 103, a second charger 104, a second exposure unit 105, a second developing unit 106, a transfer-stripping charger 107, a cleaner 110, and a discharger 109. One cycle of process is completed by electrically charging the photosensitive body 100 uniformly with the first charger 101, forming a second electrostatic latent image by the second exposure section 105, visualizing a second color by the second developing unit 106, carrying out a control processing if needed to equalize the amount of charges by the two color toners, though not shown, transferring dichromatic information onto a transfer material 108 with the transfer-stripping charger 107, cleaning with the cleaner 110 the toner that remains on the photos ensitive body 100 after transfer, and erasing the latent images with the discharger 109.
However, the existing apparatus has the second developing unit 106 which is of contact development type so that even when there is formed a first toner image 103a which is brought out to be visible, for example, by the first developing unit 103 as shown in FIG. 74(A), there may occur a case in which a portion of the first toner image 103a is scraped off by the second developing unit 106 as shown in FIG. 74(B). Then, in response to the exposure condition of the second exposure section 105, second toner 106a may be piled up by the second developing unit 106 over the first toner image 103a as shown in FIG. 74(C).
On the other hand, when the first toner 103a that was scraped off by the second developing unit 106 is sent into the inside of the second developing unit 106 to be mixed with the second toner 106a as shown in FIG. 75, the life of the developer (consisting of a carrier and a toner) will undergo a sharp reduction.
Further, in the case of the dichromatic printing process in which both of the first developing unit 103 and the second developing unit 106 are operated in the normal development mode, the changes in the surface potential of the photosensitive body 100, the conditions of the toner on the photosensitive body 100, and so forth will change as illustrated in FIG. 76(A).
Namely, due to charging by the first charger 001, the surface potential of the photosensitive body 100 is raised, and when the normal exposure is given using the first exposure section 102, only the information zone which is irradiated by the laser beam is maintained at a high potential to form an electrostatic latent image, leaving the outside of the information zone at a low potential. The electrostatic latent image is brought out to be visible using a negatively charged toner by the first developing unit 103. When the photosensitive body 100 is charged again in this state by the second charger 104, the surface potential of the photosensitive body 100 returns to nearly the level of the first charged state and the surface toner on the electrostatic latent image is transformed to a state in which it is charged positively by the appended charges.
Next, when the photosensitive body 100 is exposed normally by the second exposure section 105, there is formed an electrostatic latent image with high potential in the information zone, and at the same time there remains the image that was visualized in the past by the first developing unit 103. Further, an electrostatic latent image is brought out visible by the second developing unit 106 in a second exposure using negatively charged toner. A small amount of the toner is attached also to the electrostatic latent image due to the first exposure
The electrostatic latent image that is brought out to be visible in this manner by the two normal development modes is transferred onto the transfer material 108.
In addition, in the case of the dischromatic printing process in which the first developing unit 103 is operated in the inverted development mode and the second developing unit 106 is operated in the normal development mode, the surface potential of the photosensitive body 100 due to charging by the first charger 101 is raised, and an inverted exposure is carried out by the first exposure section 102 as shown in FIG. 76(B), bringing the information zone alone in low potential to form an electrostatic latent image, with the area outside of the information zone maintained at high potential. The electrostatic latent image is brought out to be visible by the first developing unit 103 due to positively charged toner. When the photosensitive body 100 is charged in this state again by the second developing unit 104, the surface potential of the photosensitive body 100 returns to approximately the level of the first charging.
Next, when the photosensitive body 100 is exposed normally by means of the second exposing section 105, the information zone becomes an electrostatic latent image with high potential, and the image that was brought out visible by first developing unit 103 remains as is. Then, the electrostatic latent image due to the second exposure is brought out visible by the second developing unit 106 with negatively charged toner, and a small amount of the toner is attached also to the electrostatic latent image due to the first exposure After carrying out a pre-transfer charging with a charger which is not shown in order to give the same polarity to the electrostatic latent images that are brought out visible in this manner by the inverted development mode and the normal development mode, each of the electrostatic latent images that are brought out to be visible is transferred onto the transfer material 108.
In the case of the conventional dichromatic printing process by the combination of the normal-normal development modes or the dichromatic printing process by the combination of the inverted-normal development modes, there is necessarily involved a process of charging a toner with the charge that has the polarity that is opposite to the polarity of the toner.
In particular, in the dichromatic printing process by the combination of the inverted-normal development modes, the polarity of the toner used varies for each development mode so that there is an inconvenience in that in order to transfer simultaneously both electrostatic latent images that are brought out to be visible onto the transfer material 108, there has to be given a pre-transfer charging to invert the polarity of one of the toners. Moreover, when the dichromatic printing process is employed in which development is carried out in the inverted mode after development in the normal mode, there also arises the necessity of carrying out a pre-transfer charging.
Furthermore, in the dichromatic printing process of the combination of the normal-normal development modes, the toner
is the same in each of the developing units. However, it is inevitable to have the opposite charge on the toner, at the time of recharging with the second charger 104, as shown in FIG. 76(A).
When the opposite charge appears on the toner, although each image is transferred later with corona of respective polarity, it is clear that the efficiency for each is lower than that for the ordinary monochromatic transfer.
However, when a high resistance is given to the toner in order to enhance the transfer efficiency and to secure a stable development in a humid atmosphere, there arises a problem that the toner which sits on the photosensitive body inverts the polarity so that it is difficult to invert the polarity even with the reversed charging.
In addition, when the thickness of the toner layer on the photosensitive body is large, the toner layer is laminated in multiple layers rather than in a single layer. In such a case, when the top layer in particular is inverted, it prevents the transfer of the opposite charge to the inner toner layers, so that there is a problem that the toner polarity in the lower layers is difficult.
Moreover, the existing color copier in practice is of the type in which an image is transferred onto a transfer paper or an intermediate transfer drum for each color, and this process is repeated, to complete the full color print, so that this method can also be applied to the recording apparatus of the type under consideration.
However, in that case, the copying speed will have to be reduced sharply since a sheet of copy is obtained by repeating the process similar to the above.
Furthermore, in the existing recording apparatus of the above kind, when printing is done in only one color, if, for instance, while the apparatus is in printing operation in a first color, a second color is designated, then the printing operation in the second color will be initiated by temporarily interrupting the rotational driving of the photosensitive body simultaneous with the completion of printing operation in the first color. Therefore, the copying speed will have to be reduced in some cases.


Electrode catheters have been in common use in medical practice for many years. They are used to stimulate and map electrical activity in the heart and to ablate sites of aberrant electrical activity. In use, the electrode catheter is inserted into a major vein or artery, e.g., femoral artery, and then guided into the chamber of the heart which is of concern. Within the heart, the ability to control the exact position and orientation of the catheter tip is critical and largely determines how useful the catheter is.
Bidirectional catheters have been designed to be deflectable in one direction by one puller wire and in the opposite direction within the same plane by a second puller wire. In such a construction, the puller wires extend into opposing off-axis lumens within the tip section of the catheter. So that the tip section can bend in both directions in the same plane, the puller wires and their associated lumens are located along a diameter of the tip section. For ablation catheters, electrode lead wires are also provided within the distal end and typically, an additional lumen is used to contain the electrode lead wires. For example, U.S. Pat. No. 6,210,407, is directed to a bi-directional catheter comprising two puller wires and a control handle having at least two movable members longitudinally movable between first and second positions. As another example, U.S. Pat. No. 6,171,277 is directed to a bidirectional steerable catheter having a control handle that houses a generally-circular spur gear and a pair of spaced apart rack gears. Each rack gear is longitudinally movable between first and second positions, whereby proximal movement of one rack gear results in rotational movement of the spur gear, and correspondingly distal movement of the other rack gear. Also known is U.S. Pat. No. 6,198,974 which is directed to a bi-directional electrode catheter comprising a control handle. At their proximal ends, two pairs of puller wires are attached to movable pistons in the control handle. Each piston is controlled by an operator using a slidable button fixedly attached to each piston. Movement of selected buttons results in deflection of the tip section into a generally planar “U”- or “S”-shaped curve. Further known is U.S. Pat. No. 5,891,088 directed to a steering assembly with asymmetric left and right curve configurations. Proximal ends of left and right steering wires are adjustably attached to a rotatable cam housed in a control handle. The rotatable cam has first and second cam surfaces which may be configured differently from each other to accomplish asymmetric steering.
Also known are control handles that provide a greater degree of deflection in the catheter tip. For example, U.S. Pat. No. 7,377,906, the entire disclosure of which is hereby incorporated by reference, has increased throw capacity through the use of pulleys around which puller wire travel for minimized offset angle between the puller wire and the longitudinal axis of the control handle while maximizing the travel distance of that puller wire for any given distance traveled by the pulley drawing the puller wire. Suitable tensile puller members are described in U.S. Patent Publication No. 2008/0103520, the entire disclosure of which is also hereby incorporated by reference.
However, it is desirable to provide a control handle that allows user adjustability of the maximum degree of deflection as well as deflection sensitivity of the control handle to user manipulations, as needed for different uses and applications.