The endothelial cell participates in numerous functions of vascular physiology. Many factors, such as cytokines, can alter the surface of the endothelial cell and thereby modulate the role of the endothelium in coagulation, inflammation, vaso-regulation, and adhesion. See, for example, R. P. Hebbel et al., J. Lab. Clin. Med., 129, 288 (1997); J. S. Pober, Am. J. Path., 133, 426 (1988); E. J. Favaloro, Inmmunol. Cell. Biol., 71, 571 (1993). The endothelial cell may also have a key role in the vascular pathology of sickle cell anemia, including the vaso-occlusions that cause acute painful crises. However, research in this area has been hindered by the inaccessibility of vascular endothelium in patients. For example, E. M. Levine et al. (U.S. Pat. No. 5,132,223) disclosed cloning and serial cultivation of adult human endothelial cells derived from brain-dead, but heart-beating cadaver organs. K. Gupta et al., Exp. Cell. Res., 230, 244 (1997) reported the culture of microvascular endothelial cells derived from newborn human foreskin. Thus, circulating endothelial cells might provide useful material for the study of vascular pathologies, for gene therapy, and for biomedical engineering applications. In previous investigations increased numbers of circulating endothelial cells have been found in sickle cell anemia and other conditions associated with vascular injury, such as that due to cytomegalovirus infection, rickettsial infection, myocardial infarction, intravascular instrumentation, and endotoxinemia. See, for example, F. George et al., Blood, 80, Suppl: 12a, abstract (1992); E. Percivalle et al., J. Clin. Invest., 92, 663 (1993), F. George et al., Blood, 82, 2109 (1993); C. A. Bouvier et al., Thomb. Diath. Haemorrh. Suppl., 40, 163 (1970); F. George et al., J. Immunol. Meth., 139, 65 (1991) and R. G. Gerrity et al., Exp. Mol. Pathol., 24, 59 (1976).
However, in normal donors, there are only about 2-3 circulating endothelial cells per ml of blood; they have a quiescent phenotype, and about 50% of them are microvascular as evidenced by CD36 positivity. See, A. Solovey et al., New Engl. J. Med., 337, 1584 (1997), who reported using the methodology of Gupta et al., cited above, to coculture viable circulating endothelial cells identified in the blood of patients with sickle cell anemia with primary microvascular endothelial cells (MVEC). T. Asahara et al., Science, 275, 964 (1997) isolated putative endothelial cell (EC) progenitors from human peripheral blood after CD34+ enrichment by magnetic bead selection on the basis of cell surface antigen expression. The cells were cultured on fibronectin-coated wells in modified M-199 medium containing bovine brain extract and 20% fetal bovine serum. Q. Shi et al., Blood, 92, 362 (1998) characterized bone marrow-derived precursor endothelial cells by isolating CD34+ cells derived from peripheral blood using murine anti-CD34+ antibody binding followed by exposure to anti-mouse immunomagnetic beads. The cells were cultured in gelatin or fibronectin-coated plastic wells in M199 medium containing VEGF, FBS, bFGF and IGF.
However, due to the low concentration of CEC in blood, a need exists for a culture method and medium that will permit the rapid expansion of CEC from blood, without the attendant difficulties of isolation discussed above.


1. Technical Field
The present invention relates to an improved data processing system and in particular to a method and apparatus for transmitting data. Still more particularly, the present invention relates to a method and apparatus for managing transmission of data from a source to a destination.
2. Description of the Related Art
Two basic types of communications connections are employed between processors and between a processor and a peripheral. These types of connections are known as channels and networks. A channel provides a direct or switched point-to-point connection between communicating devices. This type of connection is typically employed between a processor and a peripheral device. The primary task of the channel is to transport data at the highest possible speed with the least delay. In contrast, a network is an aggregation of distributed nodes, such as workstations, file servers, and peripherals. Typically, in a network a node contends for the transmission medium and each node must be kept free of error conditions on the network. A traditional channel is hardware intensive and typically has lower overhead than a network. Conversely, networks tend to have relatively high overhead because they are software intensive. Networks, however, are expected to handle a more extensive range of tasks as compared to channels. In a closed system, every device addressed is known to the operating system either by assignment or pre-definition. This configuration knowledge is important to the performance levels of channels. Fibre Channel is a channel-network hybrid containing network features to provide the needed connectivity, distance, and protocol multiplexing along with enough traditional channel features to retain simplicity, repeatable performance, and guaranteed delivery. Fibre Channel has an architecture that represents a true channel/network integration. Fibre Channel allows for an active intelligent interconnections scheme, called a fabric, to connect devices. A Fibre Channel port manages simple point-to-point connection between itself and the fabric. A xe2x80x9cportxe2x80x9d is a hardware entity on a xe2x80x9cnodexe2x80x9d with a node being a device connected to a network that is capable of communicating with other network devices. Transmission is isolated from control protocol. As a result, different topologies may be implemented. Fibre Channel supports both large and small data transfers.
The demand for flexible, high performance, fault-tolerant storage subsystems caused host adapter, disk storage, and high-capacity drive manufacturers to adopt Fibre Channel (FC) as a standard. This serial standard cuts cabling costs, increases data rates, and overcomes distance limitations commonly associated with a Small Computer System Interface (SCSI). Fibre Channel can carry SCSI protocols, and as a result offers an ideal upgrade for work stations, servers, and other systems requiring high availability and/or high bandwidth. Fibre Channel has become increasingly important as companies are seeking to provide faster and easier access to data for various clients. The Fibre Channel Standard (FCS) as adopted by the American National Standards Institute (ANSI), provides a low cost, high speed interconnect standard for workstations, mass storage devices, printers, and displays.
Current Fibre Channel data transfer rates exceed 100 megabytes (Mbytes) per second in each direction. Fibre Channel data transfer rates also may be scaled to lower speed, such as 50 Mbytes per second and 25 Mbytes per second. This technology provides an interface that supports both channel and network connections for both switched and shared mediums. Fibre Channel simplifies device interconnections and reduces hardware cost because each device requires only a single Fibre Channel port for both channel and network interfaces. Network, port to port, and peripheral interfaces can be accessed though the same hardware connection with the transfer of data of any format.
In sending data from a source node to a destination node, the source transmits data from a bus, such as a Peripheral Component Interconnect (PCI) bus, to a buffer for transfer onto a Fibre Channel system, which is connected to the destination node. Data is sent serially on Fibre Channel systems. As a result, data currently in a buffer must be sent before additional data may be loaded. Currently, if data cannot be sent because the destination is not accepting additional data, then this data must be removed to send data to another destination. This loading and dumping of data increases the overhead in transferring data between various nodes on a Fibre Channel system. Thus, it would be advantageous to have an improved method and apparatus for transferring data between nodes in which the overhead of acquiring the dumping and reloading of new data is eliminated.
The present invention provides a method and apparatus for transmitting data in a node having a buffer. A first set of data is received in a buffer for transmission to a target node. The first set of data is sent to the target node. Responsive to an indication that the target node is unable to receive data, a second set of data is loaded into the buffer for transmission to another target node, while the first set of data is retained in the buffer.


The Field of the Invention
The present invention relates to a digital broadcasting system for transmitting and receiving a digital broadcast signal, and more particularly, to a transmitting system for processing and transmitting the digital broadcast signal, and a method of processing data in the transmitting system and the receiving system.
Description of the Related Art
The Vestigial Sideband (VSB) transmission mode, which is adopted as the standard for digital broadcasting in North America and the Republic of Korea, is a system using a single carrier method. Therefore, the receiving performance of the digital broadcast receiving system may be deteriorated in a poor channel environment. Particularly, since resistance to changes in channels and noise is more highly required when using portable and/or mobile broadcast receivers, the receiving performance may be even more deteriorated when transmitting mobile service data by the VSB transmission mode.


The present invention relates to a table for holding, by suction under vacuum, an original document to be imaged by an imaging apparatus or the like. More particularly, the invention relates to an original table suitable for use with an imaging apparatus that performs imaging of an original to provide an image on a printing plate or for use with a platemaking apparatus used for this purpose.
A typical configuration of an original table used with a conventional imager for plate making or platemaking apparatus is shown in FIG. 1. Specifically, an original mount 1 equipped at one side with a pivotable glass holder 2 holds the original 3 in position by means of the glass 2 during imaging.
A problem with the original table using a holder glass is that the glass is heavy and makes the handling of the table cumbersome. Furthermore, at low reduction ratios, the original table must be placed only a short distance from the optical system, and this prevents the glass holder from opening sufficiently to achieve perfect registry of the original.


As is well known to those skilled in the art, various catalysts are used in processing. Many of these catalysts are characterized by the presence of catalytically active components on a support. Attempts are constantly being made to improve the properties of the support and to thus permit attainment of a catalyst composition, containing support preferably plus other ingredients, which is characterized by desirable properties including, for example, conversion, yield, selectivity, etc.
It is an object of this invention to provide a novel alumina, and a process for making this product. Other objects will be apparent to those skilled in the art.


1. Technical Field
The relates to a phase-change random access memory (PCRAM) device, and more particularly, to a PCRAM device and a method of manufacturing the same.
2. Related Art
With demands on lower power consumption, next-generation memory devices having nonvolatile and non-refresh properties have been studied. A PCRAM device of the next-generation memory devices includes a switching element connected at intersections of word lines and bit lines, which are arranged to cross each other, a lower electrode electrically connected to the switching element, a phase-change layer formed on the lower electrode, and an upper electrode formed on the phase-change layer.
In a conventional PCRAM device, when a write current flows through the switching element and the lower electrode, Joule heat is generated at an interface between the phase-change layer and the lower electrode. The phase-change layer is phase-changed into an amorphous state or a crystalline state by the generated joule heat. Therefore, the conventional PCRAM device stores data using a difference between resistances in the amorphous state and the crystalline state of the phase-change layer.
However, in the conventional PCRAM device, the Joule heat generated when the write current flows affects a phase-change layer of adjacent cell.
The effect on adjacent cells is generally referred to as thermal disturbance. In recent years, the thermal disturbance has an increased effect on adjacent cells when a semiconductor memory device is highly integrated.
FIGS. 1A and 1B are views illustrating thermal disturbance of a conventional PCRAM device.
As shown in FIGS. 1A and 1B, the conventional PCRAM device includes a lower electrode 10 formed on a switching element (not shown), a phase-change layer 20 formed on the lower electrode 10, and an upper electrode 30 formed on the phase-change layer 20. The reference numeral 40 denotes an insulating layer.
As shown in FIG. 1A, if a cell A is written when cells B are written with data “1”, which is a high resistance state, Joule heat is generated at an interface between the lower electrode 10 and the phase-change layer 20 of the cell A (see FIG. 1B), and thus, phase-change material patterns of amorphous states in the cells B are crystallized. Therefore, resistances of the cells B are reduced.
The thermal disturbance generated in the conventional PCRAM device may cause a malfunction, and thus reliability of the conventional PCRAM device is degraded.


1. Field of Invention
This invention relates generally to optical systems for the storage and retrieval of information and, more particularly, to the read/write head of the magneto-optical information storage system which directs radiation to the storage medium and then directs radiation resulting from the interaction with the medium to the radiation detectors.
2. Description of the Related Art
The optical storage systems, at present can generally be placed into one of two categories, the categories determined by the optical property used to identify different logical states on the storage medium. The first optical storage system can be referred to a differential absorption (or reflection) of a radiation beam impinging on the storage medium surface. In the differential absorption optical systems, each logical states are associated with changes in the intensity of a beam of radiation interacting with the storage medium. In the second category of optical storage systems, changes in the rotation of plane polarized beam of radiation are used to identify optical states. The present invention is directed to the second or the magneto-optical storage and retrieval systems and provides a technique for determining selected parameters in the optical path to enhance the identification of the two orientations of magnetic regions, orientations which encode the data stored on the disk.
Referring to FIG. 1, the implementation of the read/write head in a magneto-optical information storage system, the system relying on differential rotation of the planar polarization of a optical radiation caused by the interaction of the optical radiation with the storage surface, is shown. This type of storage system relies on the Kerr effect wherein the rotation of a plane of polarization is different when a magnetic material has a magnetic orientation parallel to or a magnetic orientation anti-parallel to the direction of the radiation interacting with the magnetic material, i.e., the differential change in polarization of a reflected beam depends upon the orientation of the magnetization of the local domain with which the radiation interacts. As with the implementation for detecting a change in reflected light amplitude, the radiation from a light source 10 is collimated by lens 11 and one plane of polarization is selected by passing the collimated beam through the partial beam splitter 12'. Because linearly polarized radiation can be considered to be comprised of two circularly polarized radiation components, the interaction with the magnetic layer forming a portion of storage medium 15 effects the two circularly polarized components differently. As a result, after interaction with the storage material, the reflected radiation is not linearly polarized parallel to the applied radiation, but an elliptical polarization of the reflected radiation results in a rotation of the reflected linear polarization due to the circular dichroism and the circular birefringence of the storage media. The reflected radiation is recollimated by objective lens 14. The recollimated beam is applied to beam splitter 12 and the components of the radiation beam orthogonal to the plane of polarization of the radiation impinging on storage medium, i.e., the components induced by the interaction, are reflected by the beam splitter 12. Some of the light with polarization parallel to the impinging radiation can also be reflected from the magneto-optic region. The radiation reflected by the beam splitter 12 is transmitted through a quarter wave plate 16A and a half wave plate 16B to correct for ellipticity introduced into the radiation beam. The polarization beam splitter 17 divides the radiation reflected from beam splitter 12 into radiation components which have been rotated by the interaction with the storage material. Each detector 18 and 19 receives a component resulting from one orientation of the magnetic regions of the storage medium interacting with the impinging radiation beam. The differential amplifier 20 is used to enhance the detectability of the small signals, the rotation due to the Kerr effect typically being less than 2.degree. relative to reflected radiation which had not been subjected to differential interaction of the circularly polarized components with the optical storage material and to cancel the large DC component of the two radiation components.
In the optical storage systems using a magneto-optical storage medium, a need has been felt for a technique of determining how to optimize the parameters of the system in order to achieve the most detectable signal. In the article by W. A. Challener and T. A. Rinehart, "Jones Matrix Analysis of Magnetooptical Media and Read-Back Systems", Appl. Opt. 26, 3974 (1987), part of the problem of a differential detection system was addressed. In that article, the substrate birefringence and the wave plate tolerances were studied. However, the DC offset in the differential signal was not considered and a range of "ideal" wave plates was found, each with a sensitivity to the optical path birefringence. Therefore, the need has remained for generally applicable technique for identifying the parameters which would permit optimization of the detection of the state of the region of the storage system to which radiation was being applied.


1. Field of the Invention
The present invention relates to a design system, a design method, and a storage medium storing a design program for a structural analysis after amending the form of a model.
2. Description of the Related Art
Conventionally, when a desirable model form is obtained to minimize the weight while maintaining the strength in analyzing a structure, a plurality of candidates for a desirable form (basis vector) are defined, and then the form (a) is divided into mesh units as shown in FIG. 1 into the form (b). Then, in a manual operation, as indicated by the form (c), the coordinate indicated by a small circle (∘) of a node on each of the edges (sides) of the divided mesh units is manually input (by specifying the x, y, and Z coordinates) and amended. A structural analysis is made on a model formed based on the amended edge according to the well-known boundary conditions and the attribute (strength, weight, etc.) of a material to obtain the optimum solution satisfying a predetermined strength, for example, a model form lightest in weight.
When the above described optimization is performed, it is necessary to divide a model into mesh units, and manually associate a node on each edge (side) with a coordinate value as shown by (c) in FIG. 1. If the number of nodes is large, then a great number of manual operations are required, thereby preventing a quick structural analysis.
To solve the above described problems, the present invention aims at quickly performing a structural analysis in a simple operation by dividing a model into mesh units, specifying a child edge of an optional curve in a parent edge, projecting the parent edge into the child edge, automatically computing the coordinates, and obtaining the optimum solution in a structural analysis based on the computation.
According to the first aspect of the present invention, the design system which analyzes a structure by amending the form of a model includes: a mesh division unit for dividing the model into mesh units; a child edge generation and display unit for generating and displaying a child edge, which is newer than a parent edge divided into mesh units; an amendment unit for amending the displayed child edge into an optional form, an association unit for obtaining the correspondence between the above described parent unit and the amended child unit; and a structural analysis unit for analyzing the structure of the amended model form depending on the obtained correspondence.


The invention relates to a method for decontaminating nuclear reactors employed to generate electric power and more particularly to a method for performing full system decontaminations on boiling water reactors.
During on-line power generating operations of commercial boiling water nuclear reactors, thin layers of metal oxides tend to build up on the internal surfaces of vessels and other components and piping in contact with circulating primary coolant (essentially high temperature water). Activated metal ions in the central core regions in reactor pressure vessels are entrained in the primary coolant and then are absorbed in the metal oxides, which results in relatively high radiation levels on these surfaces. It is desirable to reduce the radiation levels to xe2x80x9cAs Low As Reasonably Achievablexe2x80x9d levels in order to reduce the exposure of personnel working near the reactors during periodic plant outages and/or plant decommissioning operations. Thus, the industry may employ one or a combination of various known chemical decontamination treatments, e.g., acid permanganate, alkaline permanganate, Citrox, CAN-DEREM, LOMI and/or other processes, in order to dissolve or break up the oxide films. Conventionally, these decontamination processes involve the addition of permanganate, oxalate, citrate, EDTA and/or other ions to the primary coolant to form decontamination solutions and then the circulation of the solutions through the components to be decontaminated. In addition to removing the oxide layers, it may be desirable to remove several microns of base metal in order to better protect personnel during decommissioning processes. Dilute chemical decontamination solutions generally contain less than about 3-5% by weight of such decontamination agents. Chemical decontaminations may be performed upon full primary coolant systems or upon selected subsystems. Full system decontaminations are the preferred approach when the goal is to reduce dose rates on multiple subsystems throughout the plants. In addition, full system decontamination processes are generally performed with nuclear fuel assemblies out of the central core regions of the reactor pressure vessels, but the fuel assemblies may be retained in the central core regions in some cases.
The activated metal ions that are removed from the internal surfaces of the primary coolant systems in the course of the decontamination operations are collected on cation exchange resins. The activated resins must then be removed to remote disposal sites.
The majority of the activated oxide deposits in boiling water reactor primary coolant systems are located in the central core regions of reactor pressure vessels. These deposits do not substantially contribute to personnel exposure. Thus, it would be very desirable to decontaminate only those systems that substantially contribute to personnel exposure and bypass the central core regions. This would substantially reduce the total exposure of personnel while reducing resin and disposal costs.
It is an object of the present invention to decontaminate a portion of a reactor pressure vessel in a boiling water reactor and its appurtentant recirculation system while bypassing its central core region. It is a further object to substantially decontaminate a boiling water reactor with lower overall personnel exposures to radiation and lower resin costs.
With these objects in view, the present invention resides in a method of decontaminating a boiling water reactor having a plurality of reactor recirculation loops hydraulically connected in parallel with a reactor pressure vessel. Such a reactor pressure vessel has: a central core region; an annulus region surrounding the central core region and in hydraulic communication with the recirculation loops; and a lower internals region in hydraulic communication with the central core region. In the practice of the present invention, a decontamination solution is circulated through at least one of the reactor recirculation loops and the annulus region of the pressure vessel without circulating through the central core region. In a preferred practice of the present invention, the decontamination solution also circulates between the annulus region and the lower internals region without circulating through the central core region. Thus, a boiling water reactor can be substantially decontaminated while reducing overall personnel exposure and generating less resin wastes.


Blood clot formation, or “thrombosis,” is a basis of a number of serious diseases, such as ischemic stroke, myocardial infarction (heart attack), and deep vein thrombosis (DVT). Blood clots, or “thrombi,” form inside blood vessels and obstruct the flow of blood through the circulatory system, thereby depriving tissue and organs of oxygen. In the case of a stroke, for instance, when blood flow to the brain is obstructed for longer than a few seconds, brain cells can die and permanent neurological damage can result.
Thrombi can be treated (reduced or eliminated) by inducing thrombolysis. Thrombolysis is the dissolving, or “lysis,” of a thrombus. Thrombolysis can sometimes be induced pharmacologically, such as by administering a tissue plasminogen activator drug (tPA), the most common thrombolytic agent. Thrombolytic agents (commonly called “clot-busting drugs”) can be administered via an intravenous line or using a catheter to deliver them proximally to the thrombus. However, thrombolysis by administration of clot-busting drugs has its limitations. For example, to be successful, the clot-busting drugs should be administered within three (3) hours of an acute ischemic stroke, and preferably within two (2) hours. Further, patients who use blood-thinning medications, and certain other medications, are usually not candidates for pharmacological thrombolysis. And of those patients receiving the treatment, it is unsuccessful in dissolving thrombi in approximately 25% of patients.
In view of the limitations of pharmacologically induced thrombolysis, various medical devices for surgically removing thrombi have been developed. The procedure for surgically removing thrombi is generally known as a “thrombectomy.” In thrombectomy treatments, a catheter system is typically used to deliver a device to the thrombus. The device can be, for example, an aspiration catheter. Aspiration catheters can perform a thrombectomy by suctioning the thrombus out of the blood vessel. Other thrombectomy procedures use a mechanical device to physically entangle with a thrombus, and to remove the thrombus as the device is removed from the blood vessel. Various types of mechanical devices, such as wires, corkscrew-like coils, bristles, and baskets have been employed to entangle with thrombi.
Some traditional thrombectomy devices can cause damage to blood vessel walls. In addition, some traditional thrombectomy devices can be prone to generating thrombotic fragments that become emboli when they travel within the bloodstream. Emboli can become lodged in arteries, veins, arterioles, and capillaries, and can block the blood supply to vital organs such as the brain or heart. Emboli in the bloodstream can be life-threatening. In the case of DVT treatment, dislodged thromboemboli can travel to the lungs, resulting in a pulmonary embolism, which can be fatal.


The present invention relates to electrochemical conversion cells, commonly referred to as fuel cells, which produce electrical energy by processing first and second reactants. For example, electrical energy can be generated in a fuel cell through the reduction of an oxygen-containing gas and the oxidation of a hydrogenous gas. By way of illustration and not limitation, a typical cell comprises a membrane electrode assembly (MEA) positioned between a pair of flowfields accommodating respective ones of the reactants. More specifically, a cathode flowfield plate and an anode flowfield plate can be positioned on opposite sides of the MEA. The voltage provided by a single cell unit is typically too small for useful application so it is common to arrange a plurality of cells in a conductively coupled “stack” to increase the electrical output of the electrochemical conversion assembly.
The membrane electrode assembly typically comprises a proton exchange membrane separating an anode layer and a cathode layer of the MEA. The MEA is typically characterized by enhanced proton conductivity under wet conditions. For the purpose of describing the context of the present invention, it is noted that the general configuration and operation of fuel cells and fuel cell stacks is beyond the scope of the present invention. Rather, the present invention is directed to methods for managing MEA hydration cycling fatigue life in fuel cells. Regarding the general configuration and operation of fuel cells and fuel cell stacks, applicants refer to the vast collection of teachings covering the manner in which fuel cell “stacks” and the various components of the stack are configured. For example, a plurality of U.S. patents and published applications relate directly to fuel cell configurations and corresponding methods of operation. More specifically, FIGS. 1 and 2 of U.S. Patent Application Pub. No. 2005/0058864 and the accompanying text present a detailed illustration of the components of one type of fuel cell stack and this particular subject matter is expressly incorporated herein by reference.


This invention relates to the simultaneous measurement of the concentration of a selected ion species in a solution and the pH of the solution. The invention particularly, though not exclusively, relates to photographic solutions, and particularly, though not exclusively, where the selected ion species is silver. In general, however, the invention relates to the simultaneous potentiometric measurement of the concentration of any ion species in a solution and measurement of the pH of the solution using an ISFET (Ion Selective Field Effect Transistor).
For the present purpose the tern xe2x80x9csolutionxe2x80x9d is to be understood as also including an emulsion, for example a mixture of a silver compound suspended in gelatin, or a dispersion. The invention will be particularly described, by way of example only, with reference to photographic solutions.
It is known simultaneously to measure silver ion concentration in, and the pH of, an aqueous solution. In one arrangement, a single reference electrode is connected into a first potentiometer circuit with a conventional glass pH electrode, and is connected into a second potentiometer circuit with a conventional silver electrode, all three electrodes being immersed in the solution. In another arrangement, an ISFET is used instead of the glass pH electrode. This necessitates the use of a separate reference electrode for each measuring circuit in order to provide electrical isolation between the circuits since the ISFET is a current carrying device whose presence would otherwise interfere with the voltage measurement of the silver electrode.
A glass pH electrode has the disadvantage that it can be damaged under conditions of high temperature and high pH, so that its readings become unreliable or inconsistent. An ISFET overcomes this disadvantage. However, the conventional arrangement including an ISFET described above is complicated by the requirement of the additional reference electrode, especially when applied in a large scale production vessel, as used in the preparation of photographic emulsions for example, where the electrodes are configured in a unitary probe. This can lead to difficulties for maintenance and for calibration. Furthermore, existing probe structures would require extensive modification to accommodate the additional reference electrode, which would be expensive.
It will be appreciated that if, on the other hand, measurement of ion concentration and pH were not required simultaneously, then the measurements would not interfere with each other and a single reference electrode could be used successively in combination with an ion concentration electrode and an ISFET.
In accordance with one aspect of the present invention, there is provided apparatus for simultaneously measuring the concentration of a selected ion species in a solution and the pH of the solution, comprising: a first electrical circuit that is arranged to receive signals from both a reference electrode and an ion selective electrode immersed in the solution and to derive therefrom an output signal representative of the concentration of the selected ion in the solution; a second electrical circuit that is arranged to receive signals from both said reference electrode and an ISFET immersed in the solution and to derive therefrom an output signal representative of the pH of the solution; wherein any d.c. input signal to said first electrical circuit from the reference electrode is substantially electrically isolated from the input of the second circuit; wherein a signal representative of the voltage, usually earth potential, of the solution is supplied (a) directly to the first circuit so as to establish a reference, usually earth, potential for the first circuit, and (b) to the second circuit through a.c. coupling means so as to establish a corresponding virtual reference, usually earth, potential for the second circuit; and wherein the first and second electrical circuits are arranged to be provided with electrical power from supplies that are electrically isolated from each other.
The apparatus may comprise means for displaying a representation of said ion concentration and pH output signals, wherein said second electrical circuit includes an isolation amplifier, and wherein said display means is arranged to receive said pH output signal of the second circuit through the isolation amplifier. Preferably, the apparatus includes a further isolation amplifier through which the ion concentration output signal of the first circuit is supplied to the display means. Advantageously, the apparatus comprises a low pass filter, wherein said pH output signal from the second electrical circuit is arranged to be passed to the display means through the low pass filter.
Preferably, the apparatus comprises a high value resistor, for example of about 1 Mxcexa9 or greater, that is arranged to effect said electrical isolation of d.c. input signals to said first and second electrical circuits. Also said a.c. coupling means may comprise a high value capacitor, for example of about 1 xcexcF or greater.
In accordance with another aspect of the present invention, there is provided a method of simultaneously measuring the concentration of a selected ion species in a solution and the pH of the solution, comprising the steps of: measuring in a first electrical circuit the potential difference between an ion selective electrode and a reference electrode both immersed in the solution, and deriving therefrom the concentration of the ions in the solution; measuring in a second electrical circuit the current flowing between an ISFET and the reference electrode both immersed in the solution, and deriving therefrom the pH of the solution; connecting the reference electrode to the first and second electrical circuits such that any d.c. signal from the reference electrode is electrically isolated from the second circuit; making an electrical connection between the solution and the first circuit so as to provide the solution potential as a reference, preferably earth, potential therefore, and making an electrical connection between the solution and the second circuit through a.c. coupling means so as to provide a corresponding virtual reference, preferably earth, potential therefore; and supplying the first and second circuits with electrical power from sources that are electrically isolated from each other.
The method of the invention is advantageously carried out using the apparatus of the invention.
Details of electrodes suitable for use in the present invention as ion selective and reference electrodes, and of ISFETs, can be found in the book xe2x80x9cpH Measurementxe2x80x9d by Helmuth Galster (VCH,1991).
The electrical isolation of the two circuits provided in the present invention allows an ISFET to be used in the pH measuring circuit, whilst needing only a single, common, reference electrode. The disadvantages of the known arrangements for simultaneous ion concentration and pH measurement are thus overcome in a particularly convenient manner.
The isolation is provided at several stages. Initially this is done by arranging that the signal from the reference electrode is used in the ion concentration circuit as a potentiometric measurement, and is supplied to the pH measuring circuit only as an a.c. input, i.e. after having any d.c. component isolated therefrom. An actual reference potential, the potential, usually earth, of the solution, is applied to the first circuit, and a virtual reference potential derived therefrom is applied to the second circuit. The two circuits have separate isolated power supplies. Furthermore, when the resulting ion concentration and pH signals are supplied to a display means, such as a multi-channel voltmeter, this is done through respective isolation amplifiers, which are preferably supplied from a third, isolated power supply.
The ability to use a single reference electrode means that a single, unitary measurement probe can be constructed, in which the ISFET can be installed relatively easily along with the ion selective and reference electrodes. Furthermore, the measuring apparatus can be calibrated more easily than is the case with the known arrangement using two reference electrodes.
Although described with reference to a single ion selective electrode and a single ISFET, it is envisaged that the present invention may comprise two or more ion concentration electrodes and/or two or more ISFETs, each type of electrode being connected into the respective first or second electrical circuit.
Apparatus for, and a method of, simultaneously measuring the concentration of a selected ion species in a solution and the pH of the solution, will now be described, by way of example, with reference to the accompanying schematic circuit diagram.


The present application relates generally to methods and systems for making payments for recyclable items such as beverage containers deposited at reverse vending machines.
Container deposit laws also known as “bottle bills” require consumers to pay a small refundable deposit on containers (such as beer, soft drink, and other beverage containers) they purchase to improve the rate of recycling or reuse.
Bottle bills in most states typically work as follows. When a retailer buys beverages from a distributor, the retailer pays a deposit to the distributor for each can or bottle purchased. The consumer pays the deposit to the retailer when buying the beverage. When the consumer returns the empty beverage container to the retail store, a redemption center, or a reverse vending machine, the deposit is refunded. The retail store or redemption center recoups the deposit from the distributor, typically along with an additional handling fee to help cover the cost of handling the containers.
As used herein, the term “distributor” refers to a product maker (e.g., the company producing the product such as the Coca-Cola Company) or to an entity distributing products from a product maker to retailers.
Reverse vending machines are automated machines that accept used beverage containers and return container deposits to users. Manufacturers of reverse vending machines include Tomra, Wincor Nixdorf, Envipco, Repant, reVend, and Can and Bottle Systems.
In use, the user places the empty beverage container into a receiving aperture of the reverse vending machine. The reverse vending machine automatically identifies the beverage container, e.g., by scanning the beverage container's UPC code. Eligible containers are accepted, and the user is paid. The user is typically given a receipt that can be redeemed at a retailer checkout station. Accepted containers are typically crushed or broken in the reverse vending machines to reduce their size.


Carousels, merry-go-rounds, playground rides, or playground roundabouts have long been a popular equipment on playgrounds for children of all ages, and can be found in numerous different configurations, sizes, functionality, and designs.
Typically such playground roundabouts comprise some sort of platform or seats to accommodate the one or more users and which then is turned either mechanically, by others or by the persons on the roundabout themselves.
Different types of roundabouts exist yielding different types of movement of the user not only making the user circle in a horizontal plane but also move up and down, or spin around his own axis etc.
U.S. Pat. No. 3,073,595 describes a playground ride where the seating platform is arranged on two freely rotating and separated hubs whose axis of ration are angularly offset resulting in a special combination of circular motion and vertical motion. As the seating platform can be rotated fast or slowly and in changing direction relative to the rotation of the base column is obtained a more exhilarated ride where the resulting movement is perceived as unpredictable by the user.
Another type of exercising device is described in U.S. Pat. No. 4,290,601 comprising a wobble plate mounted on a single shaft to a base and placed on one side on top of a roller assembly thereby creating a raised position of one portion of the wobble plate. The roller assembly is in one embodiment made from pair of hemispherical balls and held in its radial position by a radial arm connected to the shaft. A person standing on the wobble plate can then set the board in motion. The design with the roller assembly moving between the base and the underside of the wobble board however yields a construction with a relatively high number of movable parts and with a number of places where objects such as clothes, fingers etc. can get caught or entangled. The latter especially makes the exercise device unsuitable as a playground equipment.
EP 1747803 discloses an exercising apparatus of an oscillating platform placed at an angle relative to a support platform and free to rotate around two non-parallel axes. Different configurations of the plate and the axes relative to each other yield different types of motion of the user. Also, the platform rotating assembly may be driven by a gear assembly configured to rotate the platform at a predetermined rate such that the platform rotates relative to the platform by a predetermined amount during use. Thereby the amount of oscillating can be controlled however without influencing the type of motion of the user.


The present invention relates to an erasing method of a floating gate type nonvolatile semiconductor storage device.
In recent years, there has been a demand for reducing the power consumption in accordance with increase of integration level in a flash memory of a nonvolatile semiconductor storage device. In response to the above demand, a reduction in consumption of power is enabled by using the Fowler-Nordheim tunneling phenomenon for write (program) and erase operations. The flash memory that executes the write and erase operations utilizing the Fowler-Nordheim (referred to as FN hereinafter) tunneling phenomenon is called the FN--FN type flash memory.
On the other hand, flash memories are classified by the memory cell array structure, and four principal types will be enumerated hereinbelow.
[1] The Institute of Electronics, Information and Communication Engineers Technical Report, ICD93-128, p37, 1993
An AND type flash memory reported as ""AND" cell structure for a 3V-only 64Mbit Flash Memory"
[2] The Institute of Electronics, Information and Communication Engineers Technical Report, ICD93-26, p15, 1993
A DINOR type flash memory reported as "A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory"
[3] IEDM Technical Digest, p263-266, 1995
A DuSNOR type flash memory reported as "A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memories"
[4] IEDM Technical Digest, p267-270, 1995
An ACT type flash memory published in "A New Cell Structure for Sub-quarter Micron High Density Flash Memory" and "A sensing Scheme for a ACT flash memory" of The Institute of Electronics, Information and Communication Engineers Technical Report, ICD97-21, p37, 1997
The above types are published by several companies.
According to the flash memories of the above types [1] through [4], it is acceptable to execute electrical writing (program) and erasing on a memory cell. However, a voltage is applied to the drain, source or control gate of the selected memory cell in the write operation and the erase operation, while a voltage is also applied to the drain, source or control gate of the unselected memory cell. The threshold voltage of the unselected memory cell is changed by the influence of this voltage application, possibly causing erroneous reading
In recent years, there is an increasing trend toward using a method for applying a negative voltage to the semiconductor substrate (well) in order to reduce the absolute value of a voltage to be used inside the flash memory in the erase operation. This negative voltage applied to the semiconductor substrate brings the unselected memory cell whose drain, source or control gate receives the voltage into a lightly erased state, exerting bad influence (referred to as a substrate disturbance hereinafter) on the threshold voltage of the unselected memory cell. The substrate disturbance tends to become more severe as the flash memory comes to have a larger capacity.
The aforementioned substrate disturbance will be described by taking the ACT (Asymmetrical Contactless Transistor) type flash memory as an example.
FIG. 6 shows a sectional view of one memory cell of the above ACT type flash memory, and the principle of operation of the ACT type flash memory will be described with reference to FIG. 6.
In the above ACT type flash memory of FIG. 6, a tunnel oxide film 14, a floating gate 15, an interlayer insulating film 16 and a control gate 17 are lamellarly formed on a substrate (p-type well) 11 so as to form a bridge between a drain 13 and a source 12 formed on the substrate 11. Then, the drain 13 and the source 12 have different donor concentrations.
In the case of a program operation in the ACT type flash memory having the aforementioned construction, that is, in the case where electrons are extracted from the floating gate 15 to provide a written state (data "0"), a negative voltage Vnw (-8 V) is applied to the control gate 17 and a positive voltage Vpp (+5 V) is applied to the drain 13, thereby extracting electrons from the floating gate 15 by the Fowler-Nordheim (referred to as FN hereinafter) tunneling phenomenon with the source 12 brought into the floating state. By this a program operation, the threshold voltage of the memory cell is lowered to a voltage of about 1.5 V.
In the case of an erase operation, that is, in the case where electrons are injected into the floating gate 15 to provide an erased state (data "1"), a positive voltage Vpe (+10 V) is applied to the control gate 17, a negative voltage Vns (-8 V) is applied to the source 12, and the drain 13 is brought into the floating state. Electrons are injected into the floating gate 15 by the FN tunneling phenomenon. Therefore, the threshold voltage of the memory cell is increased to a voltage of about 4 V or more.
In the case of a read operation, a voltage of +3 V is applied to the control gate 17, a voltage of +1 V is applied to the drain 13, and a voltage of 0 V is applied to the source 12. The data is read by the sensing circuit (not shown) for sensing the current flowing through the memory cell.
The voltages applied to the memory cell in the program, aforementioned operations are shown in Table 1.
TABLE 1 Control Substrate Gate Drain Source P-Type Well Program -8 V 5 V Open 0 V Operation Erase 10 V Open -8 V -8 V Operation Read 3 V 1 V 0 V 0 V Operation
In order to explain the substrate disturbance in the erase operation, the application voltage in the erase operation will be described with reference to the array structure of the ACT type flash memory shown in FIG. 7. As schematically shown in FIG. 7, the array structure of the ACT type flash memory has a virtual-ground-type array structure in which two memory cells jointly own an identical bit line.
In the above ACT type flash memory are shown main bit lines BL0 through BL4096, sub-bit lines SBL00 through SBL04096 and SBL10 through SBL14096 formed from a diffusion layer (the sub-bit lines being in a layer different from that of the main bit lines), word lines WL0 through WL63, selection gate signal lines SG0 and SG1 of selection transistors ST00 through ST04096 for selecting each block and a contact section CN (the portions each being indicated by the mark .box-solid. in FIG. 7) of the main bit lines BL0 through BL4096 and the sub-bit lines SBL00 through SBL04096 and SBL10 through SBL14096. Then, in regard to the memory cells M00, M01, ... , M10, M11, ..., the number of contacts is reduced by making the memory cells of adjoining lines jointly own the sub-bit lines SBL01 through SBL04095 and SBL11 through SBL14095 and using the diffusion layer for the sub-bit lines SBL00 through SBL04096 and SBL10 through SBL14096, by which the array area is sharply reduced, allowing high-density integration to be achieved.
FIG. 8 schematically shows the sub-bit lines SBL00 through SBL04096 and SBL10 through SBL14096 (shown in FIG. 7) formed from the aforementioned diffusion layer in the form of a cross-section of the essential part of the ACT type flash memory.
As shown in FIG. 8, an interlayer insulating film 22, a floating gate 23 (FG) and a control gate 24 (WL) are lamellarly arranged on a semiconductor substrate 20 on which a sub-bit line 21 (diffusion layer) is formed. Then, the common sub-bit line 21 provided below the end portion of adjoining floating gates 23 (FG) has donor concentrations that differ between a drain 21a and a source 21b.
In the case of the aforementioned ACT type flash memory, the erasing operation is executed on a block basis. In the erase operation, for example, a positive voltage (+10 V) is applied to the word lines WL0 through WL31 connected to the control gates of the memory cells M00, M01, . . . of a selected block BLOCK0 shown in FIG. 7 in order to increase the threshold voltage of the memory cells. Further, a negative voltage (-8 V) is applied to a semiconductor substrate (well) and the main bit lines BL0 through BL4096. In this stage, the selection gate signal line SG0 has a voltage of 0 V to turn or the selection transistors ST00 through ST04096, and a negative voltage (-8 V) is applied to the sub-bit lines SBL01 through SBL04095. By this operation, a high electric field is generated between the floating gates and the channels of the memory cells M00, M01, . . . , by which electrons are injected into the floating gate by the FN tunneling phenomenon, increasing the threshold voltage of the n memory cells M00, M01, . . . to a voltage of 4 V.
On the other hand, in an unselected block BLCK1 in FIG. 7, a reference voltage Vss (0 V) is applied to the word lines WL32 through WL63. When a negative voltage (-8 V) is applied to the selection gate signal line SG1, then the selection transistors ST10 through ST14096 are turned off, as a consequence of which the sub-bit lines SBL10 through SBL14096 connected to the selection transistors ST10 through ST14096 are brought into the floating state. In this stage, the semiconductor substrate is common to all the memory cells. Therefore, the negative voltage (-8 V) is applied to the substrate, and an electric field is generated between the floating gate and the semiconductor substrate although the above electric field is less than that of the foregoing selected block. This electric field causes injection of electrons into the floating gate. The injection of electrons into the floating gate in the unselected block more frequently occurs in the memory cell in the low threshold voltage state, i.e., in the memory cell in the programmed state, i.e., in the memory cell of data "0".
Here is now considered the substrate disturbance in a 64-M flash memory in which 512 blocks each having a block size of 16 KB exist. If each block has been subjected to one million times of rewriting, assuming that each erasing time is 2 ms, then a disturbance time obtained by summing up the times applied to the unselected block in the above case is expressed by: EQU 511.times.1,000,000.times.2 msec .apprxeq.10.sup.6 sec (1)
FIG. 9 shows an example of the substrate disturbance in the erase operation. In FIG. 9, the horizontal axis represents the disturbance time, while the vertical axis represents the threshold voltage Vt (conditions:control gate voltage Vg of 0 V; drain Vd and source voltage Vs of floating; and substrate voltage Vsub of -8 V). As is apparent from FIG. 9, the threshold voltage of the memory cell becomes 3 V or more after a lapse of 10.sup.6 seconds of the disturbance time and becomes higher than the Ref voltage of 3 V of the sensing circuit in the reading stage, as a consequence of which data "0" is erroneously detected as data "1", resulting in erroneous reading.
A method for alleviating she substrate disturbance as described above is disclosed in the prior art reference of Japanese Patent Laid-Open Publication No. HEI 10-92958 concerning the AND type flash memory. In this specification, a description of the AND type flash memory will be given on condition that memory cell characteristics of this erasing method are similar to the characteristics of the aforementioned ACT type flash memory in order to clarify the problem of the erasing method of the non-volatile semiconductor storage device. That is, the application voltage conditions in the program operation and the erase operation are assumed to be similar to those of Table 1.
As shown in FIG. 10, an AND type flash memory has an array structure in which memory cells M00, M01, . . . , M10, M11, . . . are arranged in a matrix form, each of the memory cells being constructed of a floating gate type field-effect transistor capable of electrically writing and erasing information. Word lines WL0 through WL31 and WL32 through WL63 are connected to control gates of the memory cells M00, M01, . . . , M10, M11, arranged in an identical row. The memory cells M00, M01, . . . whose control gates are connected to the word lines WL0 through WL31 belong to a BLOCK0. The memory cells M10, M11, . . . whose control gates are connected to the word lines WL32 through WL63 belong to a BLOCK1. In the memory cells M00, M01, . . . of the BLOCK0, sub-bit lines SBL00 through SBL04094 are jointly connected to drains of the memory cells arranged in an identical column, while source lines SL00 through SL04094 are jointly connected to sources of the memory cells arranged in an identical column. Main bit lines BL0 through BL4094 are connected to the sub-bit lines SBL00 through SBL04094 via selection transistors ST00A through ST04094A, while a selection gate signal line DSG0 is connected to the gates of the selection transistors ST00A through ST04094A. A common source line SL is connected to the source lines SL00 through SL04094 via selection transistors ST00B through ST04094B, while a selection gate signal line SSG0 is connected to the gates of the selection transistors ST00B through ST04094B. In the memory cells M10, M11, . . . of the BLOCK1, sub-bit lines SBL10 through SBL14094 are connected to the drains of the memory cells of an identical column, while source lines SL10 through SL14094 are connected to the sources of the memory cells of an identical column. The main bit lines BL0 through BL4094 are connected to the sub-bit lines SBL10 through SBL14094 via selection transistors ST10A through ST14094A, while a selection gate signal line DSG1 is connected to the gates of the selection transistors ST10A through ST14094A. The common source line SL is connected to the source lines SL10 through SL14094 via selection transistors ST10B through ST14094B, while a selection gate signal line SSG1 is connected to the gates of the selection transistors ST10B through ST14094B.
In the AND type flash memory having the aforementioned construction, the case is herein considered where information of memory shells M00, M01, . . . , in the selected block BLOCK0 is subjected to erasing.
A high positive voltage Vpp (+10 V, for example) is applied to the word lines WL0 through WL31 of the selected block BLOCK0, and a voltage Vnv (-8 V, for example) is applied to all the main bit lines BL0 through BL4094 and a semiconductor substrate (well). A reference voltage Vss (0 V, for example) is applied to the source lines SL00 through SL4094 via the common source line SL. In this stage, the reference voltage Vss (0 V, for example) is applied to the selection gate signal line DSG0 and the voltage Vnv (-8 V, for example) is applied to the selection gate signal line SSG0. Then, the selection transistors ST00A through ST04094A whose gates are connected to the selection gate signal line DSG0 are turned on, so that the voltage Vnv (-8 V, for example) is outputted to the sub-bit lines SBL00 through SBL04094. The selection transistors ST00B through ST04094B whose gates are connected to the selection gate signal line SSG0 are turned off, so that the diffusion source lines SL00 through SL04094 are brought into the floating state. By this operation, the channels of the memory cells M00, M01, . . . of the selected block BLOCK0 are turned on, by which the channel layer comes to have a voltage of -8 V to inject electrons into the floating gate. Consequently, the threshold voltage of the memory cells M00, M01, . . . of the selected block BLOCK0 increases to end the erasing.
On the other hand, in the unselected block BLOCK1, the reference voltage Vss (0 V) is applied to the word lines WL32 through WL63 connected to the control gates of the memory cells M10, M11, . . . The voltage Vnv (-8 V) is applied to the selection signal gate line DSG1, so that the selection transistors ST10A through ST14094A whose gates are connected to the selection gate signal line DSG1 are turned off, and consequently the sub-bit lines SBL10 through SBL14094 are brought into the floating state. By applying the voltage Vcc (+3 V) to the selection gate signal line SSG1 and turning on the selection transistors ST10B through ST14096B whose gates are connected to the selection gate signal line SSG1, by which the reference voltage Vss (0 V) is outputted to the source lines SL10 through SL14094 formed from the diffusion layer via the common source line SL. By this operation, a depleted layer is formed instead of a channel layer in the semiconductor substrate (well) just below the tunnel oxide film of the memory cells M10, M11, . . . of the unselected block BLOCK1. For the above reasons, the electric field between the floating gate and the semiconductor substrate (well) is alleviated, by which the substrate disturbance is alleviated.
However, in the aforementioned AND type flash memory, some of the sub-bit lines SBL10 through SBL14094 in the floating state come to immediately have the voltage of -8 V when the voltage of -8 V is applied to the semiconductor substrate (well) due to the diffusion leak (including minute defects) and so on.
For example, the case is considered where a leak current of 0.1 .mu.A exists in the sub-bit line formed from the diffusion layer. This is because the threshold voltage of a memory cell is generally defined as the voltage of the word line when the current flowing through the memory cell is 1 .mu.A in the case of the flash memory, and there are practically many sub-bit lines through which the leak current of about 0.1 .mu.A flows. In the case of the flash memory, it is practical that the leak current of the diffusion layer is not so much reduced by comparison with the DRAM.
In this case, the voltage of -8 V is applied to the semiconductor substrate (well), and a time Ts during which the sub-bit line that should be in the floating state comes to have the voltage of -8 V is expressed by: ##EQU1##
where C: sub-bit line capacitance (0.02 pF)
V: sub-bit line voltage (-8 V) PA1 Ir: leak current (0.1 .mu.A) PA1 main bit lines each connected to an associated sub-bit line so as to form a layered structure together with the associated sub-bit line, wherein: in an erase operation of a selected block of the memory cell array, a first negative voltage is applied to the semiconductor substrate, a first positive voltage is applied to the word lines of an unselected block of the memory cell array, and a reference voltage is applied to the sub-bit lines of the unselected block so that memory cells in a low threshold voltage state within the unselected block are turned on, and that a channel layer formed in each of the memory cells which have been turned on comes to have the reference voltage.
Normally, the erase pulse time is about 1 ms, and therefore, the sub-bit line comes to sufficiently have the voltage of -8 V. In this case, the channel layer is formed in the vicinity of the sub-bit line, as a consequence of which a high electric field is generated between the floating gate and the channel layer (-8 V) in the portion, and electrons are injected into the floating gate, increasing the threshold voltage. In practice, when the memory cell channel layer is sufficiently turned on (i.e., when the channel layer is formed between the source and the drain), the source side of the sub-bit line, which is connected to the common source line SL, comes to have a voltage of 0 V, and therefore, the sub-bit line comes to have a voltage (-6 V, For example) higher than the voltage of -8 V, instead of the voltage of -8 V. However, if the sub-bit line comes to have a voltage higher than -6 V , then the channel layer is cut off by a back gate effect. Therefore, the sub-bit line does not come to have a voltage higher than -6 V (the absolute value is not reduced). The voltage of this sub-bit line differs depending on the threshold voltage and so on of the memory cell.
Therefore, the nonvolatile semiconductor storage device erasing method described above has an disadvantage that the substrate disturbance cannot be stably alleviated.


1. Field of the Invention
The present invention relates to a contents playback apparatus for playing back stored contents based on a desired function, a control method for such a contents playback apparatus, and an electronic device.
2. Description of the Related Art
In recent years, there have been developed small portable contents playback apparatus for storing contents such as music pieces, photographs, and moving images, in a semiconductor memory and playing back the stored contents according to instructions from the user. Particularly, as the storage capacity of semiconductor memories has increased and the cost thereof has decreased, contents playback apparatus that are very small in size and can store a large amount of contents have emerged and are finding a wider range of applications.
Since the contents playback apparatus can store a large amount of various contents, they incorporate various playback functions to be able to quickly find and play back favorable data of the user. For example, if a contents playback apparatus has read music data from a CD (Compact Disc) or the like and stored the read music data, then the user can select, from the functions of the contents playback apparatus, a function to retrieve desired music pieces sorted by artist or album and play back the retrieved music pieces, a function to narrow down desired music pieces in a certain range such as a play list set by the user and play back the chosen music pieces, or a shuffle playback function to play back music pieces in a sequence which differs each time they are played back.
Heretofore, a mechanism with a dial-type operation element for easily selecting and deciding on contents to be played back and a playback function in a contents playback apparatus has been disclosed in Japanese Patent Laid-open No. 2003-84902.
The mechanism with the dial-type operation element for selecting contents to be played back includes an electronic switch disposed in a casing. The operation of the operation element that is manipulated by the user is mechanically transmitted to the electronic switch. Therefore, a certain link mechanism needs to be provided between the operation member and the electronic switch. However, the link mechanism presents an obstacle to efforts to reduce the size of the casing and also to efforts to effectively utilize the space in the casing. Another problem is that as the link mechanism is provided between the operation member and the electronic switch in the casing, the casing needs to have a hole defined in a wall thereof for passage of the link mechanism therethrough, and hence cannot be made sufficiently water-resistant.


Electronic devices and systems can include various sub-elements that can receive individualized input power. This input power can be applied or removed as-needed, such as to perform within low power architectures that place various components into low-power or off modes when not in use. Individual portions of microprocessors or system-on-a-chip (SoC) devices can also include separate power domains that can be powered on and off independently of each other. These techniques can be referred to as power gating, and are often employed to conserve power in electronic devices, such as in computers, handheld devices, smartphones, gaming systems, and the like.


Reflectors for use with LED light sources typically are constructed from conductive, reflective materials, such as aluminum or vacuum metalized substrates. A number of disadvantages exist when using reflectors of this type. For instance, the use of conductive materials in the entire reflector generally requires that an isolation gap be maintained between the reflector and LED light source. The isolation gap required is based on a minimum creepage distance to protect against electric discharges on or close to an insulation surface and a minimum clearance distance to prevent dielectric breakdown between conductive parts by the ionization of air. This requirement for the isolation gap results in a reflector that is too far from the LED light source. The resultant gap reduces the ability to control light being emitted from the light source as efficiently and effectively, as some light is typically lost along the gap. In addition, in instances where the reflector needs to be easily and quickly replaced, the coaxial orientation and position of the reflector must be maintained after the reflector is replaced so that the beam control and light distribution is not affected.
In the case of metalized reflectors, these reflectors can include a plastic piece that is injection molded, and then metalized with a conductive material to achieve a reflective surface. A coating, such as a lacquer coating, must be applied to the metalized surface thereafter to protect the metallization. However, the coating generally degrades over time and the reflectivity diminishes as a result. In general, as the coating degrades, the color accuracy and total system efficiency is impacted. In addition, these metalized reflectors are conductive.


Papaya (Carica papaya L.) is an important tropical fruit crop with a yielding potential of approximately 45 tons/hectare, which is normally consumed fresh and is valued as a health food because it is rich in vitamins C and A. Papaya is widely grown in Brazil, Australia, South Africa, South-East Asia, Hawaii, India and other tropical areas. Papaya is a polygamous species, and sex inheritance is controlled by a single locus with multiple alleles. There are three sex forms of papaya trees, i.e. hermaphrodite or bisexual, pistillate or female, and staminate or male. The sex types of papaya may not be identified according to the phenotype of the juvenile plant or other chemical or biochemical methods. The male, female and hermaphroditic flowers of papaya are distributed on separate papaya plants and sex types are revealed only after flowering. Methods to identify sex type at juvenile stage have been studied (Bojappa and Singh 1974, Choudhri et al. 1957, Parasnis et al. 1999, 2000; Singh et al. 1977, Sondur et al. 1996, Somsri et al. 1998). Storey proposed that the sex of papaya is determined by three homologous gene complexes on sex chromosome (W. B. Storey, J. Hered. 44, 70–78, 1953; and W. B. Storey, Crop Plants, 21–24. Wisley, N.Y.). The genes are so tightly linked that no crossing over occurs among them; thus the complexes are transmitted to offspring as if they are single gene alleles with pleiotrophic effects on phenotypic expression. The genotypes of the male, hermaphroditic and female plants are M1m, M2m, and mm, respectively. Genotypes with homozygous dominant alleles are lethal (W. B. Storey, J. Hered. 44, 70–78, 1953).
The hermaphroditic papaya, bearing perfect flowers and producing fruits shaped from long-cylindrical to ellipsoidal, is preferred by the markets in Hawaii, Japan, South-East Asia and Taiwan. In addition, the consumers and farmers prefer hermaphrodite papaya because it has small seed cavity and is easier to package. The cross between two hermaphroditic papayas will yield a ratio of 2:1 hermaphrodite to female papaya. Therefore, the papaya growers usually plant at least two seedlings in each hole in the field, and later remove the females at flowering, a practice that is time-consuming and wasteful. Therefore, there is a need to develop a technology of obtaining all hermaphrodite papaya.


The present invention relates to devices for selecting numbers or combinations of numbers in games of chance.
Games of chance, wherein the players choose their own number or combinations of numbers, have become increasingly popular over the past few years. Governments, in order to increase revenue, frequently operate this type of game or lottery. The player receives a ticket with his selected number combination and the operator chooses a winning number on a weekly, daily or other basis. If the player's selected number combination matches the winning number, the player is a winner.
Some prizes in State lotteries have reached astronomical proportions. For example, one lottery winner was recently awarded over 16 million dollars. To cash in on this opportunity, players often select several combinations for one drawing. To do this, unprepared players often have to make a large number of selections in a relatively short time--that time being when the operator says, "Next! And what is your number?"
Players typically use various mathematical formulas or special numbers associated with birthdays, anniversaries and other meaningful dates. However, sometimes players lose faith in their numbers and look for any crutch or sign to assist them in winning.
Some devices have been previously developed which would allow random selection of combinations of numbers. Most of these selectors are hand-held and most are hand-agitated. Typically, an enclosed reservoir or chamber of number indicators, usually small numbered balls, is agitated or shaken by the player to insure a random array of the number indicators. Then the player opens a gate or slide which permits the number indicators to leave the holding reservoir or chamber to be physically withdrawn from the device or to be viewed within a display section of the device.
While such devices can select random number combinations relatively easily, none have gained widespread acceptance. One reason is that, although the devices are easily portable, lottery players rarely bring an apparatus to the site of the number combination selection. Additionally, these prior devices would be impractical if they were offered at the lottery "store" because their hand operation renders them subject to rapid wear or abuse, especially when their numbered balls have to be plucked and held by a user.
Accordingly, it is the primary object of the present invention to provide an improved number-combination selector which randomly selects number combinations from a closed reservoir or chamber without having to be hand agitated to produce the combinations.
It is another object to provide a lightweight, portable number-combination selector, wherein the number indicators are selected and stored for display in a clear sealed chute and then returned to the storage or agitation chamber without being touched by the player.
It is yet another object to provide a number-combination selector which is commensurate with the above-listed objects and comprises an adaptor hood that fits over a standard, underlying bingo-ball blower.
It is a still further object to provide a number-combination selector which is easily amenable to being operated as a commercial vending machine, wherein the player inserts a coin to start the device for a specific time period during which the player selects the combinations.
The above and other objects and advantages of this invention will become more readily apparent when the following description is read in conjunction with the accompanying drawings.


The present invention relates to a display device having a scale.
Display devices in round shape are already known in which a rotating pointer marks the values to be indicated
Furthermore, digital display devices are known in which the value to be indicated is represented by a sequence of digits.
It has been found that an indication in the form of an analog pointer means has the advantage over said digital means that it can be immediately noted visually by the user. Analog pointer means in the form of a rotating pointer have, however, the disadvantage that a substantially round dial must be selected for the direct visual perception of the value indicated.
The object of the present invention is, therefore, to provide a display device which has the advantages of an analog visual indication, with which the value indicated can be read conveniently even in the case of scales having smaller dimensions.


1. Field of the Invention
This invention relates to the air slide delivery of powders of all types and to the transport of particulate matter by a gas.
2. Description of the Prior Art
Air slide systems with filters to remove transport air from the vessel to which the particulate matter is delivered are old. These systems often require costly "bag house" filters to handle the large volumes of transport air involved.


1. Field of the Invention
The invention relates to a diffractive optical element having a multiplicity of binary blazed diffraction structures. The diffractive optical element is particularly intended for use in microlithographic projection exposure apparatus.
2. Description of the Prior Art
Conventional blazed gratings have diffraction structures of triangular, in particular sawtoothed cross section which extend mutually parallel with a spacing equal to the grating constant g. One edge of the diffraction structures, the blaze edge, has an inclination with respect to the base surface of the grating such that the reflection or refraction law is satisfied for one diffraction order of the incident light, and the majority of the intensity of the diffracted light is therefore contained in the order favoured by the blaze edge. The traditional method of producing such blazed gratings consisted in scratching the diffraction structures in a master grating with the aid of diamonds and making corresponding copies of this master grating. This mechanical method is highly elaborate, on the one hand, and on the other hand it encounters limitations with very short wavelengths of the light for which the grating is intended to be used, since the structures to be produced are too small.
Efforts have therefore been made to employ the process technology used for the production of semiconductor components, in which a substrate is coated with photoresist, exposed, subsequently developed and etched, in order to produce the diffraction structures of blazed gratings. The approach firstly involved using successions of such process cycles to achieve diffraction structures which are supposed to approximate the blaze edge by a stepped edge. If four such steps are used, for example, then diffraction efficiencies of more than 80% can be achieved in the first order. With a further process cycle, eight stages are obtained by which a first-order diffraction efficiency of about 95% can be achieved. In general, 2n steps can be produced by using n process cycles. With increasing n, the stepped profile of the edge becomes closer and closer to the sawtooth profile of ideal blazed gratings in conventional, mechanically produced gratings, the diffraction efficiency of which is 100% in the first order according to scalar theory. The production of such a grating, however, is cost-intensive and error-prone because it is necessary to carry out the process cycle repeatedly.
Attempts have also been undertaken to simulate the blaze profile of the diffraction structures by using binary structures whose dimensions are smaller than the wavelength of the electromagnetic radiation for which the grating was defined. These attempts are based on the fact that light is no longer diffracted at the small substructures, but can only be scattered. This leaves only the zeroth diffraction order which picks up the effect of the substructures merely in the form of a local effective refractive index in phase gratings, or merely in the form of a local shade of grey in amplitude gratings.
A first example of such a binary blazed grating is described in the article by Joseph N. Mait et al. “Diffractive lens fabricated with binary features less than 60 nm”, Optics Letters, 15 Mar. 2000, pages 381 et seqq. The substructure used here is a multiplicity of lines, all of which extend parallel to the diffraction structure and whose spacing is less than the effective wavelength.
The article by Philippe Lalanne et al. “Design and fabrication of blazed binary diffractive elements with sampling periods smaller than the structural cut off”, J. Opt. Soc. Am. A, May 1999, pages 1143 et seqq. describes blazed diffractive elements of the type mentioned in the introduction, in which the diffraction structures are resolved into individual substructures consisting of rectangular or square pillars. Different “fill factors” can be achieved by varying the pillar width for a predetermined pillar spacing, and this corresponds to a local variation of the effective refractive index. As an alternative, the pillars may also be arranged at different spacings with a constant width.
A common feature of all these attempts to produce binary blazed diffractive optical elements is that the substructures are minutely configured and have a very high aspect ratio (structure height to structure width). They are therefore technologically highly elaborate and expensive to produce, and cannot be made with sufficient accuracy.


The present invention relates to fuel vapor vent valves employed in fuel tanks filled with highly volatile fluids such as gasoline or mixtures of gasoline and alcohol and particularly relates to valves employed in motor vehicle fuel tanks.
Currently passenger cars and light truck vehicles employ fuel vapor storage devices connected to the vehicle fuel tank through a float operated valve which controls the flow of vapor in the dome above the liquid fuel level to a storage device. Currently, such valves are required to prevent the escape of liquid fuel in the event of overfilling the tank or angular displacement of the vehicle including rollover conditions.
With the advent of molded plastic fuel tanks, it has been found difficult to provide an economical design for the vent valve and the attachment of the valve to the tank. Heretofore, such vent valves had been installed through an access opening in the tank which requires sealing in a manner sufficient to prevent escape of vapor and permeation of the vapor through the material of the vent valve and the tank wall.
It has been found that the material required to withstand continuous exposure to the liquid fuel and vapor has the propensity to be permeable to the fuel vapor. This problem has been addressed by molding the tank wall of layers of different materials with a vapor impervious barrier layer embedded in the material of the tank wall.
If an access opening is formed in the top of the tank for installation of a vapor vent valve, the vapor barrier continuity is broken and the potential for localized vapor permeation has resulted.
Accordingly, it has been proposed to install the vapor vent valve on the interior of the fuel tank without forming an access opening in the upper wall of the tank.
The aforesaid proposal of mounting a vapor vent valve on the interior of the tank has been complicated by the use of high density polyethylene (HDPE) material for molding of the fuel tank. For economical installation of the vent valve on the inside of the fuel tank, the use of HDPE material for the valve has been required in order to permit securing the valve to the wall of the tank by weldment. However, HDPE material has been found not satisfactory for the structural components of the float operated valve and this has resulted in difficulties in designing and manufacturing a valve for interior installation in the tank.
The present invention provides a unique and novel technique for installing a float operated fuel vapor vent valve inside a fuel tank and securing the valve to the tank wall by weldment. The present invention provides for a cup-shaped or U-shaped attachment member with the valve received therein and recessed below the rim of the attachment member which is secured to the inner surface of the tank wall by weldment. The attachment member secures and retains the valve in the desired position and orientation in the tank. The arrangement of the present invention thus permits the body structure of the valve to be formed of a desired material different from the material of the attachment member which is required to be the same as the tank wall material in order to facilitate attachment by weldment.


1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory cell array in which memory cells each comprising a variable resistance element storing information by the change of an electric resistance are arranged in a row direction and a column direction, and more particularly, to a technique for preventing and suppressing the deterioration of stored data due to the reading operation of the memory cell array.
2. Description of the Related Art
Recently, there has been proposed a variable resistance type of memory element (referred to as the variable resistance element hereinafter) having a two-terminal structure in which a metal oxide is sandwiched by conductors serving as electrodes, and capable of changing its electric resistance reversibly by applying a voltage pulse. Various kinds of variable resistance elements are proposed and disclosed by combining oxide materials and electrode materials (or example, refer to document 1: Japanese Laid-Open Patent Publication No. 2004-087069, document 2: Liu, S. Q. et al., “Electric-pulse-induced reversible Resistance change effect in magnetoresistive films”, Applied Physics Letter, Vol. 76, 2749, in 2000, document 3: Seo, S. et al., “Reproducible Resistance Switching in polycrystalline NiO films”, Applied Physics Letters, Vol. 85, 5655, in 2004, document 4: Sim, H et al., “Resistance-switching characteristics of polycrystalline Nb2O5 for nonvolatile memory application”, IEEE Electron Device letters, Vol. 26, 292, in 2005, document 5: Sawa, A. et al., “Hysteretic current-voltage characteristics and resistance switching at rectifying Ti/Pr0.7Ca0.3MnO3 interface”, Applied Physics Letters, Vol. 85, 4073, in 2004, and document 6: Fujii, T. et al., “Hysteretic current-voltage characteristics and resistance switching at an epitaxial oxide Schottky junction SrRuO3/SrTi0.99Nb0.01O3”, Applied Physics Letters, Vol. 86, 12107, in 2005), and each provides distinctive electric characteristics and varies in operation mechanism. Every variable resistance element uses a reversible resistance changing operation (referred to as the “switching operation” occasionally hereinafter) and can be used as a new nonvolatile semiconductor memory device by relating information to a resistance value and reading the resistance value or a current corresponding the resistance value. Here, the information includes binary digital data, a multilevel digital data, analog data and the like, and the high resistance state and the low resistance state are stored as the binary digital data “1” and “0”, the multilevel digital data can be stored using a middle resistance value between the high resistance state and the low resistance state, or the analog data may be stored.
There can be constituted a nonvolatile semiconductor memory device by forming a memory cell array in which memory cells comprising the variable resistance element and storing information by the change of the electric resistance of the variable resistance element are arranged in a row direction and column direction in a matrix state, and providing a circuit for controlling programming, erasing and reading operation of data for each memory cell of the memory cell array in the vicinity of the memory cell array.
The constitution of the memory cell comprising the variable resistance element includes a case where each memory cell comprises a series circuit consisting of the variable resistance element and a transistor as a cell-access element (1T/1R-type memory cell), a case where each memory cell comprises a series circuit consisting of the variable resistance element and a diode as a cell-access element (1D/1R-type memory cell), a case where each memory cell comprises a variable resistance element only (1R-type memory cell) and the like. The 1T/1R-type memory cell and its memory cell array, for example are disclosed in the document 1 by the applicant of this application (refer to FIG. 1, for example). The 1D/1R-type memory cell, for example is disclosed in Japanese Laid-Open Patent Publication No. 2004-260162 by the applicant of this application (refer to FIG. 1, for example). The 1R-type memory cell, for example is disclosed in Japanese Laid-Open Patent Publication No. 2005-32401 (refer to FIG. 4, for example).
When data is read from the memory cell comprising the variable resistance element, a bias voltage is applied to the variable resistance element to flow a reading current and the resistance value of the variable resistance element is determined by the amount of the current, so that the data is read. Therefore, regardless of the constitution of the memory cell, a predetermined bias voltage is applied to the variable resistance element in the reading operation. When a phenomenon in which the resistance value of the variable resistance element is changed a little by the bias voltage applied at the time of this reading operation (referred to as the “reading disturbance” occasionally hereinafter) is repeated, recorded information could be lost in the worst case. Therefore, it is necessary to reduce the degree and frequency of the reading disturbance as much as possible.
As described above, although there are various kinds of nonvolatile variable resistance element capable of changing the electric resistance reversibly by applying the voltage pulse, the behavior of the reading disturbance in the variable resistance element is not clear.
The inventors have found that in the case where the variable resistance element showing the rectifying characteristics disclosed in the document 5 (Sawa, A. et al.) or the document 6 (Fujii, T. et al.) is used, when a reading voltage whose absolute value is not more than a programming voltage is applied to the variable resistance element continuously, the resistance value of the variable resistance element is changed and the resistance value is considerably changed depending on the polarity of the reading voltage. In addition, the variable resistance element showing the rectifying characteristics denotes that the variable resistance element itself has the rectifying characteristics and does not mean that when the memory cell comprises a series circuit consisting of the variable resistance element and a diode as a cell-access element, the memory cell has the rectifying characteristics.
FIG. 1 shows current-voltage characteristics in a high resistance state and a low resistance state of the variable resistance element disclosed in the document 5 (Sawa, A. et al.) and comprising three layers Ti/Pr0.7Ca0.3MnO3 (PCMO)/SrRuO3 (SRO) manufactured by a similar method to that disclosed in the document 5 (Sawa, A. et al.). An upper electrode is Ti and an applied voltage in FIG. 1 is the potential of the upper electrode based on a lower electrode. Referring to FIG. 1, since a negative bias current when a negative voltage is applied (at the time of negative bias) is larger than a positive bias current when a positive voltage is applied (at the time of positive bias), forward bias is provided for the rectifying characteristics at the time of negative bias while reverse bias is provided for the rectifying characteristics at the time of positive bias. In addition, when the potential of the lower electrode based on the upper electrode is defined as the applied voltage, the above relation is reversed. Furthermore, the forward bias is defined by an applied voltage polarity in which a larger current flows to the variable resistance element.
In addition, according to the current-voltage characteristics shown in FIG. 1, when the current-voltage characteristics in the high resistance state is compared with that in the low resistance state, a current difference is largely provided in both forward bias and reverse bias, so that the high resistance state and the low resistance state can be determined in the reading operation in both forward bias and reverse bias.
However, the inventors of the present invention has found that the degree of the reading disturbance is considerably different between the reading operation in the forward bias (forward reading) and the reading operation in the reverse bias (reverse reading). FIG. 2 shows graphs in which the change in resistance value is plotted with a reading voltage applying time (reading voltage pulse applying number of times) when the forward reading and reverse reading are performed for variable resistance elements in the low resistance state and in the high resistance state. The change in resistance value is shown relatively assuming that the resistance value just after the variable resistance element becomes the low resistance state or high resistance state is set to 1, which denotes that the characteristics becomes undesirable as the resistance value (relative value) becomes far from 1. It can be seen from FIG. 2 that the resistance value change is larger when the reverse reading is performed in the low resistance state than the other case. In addition, since the resistance value in the above reading operation tends to increase, when the same reading operation is continued, the resistance state is changed from the low resistance state to the high resistance state, so that recorded information is lost.
Thus, it is clear from the above experimental result that the reading disturbance phenomenon is such that the data stored in the memory cell, that is, the resistance value is changed with the voltage applying time (number of times for applying a pulse) in the reading operation. Especially, the resistance value of the variable resistance element is considerably changed when the reading operation is performed by applying the reading voltage to the variable resistance element in the low resistance state in the reverse bias, so that when the same reading operation to the same memory cell is repeated, stored data could be completely lost and could not read in the worse case.
Furthermore, since in the case of the memory cell array comprising the 1R-type memory cell, the reading voltage is also applied to the selected memory cell that is not to be read but shares the word line or bit line with the memory cell to be read, the above reading disturbance phenomenon appears more notably, so that it is highly necessary to prevent the reading disturbance phenomenon as compared with the other memory cell types.


Such a mounting device is known from U.S. Pat. No. 3,579,840. Therein, in each case a fixed clamping jaw as well as an adjustable clamping jaw on the opposite side are arranged on a ring-shaped holding device. On the bottom side of the ring-shaped holding device, between the two clamping jaws, a bar-shaped recoil cleat is provided for the engagement in a corresponding continuous transverse groove on a base portion which can be attached to the handgun. By means of the recoil cleat, the forces acting at the time of the firing are absorbed, and as a result an improved precision can be achieved. However, as a result of the continuous transverse grooves, the attachment device is also weakened, and thus the stiffness is affected.


The present invention relates to a thyristor, and more particularly, to a mechanism for accurately positioning its light-sensitive area and trigger guide in registry.
This mechanism is hereunder described with particular reference being made to a light pulse triggered thyristor. A typical example of a conventional light pulse triggered thyristor is shown in cross-section in FIG. 1, wherein a thyristor element 1 has a trigger section or light-receiving area 1ain the center of its upper surface. A reinforcing disk 2 made of a metallic material having a coefficient of thermal expansion close to that of the element 1 is secured to the lower surface thereof. A first electrode unit 3 is pressed against an electrode that is formed to surround the light-receiving area 1a on the upper surface of the element 1. A second electrode unit 4 is pressed against the lower surface of the reinforcing disk 2. An insulating tube 5 for positioning and reinforcing the metal disk 2 is made of a material like alumina ceramic and peripherally surrounds the element 1, the disk 2, and the electrode units 3 and 4. The inside diameter of the insulating tube 5 is slightly larger than the outside diameter of the disk 2. Upper and lower annular metal plate flanges 6 and 7, respectively, are hermetically secured to the upper and lower sides of the insulating tube 5. The inner peripheral surfaces of the flanges 6 and 7 are similarly secured to the outer peripheral surfaces of the electrode units 3 and 4, respectively. A transverse groove 8 is provided in the first electrode unit 3 on the side thereof facing the element 1. Said groove 8 extends radially inward from the outer peripheral surface of the first electrode unit 3 to a point beyond the light-receiving area 1a and is wider in a direction perpendicular to the section of FIG. 1 than the diameter of the light-receiving area 1a. A transverse through-hole 9 is made in an area of the insulating tube 5 corresponding to the groove 8. A light guide 10 for directing external trigger light signals to the light-receiving area 1a comprises a glass rod permitting a high degree of light transmission. The outer peripheral surface of the portion of said guide 10 which is closer to its outside end is sealed to the inner wall of the through-hole 9 so that the inside end of said guide is positioned along the central axis of the insulating tube 5 at a point close to the light-receiving area 1a. Said outside end passes through the transverse groove 8 and the through-hole 9 to extend outside of the insulating tube 5.
In the apparatus of FIG. 1, the outer peripheral surface of the portion of the light guide 10 which is closer to its outside end is sealed to the inner wall of the through-hole 9 in the insulating tube 5 so that the inside end of the guide 10 is positioned along the central axis of the insulating tube 5. The reinforcing metal disk 2 is held in position by being pressed into the insulating tube 5. Therefore, in order for both the inside end of the light guide 10 and the light-receiving area 1a of the element 1 that is secured to the upper surface of the metal disk 2 to be positioned along the central axis of the insulating tube 5, the element 1 must be fixed to the upper surface of the metal disk 2 so that the center of the light-receiving area 1a is positioned on the line that is normal to the center of said upper surface of the metal disk 2. But this is very difficult to achieve and it sometimes occurs that the center of the light-receiving area 1a is not in registry with the line that is normal to the center of the upper surface of the metal disk 2. If this misalignment occurs, the inside end of the light guide 10 becomes offset with respect to the center of the light-receiving area 1a and the amount of light being transmitted from the inside end of the light guide 10 toward the light-receiving area 1a is not sufficient to retain the desired high sensitivity of triggering by light pulses.