The present invention relates to microelectronic packaging of semiconductor chips and, more specifically, to IC flip chip assemblies designed to reduce the structural damage to C4 interconnections due to thermal stress and the CTE mismatch of the chip and the packaging material.
Advances in microelectronics technology tend to develop chips that occupy less physical space while performing more electronic functions. Conventionally, each chip is packaged for use in housings that protect the chip from its environment and provide input/output communication between the chip and external circuitry through sockets or solder connections to a circuit board or the like. Miniaturization results in generating more heat in less physical space, with less structure for transferring heat from the package.
The heat of concern is derived from wiring resistance and active components switching. The temperature of the chip and substrate rises each time the device is turned on and falls each time the device is turned off.
As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion (CTE), the chip and substrate tend to expand and contract by different amounts, a phenomenon known as CTE mismatch. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and printed wiring board (PWB) and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause fatigue of the electrical interconnections. This is especially true for the solder ball of the controlled collapse chip connection, also known as xe2x80x9cC4xe2x80x9d, connections. It is therefore important to mitigate the substantial stress caused by thermal cycling as temperatures within the device change during operation.
One type of semiconductor chip package includes one or more semiconductor chips mounted on a circuitized surface of a substrate (e.g., a ceramic substrate or a plastic composite substrate). Such a semiconductor chip package is usually intended for mounting on a printed circuit card or board. In the case of a ball grid array (BGA) package, the chip carrier includes a second circuitized surface opposite the surface to which the chip is attached. This, in turn, is connected to the printed circuit card or board.
Chip carriers of this type provide a relatively high density of chip connections and are readily achieved by mounting one or more semiconductor chips on the circuitized surface of a chip carrier substrate in the so-called xe2x80x9cflip chipxe2x80x9d configuration.
Flip chip bonding is described by Charles G. Woychik and Richard C. Senger, xe2x80x9cJoining Materials and Processes in Electronic Packagingxe2x80x9d in PRINCIPLES OF ELECTRONIC PACKAGING, by Donald P. Seraphim, Ronald Lasky and Che-Yu Li, McGraw-Hill Book Company, New York, N.Y. (1988), at pages 577 to 619; and by Nicholas G. Koopman, Timothy C. Reiley, and Paul A. Totta, xe2x80x9cChip-To-Package Interconnectionsxe2x80x9d in MICROELECTRONIC PACKAGING HANDBOOK, by Rao R. Tummala and Eugene Rymaszewski, Van Nostrand Reinhold, New York, N.Y. (1988), at pages 361 to 453.
Flip chips are small semiconductor dies having terminations all on one side of the entire face of the die in the form of a pattern of solder pads or bump contacts. These solder bumps are deposited on solder wettable terminals on the chip. Typically, the surface of the chip has been passivated or otherwise treated. In this way the use of a flip chip package allows full population area arrays of I/O. The flip chip derives its name from the practice of flipping or turning the chip over after manufacture, prior to attaching the chip to a matching substrate.
As described by Seraphim et al. and Tummala et al., an electronic circuit contains many individual electronic circuit components: thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components are interconnected to form the circuits. The individual circuits are interconnected to form functional units. Power and signal distribution are performed through these interconnections. The individual functional units require mechanical support and structural protection. The electrical circuits require electrical energy to function and the removal of thermal energy to remain functional. Microelectronic packages such as chips, modules, circuit cards, circuit boards, and combinations thereof are used to protect, house, cool, and interconnect circuit components and circuits.
In the flip chip configuration, the chip or chips are mounted active-side-down on solderable metal pads on the substrate using solder balls, a C4 connection, a gold bump, or a conductive epoxy.
Controlled collapse chip connection in flip chip technology has been successfully used for about 30 years for interconnecting high I/O count and area array solder bumps on the silicon chips to the base ceramic chip carriers (e.g., alumina carriers). In the C4 process, as distinguished from the flip chip process, the solder wettable terminals on the chip are surrounded by ball limiting metallurgy (BLM), and the matching footprint of solder wettable terminals on the card is surrounded by a solder mask. These structures act to limit the flow of molten solder during reflow.
Bonding can be used in an unpackaged configuration known in the art as direct chip attach (DCA): the direct connection of a chip to a card or board without an intermediate layer of packaging. The combination of a chip mounted on an intermediate carrier is usually described as the xe2x80x9cfirst level packagexe2x80x9d. DCA can be a lower cost method of connecting a chip to a card, since the first level package is thereby eliminated.
For direct chip attach, individual IC chips are mounted on the cards or boards. The space between the mounted chip and the card or board is then filled with an epoxy resin. By this expedient, the standoff between the IC chip and the card or board is encapsulated with epoxy.
If a polymeric dielectric card or board is employed, the DCA process requires low temperature solder metallurgy. Moreover, direct chip attach, when used with an underfill, increases the fatigue resistance of the C4 solder interconnections to thermal cycling, acts as an alpha emission barrier to MOSFET memory chips, is a parallel thermal path for heat dissipation, and provides physical protection to the chips and C4 solder interconnections.
However, one problem encountered with the combination of DCA and C4 bonding is the difficulty of reworking the encapsulated package. In order to improve rework and to accommodate the CTE mismatches between the chip and the PWB, many prior art proposals have been developed to connect integrated circuit chips to printed wiring boards via an intermediate element. Often, chip carriers are interposed between the chip and the circuit board; the CTE of the chip carrier is itself chosen as some intermediate value to provide a reasonable match to both the chip and to the printed circuit board. The very large difference in CTE between the silicon device and the printed circuit board generally requires some intermediate device carrier. One such type of interconnection mounts the integrated circuit chip on a ceramic chip carrier or module, which module is mounted on a circuit board. One or more chips may be mounted on each device carrier or module, and one or more modules may be mounted on any given circuit board. In a particularly well known type of configuration, the integrated circuit chip is mounted onto a ceramic module by flip chip bonding wherein the I/O pads on the face of the chip are bonded to corresponding pads on the module. Such connections are formed by solder bumps or solder balls normally using solder reflow techniques. It is these connections that are referred to as C4 connections.
Most conventional single and multiple chip packages are typically constructed from thick, mechanically robust, dielectric materials, such as ceramics (e.g., alumina, aluminum nitride, beryllium oxide, cordierite, and mullite) and reinforced organic laminates (e.g., epoxies with woven glass, polyimides with woven glass, and cyanate ester with woven glass). In some cases, materials are combined to produce certain improved properties. For example, a package may have a ceramic base with one or several thin films of polyimides or benzocyclobutane (BCB) disposed thereupon.
In an attempt to overcome the problem of thermal mismatch between the chip carrier and the circuit board it has been proposed to fashion the chip carrier from a material similar to that of the circuit board. Such techniques are described in IBM Technical Disclosure Bulletin Vol. 33, No. 2, pages 15-16 and IBM Technical Disclosure Bulletin Vol. 10, No. 12, pages 1977-1978. However, both of these references require that the connections, at least for the signal I/O lines, be on the same side of the carrier as that to which the chip is mounted. These techniques do solve the problem of thermal mismatch between the chip carrier and the circuit board, but require peripheral I/O bonding and an additional interposer between the chip and the chip carrier. IBM Technical Disclosure Bulletin Vol. 10, No. 12 requires peripheral attachment of the chip to an interposer (carrier 2) which is bonded to the chip carrier and then attached to the card. This peripheral bonding on the chip limits the I/O that can be placed on a small chip.
As noted above, whether the chip is attached to a carrier or directly to the PWB, these structures are made of materials with coefficients of thermal expansion that differ from the CTE of the material of the semiconductor device: silicon. Normally the device is formed of monocrystalline silicon with a coefficient of thermal expansion of 2.5-3.0 ppm/xc2x0 C. If the substrate is formed of a ceramic material, typically alumina with a coefficient of expansion of 5.5-6.5 ppm/xc2x0 C., then the mismatch in thermal expansion is relatively small. The problem is exacerbated with less expensive substrate materials, such as fiberglass, that have a CTE of roughly 17 ppm/xc2x0 C.
The stress on solder bonds during operation is approximately proportional to (1) the magnitude of the temperature fluctuations, (2) the distance of an individual bond from the neutral or central point (DNP), and (3) the difference in the coefficients of expansion of the material of the semiconductor device and the substrate. Stress is also inversely proportional to the height of the solder bond (i.e., the spacing between the device and the support substrate). The seriousness of the situation is further compounded by the fact that, as the solder terminals become smaller in diameter in order to accommodate the need for greater density, the overall height decreases.
In order to strengthen solder joints without affecting the electrical connection, the gap is filled with a polymeric encapsulant, typically a filled polymer. The encapsulant is typically applied after the solder bumps are reflowed to bond the integrated circuit die to the printed circuit board. A polymeric precursor is dispensed onto the board adjacent the die and is drawn into the gap by capillary action. The precursor is then heated and cured to form the encapsulant. This curing can also create stresses that can be detrimental to the die.
An improved solder interconnection structure with increased fatigue life was disclosed in U.S. Pat. No. 4,604,644 to Beckham, et al., assigned to the present assignee, disclosure of which is hereby incorporated by reference. The Beckham patent discloses a structure for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections. Each solder connection is joined to a solder wettable pad on the device and to a corresponding solder wettable pad on the support substrate. Dielectric organic material is disposed between the peripheral area of the device and the facing area of the substrate. The material surrounds at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of dielectric organic material.
Other prior art solutions make use of an underfill material disposed between the chip and the supporting substrate in an attempt to redistribute the stress caused by CTE mismatch. Without the underfill material, this stress is wholly borne by the solder balls. The underfill material allows this stress to be more uniformly spread out over the entire surface of the chip, supporting substrate and solder balls. Examples of the use of underfill materials may be found in U.S. Pat. Nos. 5,194,930, 5,203,076, and 5,249,101.
After soldering the IC to the substrate, an epoxy resin or other material is inserted into the space between the IC and the substrate and acts as a glue. In addition to being inserted into the space, surface tension produces a capillary action between the IC and the substrate that pulls the epoxy into the space. The epoxy is also pulled up along the sides of the IC by the surface tension. To make the mechanical bond of the epoxy even stronger, it is possible to roughen the surface of the substrate or the IC, chemically for instance, before applying the epoxy underfill.
An epoxy, after being introduced under capillary action into a space provided between the semiconductor chip and the package substrate, is cured and hardened. The hardened epoxy acts to bond the semiconductor chip to the package substrate and to protect the fragile solder connections.
The normal flow in a flip chip attach process is as follows: a) the die is fluxed; b) the die is placed on the substrate with bond pads on the die being aligned with bond pads on the substrate; c) solder is reflowed between bond pads on the die and substrate; d) the die is underfilled with a thermoset material; and e) the underfill material is fully cured.
Underfilling ensures minimum load on the interconnects and becomes the primary load bearing member between the chip and the substrate during thermal or power cycling induced due to the operation of the chip. Thermoset type materials are commonly used in the industry as underfill material. In order for the epoxy to bear much of the load it must be relatively rigid. As a result the chip and substrate are strongly coupled so that differential thermal expansion causes bending of the package when the temperature varies from that at which the epoxy was cured. In extreme cases this bending can cause cracking of the chip but, with proper design, this problem may be overcome. Without the epoxy this differential expansion causes shear in the C4 solder joints but little package bending. Warpage tends to be smaller when thicker organic substrates are used and greater as the rigidity and thickness of the substrate decreases.
Accordingly, it is a general object of the present invention to provide novel and useful semiconductor devices wherein the foregoing problems are mitigated.
One specific object of the present invention is to provide a package for the semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on the chip-to-substrate or chip-to-card interconnections.
Another object of the present invention is to provide a package that can be readily modified to changes in chip size and configuration.
Another object of the present invention is to design a package that allows adhesive or underfill to be applied after the package has been assembled.
In accordance with the present invention, there is provided an electrical package that includes a substrate with an upper surface, having at least one electrical circuitry connecting pad. An electric device is also provided with a first modulus of elasticity. The electric device has a connection region on its lower major surface. At least one flexible connector links the connecting pad(s) to the connection region. A collar is also provided with a second modulus of elasticity. The vertical side or dimension of the collar is shorter than the electric device perimeter and is bonded to the perimeter. The horizontal side or dimension of the collar is bonded to the substrate upper surface. The adhesive material has a third modulus of elasticity. Thus, a unitary electrical package is formed that includes the electric device, the substrate and the collar. The second modulus of elasticity is at least as large as the third module of elasticity.


Current child-sized toy vehicles come in a variety of different models, which are typically targeted to children of different age ranges. For example, a foot-to-floor toy vehicle is a model which is typically intended for children in the age range of 12-36 months. Foot-to-floor vehicles are propelled when a child, seated on the vehicle, pushes his or her foot against the ground. A pedal toy vehicle is a model which is typically intended for children in the age range of 2-7 years. Pedal vehicles are powered by manually rotating foot pedals which are attached to a transmission unit attached to the axle of the vehicle. An electric toy vehicle is a model which is typically intended for children in the age range of 3-7 years. Electric vehicles are powered by activating an electronic transmission unit which rotates an axle of the vehicle. A gas-powered toy vehicle is a model which is typically intended for children in the age range of 6-11 years. Gas-powered toy vehicles are powered by a gas powered transmission unit which rotates an axle of the vehicle.
Each of the above described models can be produced in a variety of different sizes, shapes, colors and body styles. For example, some toy vehicle makers have produced toy vehicles which resemble various different body styles, such as sports cars, trucks or Jeeps®. However, these toy vehicles do not allow for the interchangeability of body styles, such that one toy vehicle can be assembled, for example with sports car components and later disassembled and replaced with truck components, or assembled as a hybrid vehicle, for instance, having a sports car front end and engine, but a truck rear end and tires.
Children in the intended age range of these toy vehicles can have short attention spans and become bored with individual toys rather quickly. As a result, producing a toy vehicle having interchangeable body styles allows a child to use his or her own creative abilities to transform the toy vehicle according to the child's whimsical desires.
Consequently, an improved child-sized toy vehicle is needed to address the problems of the prior art.


The inventions described below relate to the field inflatable liners for shoes and boots, and their method of manufacture. More specifically, the invention relates to unique removable snowboard boot liners made from Ethyl Vinyl Acetate (EVA) containing an air bladder and their method of manufacture.
While removable liners present many advantages, one major disadvantage associated with removable liners is that the foot of an athlete wearing a snowboard boot with a removable liner has a tendency to slip and move within the boot. This slipping may be caused by the athlete""s foot moving within the liner, by the lliner moving within the boot, or by a combination of these two phenomena. The most common result of this slipping is that the heal of the athlete lifts up from the bed of the boot. This slipping and lifting makes it more difficult for the athlete to control the snowboard, results in blisters and increases the likelihood of more serious injuries to the athlete.
This slipping problem has been found in the context of ski boots. Multiple solutions to this problem in the field of ski boots have been presented including several variations on the theme of using an air bladder positioned at various locations between the foot of the athlete and the exterior of the boot. Air bladders also have been used in other types of footwear for various purposes.
This invention is specifically concerned with snowboard boot liners made of EVA having an inflatable air bladder incorporated therein and the mass production of such liners.
Holstine, U.S. Pat. No. 5,692,321 discloses an athletic boot such as a snowboard boot having a bladder system consisting of an upper and lower bladder in communication with each other disposed between the wearer""s foot and the exterior of the boot. The upper and lower bladder system is a closed system. Thus, the overall inflation level of the bladder system is fixed and may not be readily adjusted. The system disclosed in Holstine is designed to give increased support to the ankle of a wearer when downward forces compress the lower bladder causing a corresponding inflation of the upper bladder. Holstine stresses that the disclosed boot provides the athlete with increased flexibility and range of motion of the athlete""s foot when impact or operational forces are removed from the boot. Holstine does not disclose how his boot is to be produced.
Potter, et al., U.S. Pat. No. 5,765,298 discloses an athletic shoe with an inflatable bladder present in the ankle collar The bladder has weld fines or other means incorporated therein to prevent the formation of restrictive vertical columns of pressurized gas in the medial and lateral section of the bladder. This allows increased flexibility and mobility of the wearer""s ankle. Potter, et al. do not disclose how their product is to be produced.
Nishimura U.S. Pat. Nos. 3,744,159 and 3,758,964 disclose sports shoes containing an inflatable air bladder. The majority of Nishimura""s disclosures focus on ski boots containing inflatable air bladders. Nishimura does not disclose the methods used to manufacture his products. Nor does Nishimura disclose the use of EVA as a liner material.
None of the foregoing prior art have suggested snowboard boot liners made of EVA having an inflatable air bladder incorporated therein and the mass production of such liners.
The present invention is directed to snowboard boot liners made of EVA having an inflatable air bladder incorporated therein and the mass production of such liners.
The steps involved in making a conventional snowboard boot liner from EVA are as follows:
1. The pattern of the liner must be cut from a flat sheet of EVA;
2. The EVA is then folded and stitched together to approximate the shape of the final liner;
3. The stitched EVA is placed on a last;
4. The stitched EVA on the last is heated to allow the EVA to be molded to its final shape; and
5. The heated EVA is molded to its final shape.
The method outlined above is well known to those in the art. The length of time and temperature used to heat the EVA in step 4 is well known to those ordinarily skilled in the art of making snowboard boot liners from EVA. However, for purposes of illustrative example, the heating may be accomplished in a tunnel oven set at about 100xc2x0 C. The total residence time in the tunnel oven may be approximately five minutes. The exact methods used to accomplish the molding of the EVA to its final shape in step 5 are well known to those of ordinary skill in the art of making snowboard boot liners from EVA. However, for purposes of illustrative example, neoprene socks may be used.
Air bladders in shoes generally are made by placing one sheet of suitable material on top of a second sheet of suitable material, cutting out the material in the appropriate pattern and securing the sheets together to form the boundary of the bladder and any desired internal contours such as uninflated spaces to accommodate the ankle bones. Frequently the two sheets are attached together by melting both sheets together wherever a seam is desired.
The method of the invention allows the air bladder to be stitched into place on the EVA liner before the EVA is stitched and molded. This allows the air bladder to be stitched when the liner is still a flat sheet of EVA. It would be extremely difficult, if not impossible, to attach the air bladder by machine stitching once the EVA has been folded, stitched, heated and molded. Prior to the invention of the method described in this patent, it was not possible to attach an air bladder made from typical materials known in the art of footwear air bladders prior to the heating and molding of the EVA. This is because the two sheets that make up the air bladder would melt together when the bladder went through the heating and molding process with the EVA-Thus, the bladder could not be inflated and would be useless. This made the mass production of EVA snowboard boot liners with inflatable bladders impractical.
The present method solves this problem by introducing a substance between the two sheets that make up the air bladder prior to the sealing of the seams of the bladder and partially inflating the air bladder prior to the heating and molding of the EVA liner. The introduction of this substance and partial inflation of the bladder keep the two sheets that make up the bladder separated during the heating and molding of the EVA. In addition, the disclosed design and installation of the bladder minimizes the amount of slipping of the athlete""s foot within the liner and minimizes the amount of lifting of the athlete""s heal from the bed of the boot.


The present invention relates to an positive yarn feeding device, and more particularly to an positive yarn feeding device in which the operation speed can be optionally adjusted and the yarns with different colors can be easily interchanged.
An positive yarn feeding device is developed for knitting colorful cloth from various colors of yarns. The early positive yarn feeding device employs electromagnetically controlled measures in the yarn feeding operation. For example, Taiwan Invention Patent Application No. 7113777 discloses a yarn feeding device for optionally feeding several yarns to a horizontal yarn knitting machine. In such device multiple sensors 7A-7D, D1/T1, D2/T2, D3/T3, D4/T4, etc. for detecting the position of the yarn guiding arms, and multiple relays CR, timers TC, TD1, TD2 and quite complicated logic control circuit are necessary to form the device.. Therefore, the cost thereof is very high and cannot be accepted in the market. Moreover in the site of the knitting machine, the fluffs always suspend in the air and attach to the device so that the logic circuit cannot work stably. Above all, once the contacts of the relays' circuit and timer are jammed with fluffs, the work thereof will fail and the whole control circuit will malfunction.
Taiwan Utility Model Patent Application No. 7223942 discloses a positive yarn feeding device for a knitting machine which improves the above technical problem, in which when the knitting machine needs yarns in knitting operation, the tension of the yarn is increased and when the tension is greater than a preset value of the yarn feeding device, the yarn on the yarn feeding roller is pulled by a movable yarn guiding arm to contact with the frictional yarn feeding surface of the yarn feeding wheel so as to achieve the object of positive yarn feeding. Such structure is simple and practical. However, recently the knitting market tends to develop the knitting technique of multiple colors and twin yarn feeders so as to achieve various colors and figures of the product. When it is desired to produce two colors or three colors of alternately knitted cloth, two or three layers of yarn feeding wheels are necessary to be vertically piled for meeting the factory technical requirement. As shown in FIG. 9, the movable yarn guide 45 and the tension control means are disposed right under the yarn feeding wheels 17, 18 and the drive pully 16. Accordingly, when two colors or four colors of yarns are fed under the same yarn feeding wheel at the same time for knitting a cloth with colorful stripes, two or over two layers of yarn feeding wheels will be needed. This greatly increases the height of the space for the operation and causes difficulty in yarn threading and connecting processes. Moreover, when controlling or adjusting the speed, such height is always far beyond the head of an operator and thus causes great inconvenience. In addition, multiple yarns are parallelly disposed and tend to interfere with one another. In case there are three or more than three layers of yarn feeding wheels, the errors in operation will take place even more frequently. Above all, when the feeding speed of the yarn feeding wheels on the same layer cannot meet the knitting requirement and the yarn needs to be guided to the more upward or more downward layer of yarn feeding wheel, the yarn must be first torn off and then the yarn connecting and threading processes can be performed. Accordingly, the knitting changing operation will be quite time-costing and labor-costing. Besides, in such a yarn feeding operation, the main yarn feeding technique is such that whether the yarn feeding operation should be performed is decided by the effect of the frictional outer periphery of the yarn feeding wheel and the necessary tension of the yarn. However, when the yarn feeding wheel does not feed the yarn, as shown in FIG. 10, the yarn 76 still contacts with the frictional periphery of the yarn feeding wheel by at least 90 degree contacting angle. If the frictional coefficient of the yarn feeding wheel is too great, mistakes in operation will take place. The mistake which occurs most often is that when the yarn is not needed and the contacting angle between the yarn 76 and the frictional periphery of the yarn feeding wheel is considerably large, the yarn will be still fed to cause negative yarn feeding phenomenon. Therefore, the space between the stripes of the knitted cloth will be irregular or the stripes will be oblique. While the fixed yarn guiding arm 25 is adjustable as shown in FIG. 11 to minimize the contacting angle between the yarn 76 and the periphery of the yarn feeding wheel 17 or maximize the contacting angle to be over 180 degrees when positively feeding the yarn, because the yarn guiding arm 25 of the yarn feeding wheel is disposed above the yarn feeding wheel, when the number of the yarn feeding wheel is over 120, it is very difficult or even impossible to adjust the yarn feeding wheels one by one. In addition, in two color or three color knitting operation, it will be quite difficult to operate or adjust the second or third layer wheel since the height thereof will be unreachable. Therefore, the fixed arm 25 in fact is unable to meet the requirement of the present knitting market.
Moreover, if the yarn feeding wheels have the same operation speed for multicolor knitting operation, although the wheels can be disposed on the same level, the space between the wheels will be too small to operate the yarn. This will affect the time for changing the knitting operation and the amount of the products or even indirectly cause failure of the device. If the currently most popular elastic rubber yarn or metal yarn is to be mixed with the general yarns, because the space is limited, such mixing process cannot be accomplished. Therefore, the pattern of the produced cloth will not satisfy the present market requirement. In case each yarn feeding wheel feeds two yarns at the same time barely, since the yarn guiding eye thereof has only one single eyelet, although the tension of the yarn can separate the adjacent two yarns when the yarns are fed, once the yarn feeding operation is stopped and the tension of the yarn disappears, the adjacent two or three yarns will twist with one another due to the self-twisting property thereof. Therefore, when the device is again activated, the failure thereof will inevitably occur. Therefore, the yarn feeding wheel can feed only one single yarn.


The present disclosure generally relates to a rearview device system, and more particularly, to a display mirror assembly having a partially reflective, partially transmissive element and a display behind the reflective element.


U.S. Pat. No. 4,836,767 (Schad) relates to an apparatus for producing molded plastic articles which is capable of simultaneously producing and cooling the plastic articles. The apparatus has a stationary mold half having at least one cavity, at least two mating mold portions, each having at least one core element, mounted to a movable carrier plate which aligns a first one of the mating mold portions with the stationary mold half and positions a second of the mating mold portions in a cooling position, a device for cooling the molded plastic article(s) when in the cooling position, and a device for moving the carrier plate along a first axis so that the aligned mold portion abuts the stationary mold half and the second mating mold portion simultaneously brings each plastic article(s) thereon into contact with the cooling device. The carrier plate is also rotatable about an axis parallel to the first axis to permit different ones of the mating mold portions to assume the aligned position during different molding cycles.
U.S. Pat. No. 6,299,431 (Neter) discloses a rotary cooling station to be used in conjunction with a high output injection molding machine and a robot having a take-out plate. A high speed robot transfers warm preforms onto a separate rotary cooling station where they are retained and internally cooled by specialized cores. The preforms may also be simultaneously cooled from the outside to speed up the cooling rate and thus avoid the formation of crystallinity zones. Solutions for the retention and ejection of the cooled preforms are described. The rotary cooling station of the present invention may be used to cool molded articles made of a single material or multiple materials.
U.S. Pat. No. 6,391,244 (Chen) discloses a take-out device for use with a machine for injection molding plastic articles such as PET preforms. The take-out device has a plurality of cooling tubes that receive hot preforms from the molding machine, carry them to a position remote from the molds of the machine for cooling, and then eject the cooled preforms onto a conveyor or other handling apparatus. The preforms are retained within the cooling tubes by vacuum pressure, but are then ejected by positive air pressure. A retaining plate spaced slightly outwardly beyond the outer ends of the cooling tubes is shiftable into a closed position in which it momentarily blocks ejection of the preforms during the application positive air pressure, yet allows them to be dislodged slightly axially outwardly from the tubes. Such slight dislodging movement is inadequate to vent the air system to atmosphere such that sufficient dislodging air pressure remains in tubes where the preforms might otherwise tend to stick and resist ejection. After the momentary delay, the plate is shifted to an open position in which all of the dislodged preforms are freed to be pushed out of the tubes by the air pressure. Preferably, the retaining plate is provided with specially shaped holes having pass-through portions that become aligned with the tubes when the plate is in its open position, and smaller diameter blocking portions that become aligned with the tubes when the plate is in its closed position. The smaller diameter blocking portions exceed the diameter of the neck of the preforms but are smaller in diameter than the flanges of the preforms such that surface areas around the blocking portions overlie the flanges to block ejection of the preforms as they undergo their dislodging movement.
EP Pat. No. 1515829 (Unterlander) relates to a method and apparatus for cooling molded plastic articles after molding is finished. In particular, the disclosed invention relates to method and apparatus for a post mold cooling (“PMC”) device having at least two opposed faces. The method and apparatus are, according to the inventors, particularly well suited for cooling injection molded thermoplastic polyester polymer materials such as polyethylene terephthalate (“PET”) preforms.


Inventive concepts described herein relate to a semiconductor memory device, and more particularly, to a nonvolatile memory device and/or a control method thereof.
Semiconductor memory devices may be characterized as volatile or nonvolatile. A volatile semiconductor memory device may perform read and write operations in a high speed, while data stored therein may be lost upon removal of power from the device. A nonvolatile semiconductor memory device may retain data stored therein even upon removal of power from the device. Accordingly, a nonvolatile semiconductor memory device may be used to store data which must be retained regardless of whether the device is powered.
A flash memory device may be a typical nonvolatile semiconductor memory device. The flash memory device may be used as a voice and image data storing medium for information appliances such as a computer, a cellular phone, a PDA, a digital camera, a camcorder, a voice recorder, an MP3 player, a handheld PC, a game machine, a facsimile, a scanner, a printer, and the like.
In recent years, research has been conducted on nonvolatile memory devices where memory cells are stacked three-dimensionally to improve a degree of integration of the devices. Such a nonvolatile memory device may be referred to as a vertical NAND flash memory device or a three-dimensional nonvolatile memory device. In the three-dimensional nonvolatile memory device, word lines may be stacked in a direction perpendicular to a substrate. Cell strings may be constituted by forming pillars to penetrate the stacked word lines.
The pillars may be disposed in a zigzag shape to improve efficiency of space arrangement. This structure may cause irregular driving characteristics of strings. Thus, a technique of solving such a problem of the three-dimensional nonvolatile memory device is desired.


The present invention relates to a tape-like carrier for mounting of integrated circuit, and more particular to the tape-like carrier used for tape automated bonding in which plural inner leads are automatically bonded to a semiconductor pellet. Further the present invention relates to the tape-like carrier suitable for connection of very multiple terminals of a semiconductor pellet with electronic elements.
Heretofore well known is a longitudinally extending tape-like carrier for mounting of integrated circuit including sets of leads secured to a flexible insulating film having longitudinally spaced apertures which are dimensioned to encompass contact regions of semiconductor pellet, said leads extending from the periphery of the every aperture toward the inside thereof (U.S. Pat. No. 3,689,991).
FIGS. 1 to 2b show one prior illustration of such a tape-like carrier for mounting of integrated circuit, together with a semiconductor pellet having bump electrodes with leads, FIG. 1 being a plan view, FIG. 2a being a cross-sectional view taken on line IIa-IIa of FIG. 1 and FIG. 2b being a cross-sectional view taken on line IIb-IIb of FIG. 1.
With reference to FIGS. 1 to 2b, the conventional tape-like carrier for mounting of integrated circuit comprises a flexible insulating film 5 in the form of tape made of polyimide. The flexible insulating film 5 is provided with sprocket holes 7 at regular intervals along the longitudinal direction in both side regions thereof. Further the flexible insulating film 5 has longitudinally spaced apertures 26 which are dimensioned to encompass contact regions of a semiconductor pellet.
Longitudinally spaced sets of leads 23 and bars 28 in the form of a frame leading to the leads 23 are formed on the flexible insulating film 5. The leads 23 extend within the periphery of a respective aperture 26 for semiconductor pellet. Between the leads 23 and the leads 23 and between the leads 23 and the bars 28, a surface of the flexible insulating film 5 is partially exposed.
Located in the center of the aperture 26 is a semiconductor pellet 1 having plural bump electrodes 2 formed on the contact regions of the pellet 1. The bump electrodes 2 are bonded to the corresponding leads 23 which are arranged at regular intervals so as to be coincident with the bump electrodes 2, by a heat bonding method using a bonding tool, that is, gang bonding.
When bonding of very multiple inner leads 23 with very multiple bumps 2 of the semiconductor pellet is performed using the above tape-like carrier for mounting of an integrated circuit, the heat dissipation characteristic is remarkably worse so that the following inconvenience occurs: i.e., as metal regions which dissipate heat of the leads 23 conducted from the bonding tool are only the surfaces of the bars 28 and the leads 23, the efficiency of heat dissipation is low.
Therefore, when the inner lead bonding is performed by using the above tape-like carrier for mounting the integrated circuit, thermal expansion of the leads 23 and the deformation and contraction of the flexible insulating film 5 occur, which results in the change of pitches between the leads 23. Thereby, an outer lead bonding for mounting the semiconductor pellet 1 to a substrate (not shown) or to an outer lead frame cannot be normally performed in a postprocess, which results in the faulty bonding.


1. Field of the Invention
The present invention relates to a mass spectroscopy spectrum analysis system using a mass spectrometer, and to a system for automatically determining an optimum flow of mass spectroscopy within a measurement time in order to identify the chemical structure of biopolymers, such as polypeptides or sugars, with high precision and efficiency.
2. Background Art
In a general mass spectroscopy, a sample as the object of measurement is ionized, and a variety of resultant ions are delivered to a mass spectrometer for measuring the ion intensity for each mass-to-charge ratio m/z, which is the ratio of the mass number m of ion to the valence z. As a result, a mass spectrum is obtained, which consists of a peak of the measured ion intensity (ion peak) for each mass-to-charge ratio m/z value. Such a mass spectroscopic analysis of the ionized sample in a first dissociation step is called MS1. In tandem mass spectrometer, in which multiple-stage isolation is possible, an ion peak having a specific mass-to-charge ratio m/z is selected (the selected ion species is called a parent ion) from the ion peaks detected by MS1, and the thus selected ion is dissociated and broken up by collision with gas molecules or the like. The resultant dissociated ion species is then subjected to mass spectroscopy, thereby obtaining a mass spectrum in a similar manner. The n-stage dissociation of the parent ion and the subjecting of the dissociated ion species to mass spectroscopy are referred to as MSn+1. Thus, in the tandem mass spectrometer, the parent ion is dissociated in multiple stages (1, 2, . . . , n stages), and the mass number of the ion species generated in each stage is analyzed (MS2, MS3, . . . , MSn+1).
(1) Most of the mass spectrometers capable of tandem analysis are equipped with a data-dependent function whereby, when selecting the parent ion for MS2 analysis from the ion peaks in MS1, the ion peaks are selected in decreasing intensities (such as the ion peaks in the top 10 strongest-intensities) as the parent ions, and then they are subjected to dissociation and mass spectroscopy (MS2).
(2) The ion-trapping type mass spectrometer manufactured by Finningan is equipped with a Dynamic Exclusion function whereby, when selecting a parent ion for MS2 analysis from the ion peaks in MS1, the ion species having a mass-to-charge ratio m/z value that is designated by the user in advance is excluded from the selection as a parent ion.
(3) Known examples relating to the determination of correspondence between a measured ion species and an ion species that has been measured include the following:
Patent Document 1: JP Patent Publication (Kokai) No. 2001-249114 A
Patent Document 2: JP Patent Publication (Kokai) No. 10-142196 A 1998
In Patent Document 1, a characteristic peak in the first-stage spectrum data and the spectrum data in the second stage of the corresponding ion species are stored in a database. In the subsequent measurements, spectrum data obtained by mass spectroscopy in the second stage of a sample as the object of measurement is compared with the second-stage spectrum data in the database in order to determine the degree of correspondence. Data components with the highest degree of correspondence is outputted as the comparison result.
In Patent Document 2, a measurement is continuously carried out during a multiple-stage dissociation measurement without conducting a sample injection process during measurement so that an ion intensity fluctuation due to injection between the MSn and MSn+1 data can be prevented. In this way, the need for the addition of a standard sample can be eliminated, thereby enabling an efficient quantitative analysis. The routine returns to MSn+1 or proceeds to the next MS1 measurement, depending on whether or not the data corresponds to the designated ion data that has been already collected in the MSn and MSn+1 data analysis.
Reviews of Modern Physics, Vol. 62 (1990), pp. 531-540, provides a basic description of an ion trap. A cross section of a basic configuration of the ion trap is shown in FIG. 15. The ion trap, which is a quadrupole ion trap, is made up of two end-cap electrodes and a single ring electrode. An RF voltage is applied to these electrodes such that a quadrupole electric field is formed at the center of these electrodes, thus enabling the trapping of gaseous ions three dimensionally. By continuously varying the RF voltage, the mass of the ions that are discharged can be controlled. A quadrupole pole is made up of four parallel poles. By applying a RF voltage to the electrodes, gaseous ions can be two dimensionally trapped at the center of the electrodes. By controlling the RF voltage that is applied, it becomes possible to discharge ions with a specific mass or, conversely, trap only those ions with a specific mass.
A tandem mass spectroscopy (MS/MS) can be conducted using a quadrupole ion trap, as described in the U.S. Pat. No. Re. 34000. In this apparatus, those ions for which no analysis is required are discharged prior to MS/MS. Namely, the removal of the ions for which no analysis is required is not conducted prior to the primary mass spectroscopy. A RF voltage that resonates with the ions is then applied in order to increase the kinetic energy. As a result of these operations, dissociated ions (fragment ions) are created by the collision induced dissociation (CID) with remaining molecules. By subjecting these fragment ions to mass spectroscopy (tandem mass spectroscopy), the mass of the fragment ions can be determined. In this case, it is necessary to initially conduct a mass spectroscopy without involving a CID (primary mass spectroscopy) in order to determine the ions as the object of a tandem mass spectroscopy (MS/MS, or a secondary mass spectroscopy). It is also possible to repeat a similar operation to further conduct a tandem mass spectroscopy (MSn) on a specific dissociated ion.
Recently, mass spectroscopic methods are often employed for an exhaustive analysis of proteins. Analytical Chemistry, Vol. 73 (2001), pp. 5683-5690, describes examples of analysis called a shotgun analysis. In this technique, a peptide mixture prepared by subjection a protein to enzymatic digestion is separated using a liquid chromatograph, and a separated sample is then subjected to a tandem mass spectroscopy using a quadrupole ion-trap mass spectrometer. With reference to the determined mass of the ion and that of the fragment ion, a database of proteins or genes is searched in order to identify a protein. In case the types of the peptide mixture are too numerous, each peptide might not be completely separated in the liquid chromatograph, and a plurality of kinds of peptides might be simultaneously introduced into the mass spectrometer. This gives rise to the need for automatic tandem analysis called data-dependent analysis. Specifically, the band width of a separated sample separated in a liquid chromatograph is in the order of one minute, and the number of kinds of ions that can be subjected to tandem mass spectrometer at one time is limited to five. In many cases, the ions with greater ion intensities are preferentially subjected to tandem mass spectroscopy, although this depends on the setting of the data-dependent analysis.
A technical material for the quadrupole ion-trap mass spectrometer manufactured by ThermoFinnigan (www.thermo.com/eThermo/CMA/PDFs/Articles/articlesFile—10918.pdf) describes a dynamic exclusion function. Prior to the start of analysis, the masses of those ions to be excluded from tandem mass analysis are entered and then a list is prepared. By this operation, it becomes possible to exclude those ions put on the list as the objects of data-dependent analysis (tandem mass spectrometer). When this function is to be employed, a conventional mass spectroscopy is conducted first without involving the CID, and then the mass of the ions to be detected is determined. Next, priorities of the ions as the objects of tandem mass spectroscopy are determined in the detected ions, whereupon those ions put on the list are excluded from the objects of data-dependent analysis (tandem mass spectroscopy).


The Internet has become a popular place to conduct business. Through Web auction sites, Web sites for displaying classified ads, Web shopping malls, online chat rooms, and other online transaction facilitation sites, two consumers may agree to a transaction. Frequently, such transactions involve the exchange of goods or services for money. While consumers frequently find that agreeing to transactions on the Internet is easy, completing a payment to consummate the transaction is more difficult.
Typically, two consumers who have agreed through the Internet to exchange goods for money resort to offline methods to perform the exchange. For example, the seller may ship the goods to the buyer through a shipping service, and the buyer may send a paper check to the seller.
Such offline methods of exchange are problematic. Because the buyer and the seller are usually strangers, they may not trust each other to perform their mutual obligations under the agreement. Accordingly, they may be unable to agree whether the buyer will send the check first or the seller will send the goods first. Even if the buyer and the seller agree that the seller will ship the goods at the same time as the buyer sends the check, the seller has no guarantee that the check will not bounce. Likewise, the buyer has no guarantee that the goods will arrive in satisfactory condition. Accordingly, a significant percentage of transactions to which an individual buyer and seller have agreed upon over the Internet are never consummated.
Another inconvenience of transactions agreed upon by individuals over the Internet is that the buyer is often limited to paying by cash or paper check. More convenient payment instruments exist, such as credit cards and bank account debits through electronic fund transactions. However, the buyer typically does not have the option to use these other payment instruments when the seller is an individual as opposed to a retail business that has been pre-established as an online merchant.
The term “merchant” is used herein to refer to a seller of goods or services who is authorized by a credit card association (such as DISCOVER, VISA, or MASTERCARD) to submit to the credit card association charges on credit cards belonging to members of the credit card association. After receiving an authorization for the charge, the merchant then receives from the credit card association a direct deposit into the merchant's bank account of the amount of the charge. As known to those skilled in the art, a business must undergo an approval process in order to become a merchant, and upon approval, the merchant is assigned a merchant number.
Although retail businesses are routinely set up as merchants in order to accept payments through credit cards or electronic fund transactions, this is not an adequate solution to facilitating payments between individuals over the Internet. For example, merchants, after undergoing an extensive underwriting effort, are typically given special privileges, such as a general authorization to charge credit cards. This general authorization provides the merchant with the ability to commit fraud. Specifically, the merchant is capable of charging a customer's credit card more than he should. Also, the merchant may submit charges on a credit card belonging to a credit card association member with which the merchant has never had any contact. For these reasons, the idea of allowing individual sellers to become merchants has heretofore been rejected.
Another problem with an individual seller becoming a merchant is that the approval process for becoming a merchant is frequently more of a hassle than an occasional seller is willing to undergo. The purpose of the approval process is to reduce the risk of fraud by the merchant. Accordingly, the seller usually must submit extensive background information for consideration in the approval process. This may be inconvenient and time consuming for the seller.
Therefore, there is a need in the art for a safe and convenient method by which one consumer can pay a second consumer over the Internet.


The broad field of molecular electronics was introduced in the 1970's by Aviram and Ratner. Molecular electronics achieves the ultimate scaling down of electrical circuits by using single molecules as circuit components. Molecular circuits comprising single molecule components can function diversely as switches, rectifiers, actuators and sensors, depending on the nature of the molecule. Of particular interest is the application of such circuits as sensors, where molecular interactions provide a basis for single molecule sensing. In particular, informative current changes could include an increase, or decrease, a pulse, or other time variation in the current.
Notwithstanding the achievements in the field of molecular electronics, new molecular circuits that can function as molecular sensors are still needed. In particular, the need still exists for improved single molecule systems that can yield molecular information with greater signal-to-noise ratios such that signals truly indicative of molecular interactions are distinguishable from non-informative noise.


In conventional DIAMETER networks, there is currently no way for a DIAMETER node, such as a DIAMETER relay node or DIAMETER routing node, to automatically receive information from a peer DIAMETER node indicating which originating hosts or originating realms the peer DIAMETER node should receive particular types of traffic from. Expressed another way, there is currently no mechanism in the DIAMETER specifications that allows a peer DIAMETER node to specify, to a DIAMETER relay or routing node, that when the DIAMETER relay or routing node receives traffic from a particular originating host or originating realm, the traffic should be directed to the peer DIAMETER node. Internet engineering task force (IETF) request for comments (RFCs) 3588 and 3589 are incorporated herein by reference in their entireties. For example, in the event that network operator X signs an agreement with operator Y that all traffic transmitted through hub provider A's network should be routed to operator X's realm, it may be desirable for operator X to automatically notify hub provider A of the agreement between operator X and operator Y so that hub provider A can update its routing tables accordingly.
Currently, in the exemplary scenario described above, hub provider A must manually gather origin-based routing information and update its routing tables. For example, a human user may be required to manually log into a terminal associated with one or more DIAMETER nodes in the hub provider's network and add origin-based rules to the routing tables.
While no method currently exists for automatically notifying and updating the routing tables of a DIAMETER node with origin-based routing information, conventional solutions exist for automatic notification and routing table updating for destination-based routing information. Currently, this is accomplished using the domain name system (DNS). For example, if network operator X wishes to know the networks (i.e., realms or hosts) to which he can route traffic, operator X sends a DNS query to a DNS server that maintains this information. Based on the information included in the DNS response, network operator X (i.e., the DIAMETER node in realm X that initiated the DNS query) may automatically update its routing tables with the destination-based routing information.
As may be appreciated from the above discussion, one drawback to conventional methods for populating or updating routing information in DIAMETER nodes is that automatic routing table population is only available for destination-based routing information. As a result, a corollary drawback of conventional methods is therefore that populating and/or updating routing information for DIAMETER nodes is a manual process that may be slow and prone to error.
Accordingly, in light of these difficulties, a need exists for improved methods, systems, and computer readable media for automatically populating and/or updating routing tables of DIAMETER nodes with origin-based routing information.


A battery pack for an electric car in which a plurality of battery housing parts are defined by disposing a lattice-shaped partition frame on an upper face of a plate-shaped battery frame for the electric car, and a plurality of batteries are mounted in each of the battery housing parts, is known from Patent Document 1.


1. Field of the Invention
The present invention relates to a mobile telecommunications technology, and more particularly, to a technique for receiving and transmitting downlink reference signals. Herein, downlink reference signals for data demodulation are efficiently received and transmitted in a single user mode or a multi-user mode.
2. Discussion of the Related Art
In a mobile telecommunications system, a user equipment (UE) may receive information from a base station through a downlink, and the UE may also transmit information through an uplink. Information transmitted or received by the UE may include data and diverse control information. And, depending upon the type and usage of the information transmitted or received by the UE, a variety of physical channels may exist.
FIG. 1 illustrates a general view showing the physical channels used in a mobile telecommunications system, such as a 3rd generation partnership project (3GPP) long term evolution (LTE) system and a general method for transmitting signals. When power of a UE is turned off and then turned back on, or when using a UE newly introduced to a cell, in step 101, the UE performs an initial cell search process in order to be in synchronization with the base station. In order to do so, the UE receives a primary synchronization channel (P-SCH) and a secondary synchronization channel (S-SCH) from the base station, so as to be in synchronization with the base station, thereby being able to acquire information such as cell ID. Thereafter, the UE receives a physical broadcast channel from the base station, thereby being capable of acquiring broadcast information within the cell. Meanwhile, during an initial cell searching step, the UE receives a downlink reference signal (DL RS), thereby being able to verify the downlink (DL) channel status. After completing the initial cell search, in step 102, the UE may receive a physical downlink control channel (PDCCH) and a physical downlink shared channel (PDSCH) based upon the physical downlink control channel information, so as to acquire more detailed system information.
Meanwhile, in case the UE has not completed its access to the base station, the UE may perform a random access procedure, as shown in step 103 to step 106, in a later process in order to complete its access to the base station. For this, the UE transmits a characteristic sequence as a preamble through a physical random access channel (PRACH) (S103). Then, the UE may receive a response message respective to the random access through the physical downlink control channel (PDCCH) and its corresponding physical downlink shared channel (PDSCH) (S104). Subsequently, with the exception of a handover, in case of a contention-based random access, the UE may perform a contention resolution procedure, such as transmitting additional physical random access channels (PRACHs) (S105) and receiving the respective physical downlink shared channels (PDSCHs) (S106). After performing the above-described procedure, the UE may receive physical downlink control channel (PDCCH)/physical downlink shared channel (PDSCH) (S107) and may transmit physical uplink shared channel (PUSCH)/physical uplink control channel (PUCCH) (S108), as a general uplink/downlink (UL/DL) signal transmission procedure.
FIG. 2 illustrates a block view showing a signal processing procedure for transmitting a downlink signal from a base station. In the 3GPP LTE system, the base station may transmit at least one or more code words via downlink. Each of the at least one or more code words may be processed through a scrambling module 301 and a modulation mapper 302 as a complex symbol. Thereafter, the complex symbol is mapped to multiple layers by a layer mapper 303. Herein, a precoding module 304 multiplies each layer by a selected precoding matrix depending upon the channel status, thereby allocating (or assigning) the processed layers to each transmission antenna. Each transmission signal processed as described above for the respective antenna is mapped to a time-frequency resource element, which is to be used by a resource element mapper 305 for transmission. Subsequently, each of the transmission signals passes through an OFDM signal generator 306 so as to be transmitted through the respective antenna.
Hereinafter, a downlink reference signal that is used in the 3GPP LTE system will be described in detail. The 3GPP LTE system uses antenna number 0 to antenna number 5 as its logical antenna ports. Herein, each antenna port is not divided (or classified) by a physical division (or classification). Therefore, the question of mapping each logical antenna index to which actual physical antenna index would relate to the implementation by each manufacturer.
In the 3GPP LTE system, three different types of reference signals are used as downlink reference signals. The three types include cell-specific reference signals (non-associated with MBSFN transmission), MBSFN reference signals associated with MBSFN transmission, and UE-specific reference signals. A cell-specific reference signal corresponds to a reference signal generated by using a cell ID for each cell as an initial value. Herein, antenna port 0 to antenna port 3 may be used for transmitting the cell-specific reference signals. An MBSFN reference signal is used for acquiring downlink channel information respective to the MBSFN transmission. Herein, antenna port 4 may be used for transmitting the MBSFN reference signal. Meanwhile, in the 3GPP LTE system, a UE-specific reference signal is supported for a single antenna port transmission of the PDSCH. Herein, antenna port 5 may be used for transmitting the UE-specific reference signal. The UE may receive from an upper layer (or higher layer) (e.g., a MAC layer or higher) information on whether such user-specific reference signals exist so as to be used for PDSCH demodulation.
FIG. 3 illustrates an example of a specific reference signal being mapped in a time-frequency resource region and transmitted, when the 3GPP LTE system uses a general cyclic prefix. Referring to FIG. 3, the horizontal axis represents a time region, and the vertical axis represents a frequency region. In the time-frequency region shown in FIG. 3, the smallest squared region corresponds to 1 OFDM symbol in the time region and to 1 subcarrier in the frequency region. In the 3GPP LTE system, when a normal cyclic prefix (CP) is used, one slot includes 7 OFDM symbols, and one sub-frame includes 2 slots. FIG. 3 illustrates a pattern where a UE-specific reference signal being transmitted through antenna port 5 is mapped to the time-frequency region throughout even-numbered slots and odd-numbered slots, thereby being transmitted.


Today, integrated circuit's sensors can require a level of precision which cannot be reached with current ultra large scale integration (ULSI) production techniques.
A conventional solution consists in measuring device deviations with respect to a target value once the wafer manufacturing is complete, and in compensating deviations accordingly via extra processing. Depending on the device type, different solutions are currently in use. For example, digital coding is adopted via fuse concepts with fine-tuning of the electrical characteristics of the product after its final electrical testing at wafer-level. For another example, current sensors are embedded in many ICs to insure constant monitoring and protection of the device during circuit start-up or malfunction. At least some effects of implementing the teaching disclosed herein are as follows: An alternative to conventional laser fuses is provided that enables use of fuses where a conventional laser fuse cannot be used thus opening the processing to a broader range of applications. During wafer processing, techniques that are disclosed herein allow to have chip-selective modifications provided on a wafer, whereby individual chips can be manufactured while using lithography masks designed for production of multiple non-individual chips on a same wafer.
At least some effects associated with the introduction of post-processing printed structures can be as follows: Conventional process technologies can be easily adapted or complemented according to some implementations so as to perform digital coding without necessitating Laser tools. Thus, negative effects typically associated with a use of conventional Laser such as alignment problems can be avoided.


The subject matter of the present application relates to microelectronic assemblies and fabrication methods therefor, and more particularly to the structure of and fabrication method for a multilayer interconnect element.
There is a current need for microelectronic interconnect elements to provide greater wiring density. Microelectronic interconnect elements include, for example, package substrates used for direct interconnection to microelectronic elements such as semiconductor chips. Other types of interconnect elements include circuit panels which can be directly connected to microelectronic elements or indirectly, such as through a package substrate of a packaged chip. The need is felt especially to improve the density of metal wiring lines, e.g., conductive traces on a dielectric element, as measured by the pitch of the metal lines and minimum spacing between adjacent metal lines.
Some package substrates and circuit panels have multiple dielectric layers and metal wiring lines provided on some or all of the dielectric layers. A multi-layer wiring substrate 12 according to the prior art, referred to as “High Density Interconnect” is illustrated in FIGS. 1-2. The substrate 12 has a plurality of dielectric layers, two such dielectric layers 14, and 14′ being shown in FIG. 1. As shown therein, each of a plurality of metal lines 10, 10′ and 10″ has approximately the same width w and thickness t.
One limitation of the substrate shown in FIG. 1 is a vertical distance factor d by which each of the metal lines 10, 10′ and 10″ is spaced from closest adjacent metal lines (of lines 10, 10′ and 10″) in a vertical direction 30, i.e., the direction of the thickness of each metal line. Each of the metal lines 10 and 10′ is supported by a respective dielectric layer 14 or 14′. As illustrated in FIG. 1, the metal lines 10′ and 10″ are separated in a vertical direction 30 of the substrate 12 by a distance d through a portion of the thickness td of the dielectric layer 14′. A minimum vertical spacing constrains the metal wiring density within the volume occupied by metal lines and dielectric layers 14 of the substrate 12. As further shown in FIG. 2, each of a plurality of traces 10″ adjacent to each other in a horizontal direction 40 has width w and is spaced from the adjacent trace 10″ by a spacing s. Thus, a minimum pitch of the traces 10″, measured between the centers of adjacent traces, is the value of w+s. A minimum spacing s is required for manufacturability of the traces. For example, the traces 10″ of FIG. 2 may be formed subtractively by etching a metal layer. In such case, a constraint in the form of a minimum spacing s is imposed by the resolution of the photolithographic exposure process used to define an etch mask, e.g., a photoresist mask, and the need for the etching process to reliably produce separated traces from a metal layer having a given thickness t. In another example, when the traces 10″ of FIG. 2 are formed in an additive manner by electroplating, a minimum spacing s is imposed by the resolution of the photolithographic exposure process used to define a plating mask, e.g., a photoresist mask, the electroplating process used to form the lines, and the requirements of processes employed after the plating process, e.g., photoresist mask removal. Accordingly, in a HDI implementation, the resulting multi-layer substrate 12 has adjacent traces 10″ spaced apart in a horizontal direction 40 of the substrate by a minimum spacing s. Also, a minimum distance d separates traces of adjacent dielectric layers in a vertical direction 30 of the substrate.


This invention generally relates to overhead doors and, more specifically, to an improved tension spring counterbalancing mechanism use in overhead doors, such as residential garage doors.
Overhead doors generally require a counterbalancing force which enables the door to be more easily moved between opened and closed positions either manually or by way of a powered opening device. Often, overhead door systems rely on one or more extension springs, placed in tension when the door is in a closed position, so as to provide the desired counterbalancing force. In tension spring counterbalancing systems, the tension in the spring is released as the door is lifted thereby effectively reducing the weight of the door which must be lifted either by the motor of a door opener or by hand. These extension springs must be stretched or extended during the installation of the overhead door such that they are supplied with the necessary counterbalancing tension.
Presently, the installation of extension spring systems involve labor intensive procedures on the part of the installer. That is, in order for the installer to stretch or extend the spring, the full weight of the overhead door, which may be 200-300 pounds, must be manually lifted and clamped or otherwise propped up in a fully opened position. This procedure usually requires three people, i.e., two people for lifting the door and one more for clamping it in the open position. The operating cable of the door is then attached to the free end of the spring. Since the other end of the spring is fixed, the spring is tensioned when the door is lowered to the closed position. This type of system is not only difficult to install but the door may be inadvertently released from the open position when the spring or springs have not yet been attached to the operating cable. These concerns are amplified by the fact that extension spring systems are often installed by residential homeowners who, in general, are inexperienced with overhead door installation.
Another problem associated with overhead doors utilizing extension spring counterbalancing systems concerns the prevention of damage and/or injury resulting from the spring breaking while under tension. Past solutions to this problem have generally involved the use of a rope or cable passed centrally through the spring. Such safety cables are disclosed in U.S. Pat. Nos. 3,958,367; 4,082,133; and 4,640,049. In theory, spring pieces are meant to remain suspended on the rope or cable if the spring should break under tension. However, there is no guarantee that when a spring under tension breaks, it will break in only one place at a location in which the two remaining pieces of the spring will be adequately suspended on the rope or cable. The spring may, for example be brittle and break into several small pieces which would not be retained by a rope or cable.
U.S. Pat. No. 4,757,853 discloses the combined use of a safety rope extending centrally through the spring and a pair of metal end caps placed over the two ends of the spring. The purpose of the two end caps is stated to be for containment of the extreme ends of the spring through which the safety rope does not extend. While such end caps may provide containment for the ends of the spring, this safety system still does not provide full protection for the entire length of the spring and, in addition, adds undesirable complexity to the overhead door system.
A need in the art therefore exists for improvements in the art of overhead doors employing extension springs. Specifically, an extension spring system is needed which allows easier installation of the overhead door, especially with regard to the procedures involved with supplying counterbalancing tension to the spring. Furthermore, a system is needed which provides for full containment of the extension spring to guard more completely against damage and injury in the event that the spring breaks under tension.


Pipeline network processors are designed to forward Internet Protocol (IP) packets at an extremely high data rate in excess of two million packets per second. Pipeline network processors typically have a limited number of instruction cycles and memory to perform the applicable task. Implementing features or functions that do not fit the traditional packet forwarding model is a challenging endeavor and may have a negative impact on normal packet forwarding functions such as packet filtering and quality of service processing.
With respect to cable modem routers, one of the required and commonly used features is Multicast Echo. This feature enables cable media to behave like a standard shared media, as in Ethernet, in a local area network environment for Internet Protocol multicast traffic. Cable is a unidirectional media wherein packets are sent from customer premises equipment through a cable modem to an upstream port of a cable modem termination system. Packets are also sent from a downstream port of the cable modem termination system through the cable modem to the customer premises equipment. From a cable standpoint, the configured combination of one or more upstream ports and one or more downstream ports is known as a Media Access Control (MAC) Domain which is a cable media equivalent of a local area network segment.
In a local area network environment, a device is able to receive all multicast packets sent by other devices on the same segment. However in a cable environment, only half of the multicast processing has been completed when a multicast packet is received at an upstream port. The other customer premises equipment connected to the downstream port of the MAC Domain did not receive the multicast packet. Though other devices on the downstream port may be known to be present, normal multicast processing does not add the input interface to the list of output interfaces for multicast traffic and thus no relationship information among ports. This is intentionally done and required by the multicast protocol to avoid multicast traffic loops. The Multicast Echo feature overrides normal multicast processing and permits multicast packets to be forwarded to downstream ports of the MAC Domain.
When a high speed, high end cable modem termination system is developed using a pipeline network processor to forward packets between a large number, several hundred, of cable interfaces and a large number of trunk interfaces, implementing the Multicast Echo feature for the cable interfaces becomes extremely difficult. The cable line cards strip off the Data Over Cable (DOCSIS) header before passing the packet to the pipeline network processor. The pipeline network processor needs to add the original DOCSIS header to the multicast packet in order to forward the packet to one or more downstream ports. There needs to be support for tens of thousands of multicast groups, different service flows, and many MAC Domains. The amount of memory necessary to hold such large data structures and the processing cycles required to search them would preclude the use of a pipeline network processor in terms of cost and performance. A single multicast flow, which is less than 1% of the total traffic, could severely impact the processing of the other 99% of the traffic. Therefore, it is desirable to implement a Multicast Echo feature using a pipeline network processor despite its limited resources.


A data structure is a particular way of storing and organizing data in a computer so that it can be used efficiently. Data structures are used in almost every program or software system. There are many different types of data structures, such as hash tables, binary search trees, skip lists, ternary search trees, etc. In particular, a hash table is a data structure that uses a hash function to map identifying values, known as keys (e.g., a person's name) to their associated values (e.g., their telephone number). Currently, in many situations, hash tables turn out to be more efficient than search trees or other table lookup structures. For this reason, they are widely used in many kinds of computer software, particularly for associative arrays, database indexing, caches and sets.
While hash tables are currently more efficient than search trees or other table lookup structures, the memory footprint (referring to the amount of main memory that a program uses or references while running) and access speed (referring to the lookup rate) could be improved. Hence, the functionality of hash tables should be maintained while reducing the memory footprint and improving access speed.


Tyrosine ammonia lyase (TAL; also referred to as tyrase, L-tyrosine ammonia lyase, and “L-tyrosine ammonia lyase [trans-p-hyroxycinnamate forming]”), along with histidine ammonia lyase (HAL) and phenylalanine ammonia-lyase (PAL) are members of the aromatic amino acid lyase family (EC 4.3.1.23-1.25 and 4.3.1.3). The enzymes having TAL activity are currently classified in EC4.3.1.23 (previously classified as EC 4.3.1.5). TAL catalyzes the formation of p-coumaric acid from L-tyrosine.
Tyrosinemia (also referred to as “hereditary tyrosinemia,” and “hypertyrosinemia”) is a genetic disorder characterized by elevated blood levels of tyrosine, due to the deficiency of an enzyme required for the catabolism of tyrosine in the liver. If untreated, tyrosine and other metabolites accumulate in the tissues and organs of affected individuals, resulting in serious medical issues. Tyrosinemia is an inborn error of metabolism inherited in an autosomal recessive pattern. There are three types of tyrosinemia, each caused by the deficiency of a different enzyme. Currently used treatment methods depend upon the type of tyrosinemia involved. A low protein diet is often used.
Type I tyrosinemia (also referred to as “FAH deficiency,” “fumaryl acetoacetase deficiency,” “fumaryl aceotacetate hydrolase deficiency,” “hereditary infantile tyrosinemia,” and “hepatorenal tyrosinemia”) is caused by a deficiency of fumarylacetoacetate hydrolase, due to mutations in the fah gene. This is the most severe form of the disease, with symptoms usually appearing in the first few months of life, commonly including failure to thrive, diarrhea, bloody stools, vomiting, jaundice, enlarged liver, the tendency to easily bruise, lethargy, irritability, fever, and other symptoms, such as a distinctive cabbage-like odor of the skin and urine. Some affected infants have repeated neurologic episodes of acute polyneuropathy, characterized by severe leg pain, as well as altered mental status, abdominal pain, and respiratory failure. Infants with the acute form are typically affected at birth and there is a rapid onset of symptoms that can lead to developmental delays, enlarged spleen, ascites, kidney disease, and blood clotting abnormalities. Untreated, it can lead to hepatic and renal failure, nervous system problems, and an increased risk of liver cancer (e.g., hepatocellular carcinoma). In some cases, hypertension and hypertrophic cardiomyopathy are present. If untreated, this disease can be fatal. In the less-common chronic form, the symptoms exhibit a more gradual onset and tend to be less severe. Affected infants initially exhibit vomiting, diarrhea, enlarged liver and spleen, and failure to thrive. Eventually, progressive liver cirrhosis occurs, leading to chronic liver failure, developmental delays, and renal Fanconi syndrome (a rare kidney disorder characterized by weakening and softening of the bones [rickets], vomiting, dehydration, weakness, and fever). In some cases, the most effective treatment has been full or partial liver transplant. Worldwide, this form affects approximately 1 in 100,000 human births (Genetics Home Reference, U.S. National Library of Medicine).
Type II tyrosinemia (also referred to as “keratosis palmoplantaris-corneal dystrophy,” oculocutaneous tyrosinemia,” “Richner-Hanhart syndrome,” “tyrosinemia due to TAT deficiency,” and “tyrosinema due to tyrosine aminotransferase deficiency,”) is caused by a deficiency of tyrosine aminotransferase, due to mutations in the tat gene. It affects the eyes, skin, and mental development. As with Type 1 tyrosinemia, symptoms usually begin in early life, and include excessive tearing, photophobia, eye pain and redness, and painful skin lesions on the palms and soles. About half of affected individuals have some level of intellectual disability. This form occurs in less than 1 in 250,000 persons (Genetics Home Reference, supra).
Type III tyrosinemia (also referred to as “tyrosinemia due to 4-hydroxyphenylpyruvate dioxygenase deficiency,” “tyrosinemia due to 4-hydroxyphenylpyuriv acid oxidase deficiency,” and “tyrosinemia due to HPD deficiency”) is a rare disorder, caused by a deficiency of 4-hydroxyphenylpyruvate dioxygenase, due to mutations in the hpd gene. Symptoms of this form include intellectual disability, seizures, and intermittent ataxia. This form is very rare, only a few cases have been reported (Genetics Home Reference, supra).
There are additional cases in which there are temporary elevated tyrosine levels, due to non-genetic factors such as vitamin C deficiency or premature birth, which results in immature liver enzymes. Differential diagnoses are used to differentiate these transient cases from tyrosinema I, II, or III.
In addition to tyrosinema, there are other diseases associated with insufficient or absent tyrosine metabolism. For example, alkaptonuria also referred to as alcaptonuria, is a disease caused by deficiency of homogentisate 1,2-dioxygenase, which is an enzyme involved in tyrosine degradation. This enzyme is encoded by the HGD gene. Insufficient activity of this enzyme results in the accumulation of homogentisic acid. Excess homogentisic acid and related compounds are deposited in connective tissues, causing the cartilage and skin to darken. Over time, arthritis may result due to the accumulation of homogentisic acid and related metabolites in the joints of affected individuals. Homogentisic acid is also excreted in urine, making the urine turn black. Alkaptonuria is a rare disease that affects 1 in 250,000 to 1,000,000 people worldwide (See, Genetics Home Reference, supra).
Treatment of these diseases has largely been the life-long use of a methionine-, phenylalanine-, and tyrosine-restricted diet. Treatment with nitisinone (NTBC; 2-(2-nitro-4-trifluoromethylbenzol)-1,3-cyclohexane dione; Orfadin®) has been reported to be helpful for type I tyrosinemia and alkaptonuria, due to its inhibition of the 4-hydroxyphenylpyruvate oxidase pathway. However, NTBC must be used in combination with a challenging and costly methionine-, phenylalanine-, and tyrosine-restricted diet to prevent both liver failure and carcinogenesis. There remains a need in the art for easy to administer, effective treatment(s) to ameliorate the symptoms of these diseases and allow patients to utilize normal diets.


1. Field of the Invention
This invention relates to improvements in the encoding scheme of gray pixels. More particularly, this invention relates to gray pixel encoding schemes which are used in combination with a halftoning imaging that produces gray level halftoned images.
2. Description of Related Art
Xerographic printers use halftoning processes to generate digital images from originals. The image is formed by using pixels which are completely black, completely white or different shades of gray. These are represented as explicit gray pixels. When viewed from a distance, the pixels blend together to form the image.
In traditional binary xerographic printers, halftone methods use binary systems such that the laser has only two laser intensity levels: ON (black) and OFF (white). Another method is disclosed in U.S. Pat. No. 4,868,587 (Loce et al.), which uses two gray levels: the black and the white level for each pixel. The different levels of gray are based on the intensity of the laser light. Therefore, black has a higher light intensity than either of the gray levels. This method is an improvement over using only black and white pixels. The disadvantage of the system is that the control of the graying levels is difficult and the information is not easily transferable to other printers.
The quality of a binary xerographic printer is based on two important features: the halftone frequency, which is the number of halftone cells per linear inch; and the number of distinguishable gray steps. A typical number of halftone cells for good quality image is between 100 to 200 cells per inch. Usually around nine pixels are used per halftone cell. The maximum number of gray steps is limited to the number of pixels per halftone cell plus one. Therefore, a 3.times.3 halftone cell has about 10 output gray steps.
In the prior art, a halftone cell was divided into pixels which were turned either on or off to form reflectance modulation level. From a distance, the human eye detects a reflectance of about 0.5%, which would be interpreted as a gray level. In a good quality printer, the number of distinguishable gray steps should be around 100.
Halftone images are commonly used in printed materials to reproduce continuous tones using printers that are binary in nature. Conventional digital halftoning processes grow halftone dots by activating individual pixels within a halftone cell. The pixels are typically at printer resolution or at some small integral subdivision thereof. The printer resolution is broken down to the number of spots which are used. For example, a 400 SPI printer has a spot size of 1/400th of an inch. Pixels are used as data within the spot boundary.


Most all types of commercially-available power diodes having high reverse breakdown voltage capabilities have N-type bottomside cathodes. A rare exception is the so-called “inverse diode” or “reverse diode” that is commercially available from IXYS Corporation, 1590 Buckeye Drive, Milpitas, Calif. These unusual diodes have P type isolation structures involving a bottomside P type anode region as well as P type peripheral sidewall diffusion regions. Not only do these diodes have very high reverse breakdown voltages, but they also typically exhibit superior dynamic robustness. An attempt was made to extend this “inverse diode” technology to so-called “fast diodes” having lower reverse recovery times. The reverse recovery time of a diode is denoted Trr in the literature and in data sheets. As set forth in U.S. Pat. No. 8,716,745, an N− type epitaxial silicon layer was grown on a P type wafer. The resulting inverse diode was simulated to have superior stability and a high reverse breakdown voltage while at the same time having a thinner N− type layer as compared to a conventional diode having the same reverse breakdown capabilities. For additional information on inverse diode structures and on P type isolation structures, see: 1) U.S. Pat. No. 7,442,630, entitled “Method For Fabricating Forward And Reverse Blocking Devices”, filed Aug. 30, 2005, by Kelberlau et al.; 2) U.S. Pat. No. 5,698,454, entitled “Method Of Making A Reverse Blocking IGBT”, filed Jul. 31, 1995, by N. Zommer; 3) J. Lutz et al., “Semiconductor Power Devices”, pages 146-147, published by Springer, Berlin and Heidelberg (2011); 4) the data sheet entitled “Diode Chip”, DWN 17-18, by IXYS Corporation of Milpitas, Calif. 95035, USA; 5) U.S. Pat. No. 9,590,033, entitled “Trench Separation Diffusion For High Voltage Device”, filed Nov. 20, 2005, by Wisotzki et al.; 6) U.S. Pat. No. 4,351,677, entitled “Method of Manufacturing Semiconductor Device Having Aluminum Diffused Semiconductor Substrate”, filed Jul. 10, 1980, by Mochizuki et al.; 7) U.S. Pat. No. 6,507,050, entitled Thyristors Having A Novel Arrangement of Concentric Perimeter Zones”, filed Aug. 16, 2000, by Green; 8) U.S. Pat. No. 6,936,908, entitled “Forward and Reverse Blocking Devices”, filed Mar. 13, 2002, by Kelberlau et al.; 9) U.S. Pat. No. 7,030,426, entitled “Power Semiconductor Component in the Planar Technique”, filed Mar. 14, 2005, by Neidig; 10) U.S. Pat. No. 8,093,652, entitled “Breakdown Voltage For Power Devices”, filed Aug. 27, 2003, by Veeramma et al.; 11) the 2004 description entitled “FRED, Rectifier Diode and Thyristor Chips in Planar Design”, by IXYS Semiconductor GmbH, Edisonstrasse 15, D-68623, Lampertheim, Germany.


1. Field of the Invention
This invention relates to a decoder circuit, for example for use in memory addressing.
2. Background Art
FIG. 1 shows an example of the structure of a static random access memory (SRAM) and its addressing circuitry. The memory 1 comprises a grid of memory cells 2 arranged in rows and columns. In this example there are four rows and four columns but typical SRAMs have many more rows and columns. All the cells in a row are connected to a single wordline 3. All the cells in a column are connected to a single bitline 4. Each cell has two stable states, representing high and low output values. When one of the wordlines is activated each bitline takes on the state of the cell to which that bitline is connected and which is also connected to the activated wordline. The bitlines are connected to a multiplexer 5 which allows a single one of the bitlines to be selected to provide the final output from the memory at 6.
Each cell in the memory is allotted a number. To access a cell in the memory the cell's number is applied in binary format to input lines 7. A decoder 8 takes some of the lines 7 (indicated at 9) as input and thereby determines which one of the wordlines should be activated to access the cell. The remainder of the lines 7 (indicated at 9) pass to the multiplexer 5, which thereby determines which of the bitlines should be selected so that the final output at 6 takes on the state of the desired cell.
FIG. 2 shows one example of a structure for decoder 8. The lines 9 each branch through an inverter 10 so that address signals representing inverted (indicated at 11) and non-inverted (indicated at 12) versions of each of the lines 9 are available. The appropriate inverted or non-inverted version of each of the lines 9 is applied to a NAND gate 13 corresponding to each wordline. The output of each NAND gate passes to an inverter 14 which drives the respective wordline.
By means of the correct set of connections to each of the NAND gates a wordline is activated only when the appropriate set of inputs is applied at 9. This circuit is simple, but has a number of disadvantages if the number of address line inputs is increased.
1. In many important applications—for example in the caches of high-speed processors—speed of access to the desired memory cell is crucial. However, the large NAND gates are relatively slow.
2. In almost all applications—and especially in battery-powered applications power consumption is very important. However, in the system of FIG. 2 as the input lines 9 change values potentially many, or all, of the distributed address signals will change, giving rise to a high current consumption. The current consumption is further increased by the need to generate an inverted version of each input line to the decoder.
In an alternative structure for decoder 8 a pre-decode level is-added so that fewer distributed signals can change as the input lines 9 change values. In the predecode level the input lines 9 are split into groups that are processed by a first level of NAND gates. The outputs from those NAND gates pass to a second level of NAND gates whose outputs are inverted to drive the wordlines. Since only one of the lines that connect the two levels of NAND gates changes for each change in input values the maximum power consumption is less than for the structure of FIG. 2. Two levels of processing in the alternative structure make it relatively slow for small numbers of addresses, but for wider decoders (e.g. five or more addresses) it can be faster.
An alternative solution is to use a precharge decode structure. FIG. 3 illustrates precharge decode circuitry that represents an alternative structure for decoder 8. As before, inverted 11 and non-inverted 12 versions of each of the input lines 9 to the decoder are generated. A decode line 20 is provided for each wordline. Each wordline is driven by an inverter 14 which receives the output from a two-input NAND gate 18. One of the inputs to the NAND gate 18 is a common timing enable signal at 19. The other of the inputs is from the respective decode line 20.
Each decode line can be taken high by a respective PMOS precharge transistor 21. The precharge transistors are connected with their sources to a high voltage (Voc), their drains to the respective decode line and their gates to a common precharge signal at 22. Each decode line can be taken low by any of a number of NMOS addressing transistors. The addressing transistors 23 are connected with their drains to the respective decode line, their sources to a low voltage (ground) and their gates to a selected one of the inverted and non-inverted input lines 11, 12. The inputs to the gates of the addressing transistors are arranged so that one addressing transistor of each decode line receives a selected inverted or non-inverted version of each of the input lines 9.
In use, to decode a set of signals applied to lines 9, a pulse is applied to the precharge line 22 so that the decode lines float at VDD). Then the signals from the input lines 9 are applied to the addressing transistors 23. At all the decode lines corresponding to all the undesired wordlines at least one of the addressing transistors is turned on, so that those decode lines can all discharge to ground. At the decode line corresponding to the desired wordline none of the addressing transistors is turned on, so that decode line continues to float at VDD. After a delay that is sufficiently long for the voltages on all the undesired decode lines to have fallen, a signal is applied to the timing enable line 19, This causes the NAND gate 18 corresponding to the decode line that remains high to produce a low output, whereas all the other NAND gates produce high outputs. By virtue of the inverters 14 this causes the desired one of the wordlines to be selected.
The delay before application of the timing enable signal is crucial to the operation of the precharge circuit. The timing enable signal cannot be applied before all the undesired decode lines have discharged to below the input threshold voltage of the NAND gates 18, otherwise more than one wordline will be selected. Therefore, the delay is dependant on the speed with which the decode lines discharge. A decode line with all of its addressing transistors turned on will discharge quickly but a decode line with only one of its addressing transistors turned on will discharge relatively slowly. The timing enable signal is usually derived from the arrangement shown at 24. Another instance of the decode structure is provided, this time with all but one of its addressing inputs connected to ground. The decode line 25 of the arrangement 24 therefore falls towards ground as slowly as any of the undesired decode lines can. The enable input to the NAND gate 26 of the arrangement 24 is held high. As soon as the decode line has fallen sufficiently the output 27 of the NAND gate goes high. The output 27 provides the timing enable signal at 19.
The precharge structure of FIG. 3 can be faster than the structures of FIG. 2. However, the discharge of all the undesired decode lines gives rise to high power consumption, and the necessary delay before the timing enable signal is generated reduces the speed of operation of the circuit. The choice between a static decoder (e.g. as shown in FIG. 2) and a precharge decoder is not clear-cut and very often both options have to be investigated when undertaking a design.
It would be desirable to have a decoder circuit that allowed for faster decoding, preferably at reduced power consumption. In addition to providing a technically superior solution such a circuit could save a considerable amount of investigatory design work.