Are unused connector pins used to provide test stimulus and control
from the tester to internal nodes?
Can circuitry be quickly and easily driven to a known initial state?
(e.g., master clear, less than N clocks for initialization
Are redundant elements in design capable of being independently
Is it possible to disable on-board oscillators and drive all logic
using a tester clock?
Can long counter chains be broken into smaller segments in test mode
with each segment under tester control?
Can the tester electrically partition the item into smaller
independent, easy-to-test segments? (e.g., placing tri-state elements in
a high impedance state).
Is circuitry provided to by-pass any (unavoidable) one-shot
Can feedback loops be broken under control of the tester?
In microprocessor-based systems, does the tester have access to the
data bus, address bus and important control lines?
Are test control points included at those nodes which have high
fan-in (i.e., test bottlenecks)?
Are input buffers provided for these control point signals with high
drive capability requirements?
Are active components, such as demultiplexers and shift registers,
used to allow the tester to control necessary internal nodes using
available input pins?