In 2016, 1366 introduced a new wafer feature made possible with the Direct Wafer® process, the ability to grow a thin wafer with a thick border or what we refer to as a “3D” wafer. This R&D achievement is the result of our technology’s ability to locally control wafer thickness while the wafer forms in the melt. It is an advancement impossible to attain with conventional ingot-based production technologies. The feature has the potential to deliver additional cost reductions to an industry continuously in search of them.
Today, the solar industry operates in a wafer thickness domain limited by wafer breakage during standard manufacturing processes, particularly during value-added processes in cell fabrication and during interconnection for modules. While wafers have reduced thickness over time to lower silicon cost and optimize efficiency, breakage and poor back surface properties of the dominant BSF cell design has resulted in the industry settling on a thickness between 180-200 microns. Thick wafers use more silicon, a key factor in wafer manufacturing costs. Reducing the amount of silicon wasted, as well as the amount of silicon used, will dramatically reduce the cost of wafers and, in turn, the overall cost of photovoltaics. While manufacturers have expressed a desire to move to thinner wafers for both their cost advantages and their potential role in realizing new cell architectures or module advancements, they have been unable to do so using their existing manufacturing lines.
The industry is trending towards PERC-type solar cells and thinner module glass, and both are synergistic with thin wafers and their significant advantages, specifically higher voltage levels and flexibility. Though, again, their lack of mechanical integrity makes it difficult for manufacturers to deliver against future product road-maps.
The increased breakage of thinner wafers has several origins, including
- Edge stress. During cell fabrication, wafers often break by propagation of a defect from an edge of the wafer. Cracks starting from an edge are also a problem during cell interconnection and module fabrication.
- Stringing stress. The bus wires or interconnect ribbons must be bent down from the top surface of one cell so as to wrap under the adjacent cell. This bent wire adds to local stress near the edge of the cell during lamination.
Because 1366’s Direct Wafer process allows for local control of wafer thickness, it enables entirely new wafer configurations that reduce the volume of silicon required for each wafer without sacrificing strength, durability or performance and increase the strength of wafers without unduly increasing their cost, weight, size, rigidity or other properties.
The invention of a wafer that is thinner than a standard 180-200 micron thick wafer in certain controlled regions, but is also strong and robust enough to be used in conventional, or nearly conventional photovoltaic applications has significant implications for the industry. It provides manufacturers with a solution to reduce silicon usage without compromising existing standards or quality and makes it possible to realize industry advancements in cell architecture or module features. Combined with the elimination of waste associated with sawing, the 3D capabilities of the Direct Wafer process, the silicon usage can be less than 1.5 g/W. This enables the dominant crystalline silicon PV supply chain to leverage all of its existing infrastructure and continue down the cost roadmap via a wafer cost below $0.20/each.