After all the hype about the 50th anniversary of Moore's Law last week, there was a real indication that the next steps are getting closer this week, as equipment manufacturer ASML announced that it had reached an agreement to sell a minimum of 15 new EUV lithography tools to an unnamed customer in the U.S., almost certainly Intel.
Chip companies have been talking about the promise of extreme ultraviolet (EUV) lithography for years, touting it as a replacement for the immersion lithography that has become the standard in making advanced chips for more than a decade. With immersion lithography, tiny wavelengths of light are refracted through a liquid to print the patterns used to create the transistors on a chip. This worked well for multiple generations of chip making, but in recent years, as advanced chip manufacturing has moved to the 20, 16, and 14nm nodes, chip makers have had to use what is called "double patterning" to create even smaller patterns on the chips. This results in more time, and more expense, in creating the layers of the chip that need double patterning; and this only will get harder at subsequent generations.
With EUV, the light can be much smaller and thus a chip maker would need fewer passes to create a layer of the chip that would otherwise need multiple passes of immersion lithography. But to make this work successfully, such machines need to be able to work consistently and reliably. The biggest issue has been in developing a plasma energy source – effectively a high-power laser – that will work consistently, thus replacing the 193nm light source common in the immersion machines.
ASML has been working on this for years, and a few years back acquired Cymer, the leading company trying to make the light source. Around the same time, it received investments from its biggest customers – Intel, Samsung, and TSMC. Along the way, the company made lots of announcements about the progress it was making as it moved from tools capable of producing a few wafers per hour until more recently, when the numbers have started to get closer to the 100 wafers per hour or so it will take to make EUV cost effective.
ASML prefers to talk about a combination of wafers per day and availability, the amount of time the tool is actually in production. In its earnings call last week, the company said its goal this year was to get the tools to produce 1,000 wafers a day at a minimum of 70 percent availability; and said one customer was already able to get to 1,000 wafers a day (though presumably not at that availability). ASML's goal is to get to 1,500 wafers per day in 2016, at which point it thinks the tool will be economical for some applications.
In its earnings conference call last week, TSMC said it has two tools currently capable of an average wafer throughput of a few hundred wafers per day using an 80-watt power source.
At last fall's Intel Developer Forum, Intel Senior Fellow Mark Bohr, Logic Technology Development, said that he was very interested in EUV for its potential in improved scaling and process flow simplification, but said that although Intel was very interested in EUV, it was just not ready yet in terms of reliability and manufacturability. As a result, he said, neither Intel's 14nm nor 10nm nodes use that technology. At the time, he said that Intel was "not betting on it" for 7nm and could manufacture chips at that node without it, though he said it would be better and easier with EUV.
The news seems to indicate that Intel now thinks EUV may be ready for that process node. Although ASML did not confirm Intel was the customer, there really isn't another U.S.-based firm that would need that many tools; and the timing would seem to fit with Intel's 7nm manufacturing needs. But note the announcement only said two of the new systems were slated for delivery this year, with the rest of the 15 slated for later, and Intel itself hasn't confirmed it will use 7nm. Likely, Intel is positioning itself so that if the tools really progress at the pace ASML is predicting, it can use it at 7nm.
Of course, most of the other big chip makers have also been customers of early tools, and TSMC has also been very vocal about wanting to have such equipment for future manufacturing. You would expect other chip foundries, notably Samsung and Globalfoundries, to be in line as well, and eventually the memory manufacturers as well.
Meanwhile, there has been a lot of speculation about new materials being used at new process nodes, such as strained germanium and indium gallium arsenide. This, too, would be a big change from the materials currently being used. Again, this hasn't been confirmed, but it is interesting.
Taken all of this together, it looks like the techniques needed for making even more dense chips continue to improve, but that the costs of moving to each new generation will continue to increase.