The Structural Simulation Toolkit (SST) is a system of disparate hardware simulation component entities integrated via a simulator core. The simulator core provides essential services for interfacing, execution, synchronization, and monitoring of the various components. Components represent a variety of hardware systems such as processors, network switches, or memory devices. They interface with the simulator core to communicate and operate with a common notion of time and time units. In the SST architecture diagram shown below, the components are represented at the bottom.
The source code for some components (known as internal components) is stored in the Google Code repository (http://code.google.com/p/sst-simulator) alongside the core directory and is built at the same time. Other components (known as external components) are maintained in other open repositories. They can be independently downloaded, built, and their libraries integrated into the sst.x executable. In some cases, certain SST users such as hardware vendors can also utilize proprietary, closed-source components with SST, which is permissible under SST licensing.
Some component models were originally developed as self-contained simulators. They have been modified to interface with the SST core in order to interoperate with other components.
The component models fall in five general types: 1) processor, 2) memory, 3) network, 4) power, and 5) system-level.
Gem5 is an external component and a custom source code branch operates with SST. Gem5 has multiple processors models (Alpha, ARM, SPARC, and x86) including symmetric multiprocessor systems. It also provides an event-driven memory system. MacSim is another external component that integrates with SST and provides multiple processor models. It is a trace driven cycle level simulator and simulates x86 and NVIDIA PTX instructions. McNiagara and McOpteron are stochastic processor models within SST that can be used in system simulation. They are statistical and based on a Monte Carlo technique. The Opteron is presently a single-core model while the Niagara can model both single- and multi-core processors. Verona is a research grade model of a RISC-V CPU core. Zesto is a timing model based on the pre-release version of the x86 version of SimpleScalar. This simulator was developed for detailed cycle-level modeling of modern out-of-order pipelines.
DRAMSim2, an external component, models DDRx memory controllers, memory channels, DRAM ranks, and banks. MemHierarchy models a memory hierarchy, such as multiple cache levels. Prospero reads a trace file and generates standard memory events that can then be passed to memHierarchy cache/memory models. Prospero also has a simple trace tool that runs under the PIN binary instrumentation framework to capture a memory trace.
Iris, an external component, is a flit-level network simulator. Merlin is a generic router and NIC model intended to connect to vendor-proprietary or other ASICs. The patterns communication component generates traffic for a simplified network model without incurring the processing and memory overhead of running a full endpoint simulator. PhonenixSim is a simulator that supports the ability to model properties of photonic interconnection networks including propagation delay, insertion loss, extinction ratio, spectral resonant profiles, area occupation, and energy dissipation. Portals4, portals4_sm and SS_router model the internal crossbar and input/output queues of the SeaStar from the Cray XT line of computers. Added flexibility is enabled by parameterizing queue depths, FLIT size and number of FLITs in a packet.
In the past, SST supported Hotspot, IntSim, McPat, and Orion. These components have atrophied somewhat and are in the process of being restored.
SST/Macro is an open-source coarse-grained simulator for large parallel high-performance applications and machines and can be used independently of SST/micro. SST/macro enables the exploration of current and future implementations of applications, libraries, and runtimes on performance models of typical supercomputer hardware. The scheduler component models scheduling, allocation and machines. It is also includes failure models.
For more details on developing and building SST refer to the Google code Wiki at http://code.google.com/p/sst-simulator/wiki.