Draw a state diagram for an FSM with one input I that can stopthe sequence when set to 0, and three outputs, X, Y, Z. XYZshould always follow the following sequence: 000, 001, 010, 100,repeat. When the input returns to 1 the sequence start from000. The output should change only on a rising clockedge. Make 000 the initial state. Assume an implicit risingclock is ANDed with every FSM transition condition.