SEMICONDUCTOR firms make integrated circuits with critical dimensions that are shrinking in leaps and bounds. With chip sizes down to 130 nanometres (1nm is a billionth of a metre) and heading fast towards 90nm, a square centimetre of silicon can now have up to 100m transistors etched on to its surface. For the first time this is creating an opportunity for proponents of parallel processing on a single chip—ie, a processor that breaks tasks down into lots of little jobs that are then tackled simultaneously. Some even believe that the semiconductor firm that cracks the parallel-processing problem could be the next Intel.
It is not certain that parallel processing at the chip level will succeed. All the leading processor designs are essentially uniprocessor in layout, with limited internal parallelism. But even when the core of a processor is accompanied by a large cache of memory, it still occupies only a small portion of a contemporary digital chip. So there is room on board most processors for multiple cores that are capable of doing at least a modicum of parallel processing.
Over the past five years, dozens of chip developers, usually working without their own fabrication plants, have introduced designs that incorporate hundreds of microprocessors networked together on single chips. PicoChip Designs, a “fabless” start-up based in Bath, England, has adopted the parallel approach to digital signal processing for third-generation mobile-phone networks. The company says that its PC101 chip is being evaluated by at least one leading supplier of base-stations for mobile-phone systems. PicoChip's design includes some 430 processors, interconnected on a single chip.
Meanwhile, a Munich-based company called PACT has integrated 128 processors on a giant chip of its own. The difference is that cores in the PACT chip process data in 32-bit chunks; the PicoChip design does it 16 bits at a time. A second British start-up, Siroyan of Reading, has been working on a “clustered” digital signal processor (DSP) approach called OneDSP. Other parallel-processing start-ups in Britain include Elixent and ClearSpeed, both based in Bristol.
In North America, Improv Systems of Beverly, Massachusetts, is also designing a “scalable”DSP type of chip. Internet Machines of Agoura Hills, California, and Hyperchip of Montreal are both in the massively parallel camp. These are just a handful of parallel-processing chipmakers that have actually produced silicon. Many more hopefuls are now entering the business.
Why the rush to parallelism? One answer is that semiconductor firms do not actually know what to do with the vast numbers of transistors they can now put on a single chip. The industry's ability to design and verify something with the complexity of 100m interconnected transistors has not kept pace with its ability to manufacture it.
Most contemporary chips are composed of multiple blocks of lesser complexity, proved in a previous generation, but bolted together like Lego pieces during the design stage to make a new layout. An alternative approach is to design something less complex in the first place, and then to replicate it across the surface of the chip—to create a parallel-processing architecture.
Easier done than said. While not difficult to produce, a parallel-processing device is notoriously difficult to get running properly. As the number of processors increases, the time spent on actual processing diminishes and the time spent communicating—or waiting for other processors to communicate—increases. The point at which the benefits from adding more processors vanish depends on how the individual processors are interconnected and on the type of problem they are seeking to solve.
This explains why parallel processors are often used for specific applications. Limiting the scope of the problems they try to solve simplifies the developers' work in tuning their parallel architectures for optimum performance. One of the most common applications is in networking, especially wireless LANs (local area networks) and third-generation mobile phones. So far, however, none of the parallel-processing chip firms has come up with a commercial winner. That invites further questions about whether Intel, AMD and Texas Instruments can afford to ignore the rush to parallelism.
Actually, they are not. In January 2003, without the usual hoopla, Intel quietly revealed a few details of the parallel-processing architecture that it has under development. The Intel architecture is based on an array of several different types of processors that vary in complexity. The processors are connected through a mesh of nearest-neighbour connections that favours the so-called “data-flow” form of architecture, used widely by enterprising supercomputer builders in the 1980s.
The purpose of the new Intel design is to provide the guts of a reconfigurable radio terminal. The term “software-defined radio” is used to define a kind of mobile terminal that can sniff the radio ether and adapt itself to whatever networks it finds out there—in effect, reconfiguring itself on-the-fly to whatever radio protocol is being used.
History shows that the key to success, however, will not be the types of processor selected for a parallel architecture, nor the way they are connected. More important will be the combination of physical architecture and software. That was the case with Microsoft's MS-DOS operating system and Intel's 8086 processor architecture, which drove each other's sales upwards during the 1980s, and by the 1990s had created the dominant “Wintel” force in information technology.
The key to success in parallel processing on a chip will be the ability to map computational algorithms efficiently on to an array of resources, and hide the complexity from both programmer and user. The company that can do that has a shot at being the next Intel. And that just might be Intel itself.