We’ve been integrating increasing amounts of semiconductor IP, from third-party vendors and previous designs, into IC designs for decades now. But where once an IP block was a rarity embedded in a sea of custom logic, these days it is the other way around.
The sheer logic and memory capacity offered by today’s processes, and the advantages of using these processes to integrate entire systems, mean that the proportion of each new chip that is original work is shrinking rapidly.
Semico Research says that around 65% of the average chip design done this year has been based on IP. By 2017, the research firm forecasts that IP could account for up to 80% of a design.
Chips become systems
When chips become systems, the whole system development process becomes intimately involved with the IC design process. Where once systems were built of a hierarchy of chips, boards, subsystems and interconnect schemes that could be designed, debugged, validated and programmed as standalone units before integration, now all these steps become part of IC development.
IP blocks and the logic that interconnects them may first be expressed as transaction level models, which can be used as virtual prototypes, before being replaced with RTL descriptions. These can then be synthesised into gates for a standalone FPGA-based prototype of each IP block; to gates for each IP block as part of a larger system FPGA-based prototype; and finally to ASIC gates for the SoC.
With pressure on time to market always increasing, what designers need most as they move along this path is consistency, consistency that ensures that, for example, the unit tests written to run on an FPGA-based prototype of a standalone IP block will also work when that block is subsumed into a SoC-level FPGA-based prototype, and later into the SoC.
For example, the physical structures of ASICs and FPGAs are different, so designers need tools that can translate the clocking, debug and power-management schemes intended for the final SoC into hardware that can actually be implemented on the FPGA. It’s vital to ensure that the way this translation is done ensures that the behaviour of the IP block is consistent and reusable right along the line, from the standalone FPGA-based prototype to the final SoC-level FPGA-based prototype.
With the software content of SoCs rising, and an increasing emphasis on multicore designs and realtime data handling, for example in multimedia subsystems for smartphones and tablets, the number of software developers who need early access to physical prototypes to prove their code on live data streams is also increasing.
It’s useful for such developers to be given IP block prototypes in a physical format that is consistent from project to project, to cut the time it takes for them to understand the related tool chain, scripting, test access and I/O options. Access to an IP-level prototype enables early software development tasks that are essential for the SoC level bring-up. But it’s vital that these prototypes can be physically integrated into a larger system FPGA-based prototype, for example as a plug-in for a Synopsys HAPS-70 system, in a consistent way.
This helps ensure that system developers can be confident that the integration of IP block prototypes into a system prototype is as rapid and transparent as possible, accelerating the SoC-level prototype bring-up task. Synopsys’ HAPS-DX system offers plug-and-play interoperability with HAPS-70 systems, ensuring that the task of integrating the IP into the SoC-level prototype is as seamless as possible.
Consistency should also help when (if) system developers decide to take an intermediate step before going to the SoC design, by moving the individual IP blocks out of their standalone hardware prototypes into the larger-capacity FPGAs available on a system such as HAPS-70. If the boards for the standalone prototypes have been built in a way that is consistent with the design of their larger system-prototyping relatives, the integration of the logic that they carried should be much smoother.
The combination of consistent hardware and consistent tool chains throughout the IP to SoC design flow should make it easier to put physical IP models into software developers’ hands earlier in the system development process. It should also ensure that the code they write and the hardware they wrote it for move quickly and efficiently through the integration process from standalone IP block to system prototype to final SoC.
Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions. He has held various product marketing, application consultant and technical marketing manager positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.
Company infoSynopsys Corporate Headquarters 700 East Middlefield Road Mountain View, CA 94043 (650) 584-5000 (800) 541-7737 www.synopsys.com
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