Get email delivery of the Cadence blog featured here
Fifth Generation (5G) cellular technology will enable the
"tactile Internet"--when humans will wirelessly control real and virtual
objects--but not before we overcome enormous system design challenges.
That was the assessment from Gerhard Fettweis (pictured, below), the Vodaphone Chair of Mobile
Communications Systems, Dresden
University of Technology, who spoke Sept. 3 to Cadence employees at the company's San Jose headquarters.
now, wireless communication--cellular
moving content, voice,
video data, whatever it was," Fettweis said. "Tomorrow we can start to control
virtual and real objects. That is really the cool thing: the tactile Internet--
revolutionizing our whole life."
But to get
there, we need to address data rates, how we design wireless communications
fabrics, how we address latency, how we think about memory subsystems, and how
we deliver EDA tools and IP services, Fettweis cautioned.
potential--and it won't come for many years--is staggering.
"We can expect 128K
small Tensilica cores. We can expect 4x4 chip stacks on each side of the board.
128 chips stacked in 3D (the iPhone, he noted, contains 16 today); 4 boards in a box measuring 4x4x4
inches, exactly 1 litre in volume. We can then place 16,000 chips, which is a
billion cores, which is an exascale computer in every liter."
That's 105 more compute power than we have today, so, "We
have 25 years of innovation ahead of us," he added.
One of the
many challenges the industry will face in those 25 years is inter-chip
communications, which is going to have to get blazingly faster.
this, Fettweis and his colleagues at Dresden have created the Highly Adaptive Energy-Efficient Computing
problem is not more processors on a chip, it's how to connect them," he said.
"We're working on embedded optical connectivity with embedded wave guides
getting up to petabit/second bandwidth on the board and connecting boards on a
Raising the data rate bar
other efforts will drive the industry forward in its pursuit of higher data
"The question is not, do we need higher data rates than we
have today? The question is how ... can we get this solved so that we can
deliver not only gigabits all the way up to terabits?"
This pursuit has to be undertaken because today's data rates--even at 4G LTE--are not sufficient "to connect in real time our video and cell
phones to the Internet."
Fettweis cautioned against focusing solely on data rates as the key
to mobile product success. Apple stock declined significantly after the
introduction of the iPhone 5 with an LTE modem, he said.
"So introducing a new product with only higher data rates alone
cannot be the solution," he said.
The tactile Internet, Fettweis said, will come about when we
overcome the latency issue. Humans, he said, expect to see movement within a
millisecond of an action. Game players get "cyber sickness" if what they're
seeing moves slower than that rate.
He cited examples as diverse as urban traffic control systems to
automobile factories geared to do different body types on the same line because
their robots would be so responsive.
How do we get to that millisecond?
Memory is key
as an example the Tomahawk 2, an extremely fast, energy-efficient and resilient heterogeneous
multi-processor which can easily integrate very different kinds of devices.
It works by architecting "a lot of little memories with two
processing engines hanging off every memory." One of those is a vector DSP, the
other a Tensilica core. "So we can switch between a single processing engine
and a control processing engine as needed," Fettweis said.
This, in addition to introducing some processing efficiency, also
cuts power consumption, he said, adding:
"You get your packets
decoded; they're sitting in memory. You switch the chip into the different
mode; and then DSP is turned off, the MPU turned on, hanging off the same
memory and you can continue the control processing."
Asked how EDA can address these challenges, Fettweis said one area
is in resiliency.
Outage on a good wireless network is 3 percent or 40 minutes a day
that packets are lost, he said. Dynamic scheduling is one way of addressing the problem, he added.
A second way EDA vendors can step in is by coming up with the right
architecture for in-memory computing:
"Today, we have memories
with some gates hanging off. Basically we're memory designers. We don't have
help in our current tools yet in looking at system design just from a memory-optimized fashion. We're still thinking too much of gates and not enough about