Cascade adaptive array structures
Cascade adaptive arrays that reduce processor requirements, increase reliability, and create modularity are proposed. These cascade adaptive arrays reduce processor complexity by breaking a large array up into a number of smaller subarrays that can then be processed by a smaller, more economical signal processor. Futhermore, cascade performance approaches that of a fully adapted array. When coherent interference is present, adaptive arrays eliminate not only the interference from the output of the array, but can also suppress the desired signal. As an example of a cascade adaptive array, the spatial averaging method or the spatial dither method is used to alleviate coherent interference. This method breaks the array into subarrays. Spatial dithering is a natural by product of cascade subarrays. The subarrays are adapted and averaged. The spatial dither method breaks the interference coherence up by decorrelating it with the desired signal. The array can then differentiate between the signal and coherent interference. Cascade adaptive array structures consisting of 2, 3, and 4 element subarrays were examined. The performance of these cascade arrays was compared to the non-cascade case. Two cascade adaptive algorithms, the least mean square LMS and sample matrix inversion SMI, were simulated and compared to that of non-cascade arrays using the same algorithms. In addition, simulation was used to spatially dither the subarrays in order to demonstrate coherent interference rejection with the cascade array structures. The following are the advantages of a cascade approach. A time division multiplexed (TDM) processor is possible. The smaller subarrays require processors of lower complexity. When smaller least mean square arrays are used they converge faster than a large array using the same technique due to eigenvalue spread reduction. Also with the sample matrix inversion (SMI) technique the estimation delay decreases over that of a larger array. System reliability is enhanced through the use of multiple smaller signal processors. If a single processor fails another of a pool of processors may take its place in the array or its output may be suppressed by succeeding signal processors. Economy is achieved through the use of smaller, more economical, signal processors incorporated in a parallel processing system.
School Location:USA - Ohio
Source Type:Master's Thesis
Keywords:cascade adaptive array structures spatial dithering coherent interference sample matrix inversion smi
Date of Publication:01/01/1990