India’s first RISC-V based silicon chip got success results in the design and booting LINUX based distribution process!
What is Shakti?
The Shakti project is based on the RISC-V based silicon processor . Shakti achieved the success to booting the Linux in first ever RISC-V based chip processor.An ARM killer From IIT,Madras,INDIA.
what about these buildup saying Shakti the ARM killer? The project team of Shakti deny from this statements so this is probably not the case.According to Madhusudhan, Shakti is already going into production with the first design in the control system of experimental civilian nuclear reactor and they will also provide whole host op ip’s including the smaller trivial ones and also need bigger blocks like SRIO,PCIe and DDR4.
For those who unfamiliar with the term, RISC, which stands for reduced instruction set computer, is an architecture that uses fewer computing cycles per instruction making it ideal to carry out a set of smaller and general instructions. ISA is short for instruction set architecture, which defines the specifications to be met by a processor,it tells the CPU what it needs to do like, Addition or Multiplication.
ARM (Advance RISC Machine) are known for their low power use ,ISA (Instruction set Architecture ) based processor Used in Smartphone,Tablets,IOT devices and other small Devices, and here we have brand new processor Shakti is The RISC-V based processor made considering low power consumption,small and speed.
Physical manufacturing of chips – slated for first quarter of 2018 – could be the beginning off competition against chip makers such as ARM
Shakti Performance at first BOOT
As it is tested on intel’s 22nm finFET technology chip, currently clocking at 400MHz, DMIPS/MHz-1.67, besides the fact is that Linux was able to boot present a proof of concept of design by which the project team could moreover move approaching more production SoC designs.
Shakti Processor variants are of Six categories with one MIcrocontroller ( C Class) and Five Processor (I, M, S, H, T Classes).