|1.||A wattmeter circuit comprising a first delta sigma modulation system having an input for a first analogue signal representative of the voltage across 5 a load in which the power is to be measured, a second delta sigma modulation system having an input for a second analogue signal representative of the load current, a clock circuit for supplying clock signals to both the said modulation systems, and a digital 10 multiplier for multiplying together the digital outputs of the said modulation systems, the clock signals supplied to the said modulation systems being coherent but in phase opposition so that the output from the multiplier has a low noise level at low 15 frequencies.|
|2.||A wattmeter circuit according to claim 1, wherein the multiplier is an exclusiveOR gate or an exclusiveNOR gate.*& 20.|
|3.||25 _5U 35.|
This invention relates to a wattmeter circuit particularly, but not exclusively, for use in a 5 kilowatt hour meter.
It has been previously proposed to provide a wattmeter circuit using delta sigma modulation - see Delta Modulation Systems by R. Steel published 1975 by Penteck Press Limited at page 365. In this case
10 one of the two variables (voltage and current) which have to be multiplied together to give a measurement of instantaneous power in a load is converted into a delta sigma pulse form and the other variable is used to modulate the height of the pulses which has the
15 effect of multiplying the two quantities together when the recovered pulse waveform is reconstituted by low pass filtering. Such an arrangement has the disadvantage that the pulse train output is partly analogue in nature and consequently is not suitable
20 for directly driving digital devices eg. counters and computers. To drive a digital device, this prior art method requires the pulse train to be reconverted to an analogue signal, then subsequently to be converted into a purely digital form.
— It is an object of the present invention to provide an improved wattmeter using delta sigma modulation.
According to the present invention there is provided a wattmeter circuit comprising a first delta
-'• • sigma modulation system having an input for a first analogue signal representative of the voltage across a load in which the power is to be measured, a second delta sigma modulation system having an input for a second analogue signal representative of the load
-^ current, a clock circuit for supplying clock signals to both the said modulation systems, and a digital
multiplier for multiplying together the digital outputs of the said modulation systems, the clock signals supplied to the said modulation systems being coherent but in phase opposition so that the output from the multiplier has a low noise level at low input levels.
The digital multiplier may be an exclusive-QR or an exclusive-NOR gate.
It might be thought possible to use a delta-sigma modulator for each variable with both the modulators being controlled by the same clock pulses and then to multiply together the digital outputs of the two modulation systems. Such dual modulation systems are known in the communications field but in practice they are not suitable for a wattmeter circuit because the output from the multiplier has a high noise level at low input levels. This is because of the idling pattern of this modulating system. The pattern of output pulses with zero input voltage is a sequence of alternating 0 and 1, i.e. 01010101... . When the input voltage is precisely zero and providing all parts of the circuit are exactly accurate this output pattern will retain coherence. If the input current is also zero the current waveform derived from the same clock may be in phase or 180° out of phase with the voltage pulse train. Multiplication of the two output signals representing voltage and current will thus be either 0000... or 1111... representing minus the maximum power level or plus the maximum power level respect¬ ively. In reality, the coherence of the pulse trains to the multiplier is limited. Sooner or later the 1010... changes to 0101... . The smaller the voltage and current inputs the longer these chains continue and therefore the longer the output of the multiplier is either at 1 or at 0. However, with a small voltage
and a small current there will be a limit to the coherence of these pulse trains and hence there will be limits to the time in which the output is 1 or 0. The time average of the output of the multiplier will in fact be an accurate multiplication of the voltage and current waveforms. The problem is the low frequency noise level which depends upon the duration of the coherent pulse trains which increases as the voltage and current inputs tend to zero.
In the use of the present invention, in the event of zero inputs on both the voltage and the current waveforms, the output will also be zero rather than being indeterminate and either plus or minus.
The invention will now be further described by way of example only with reference to the accompany¬ ing drawings, in which :-
Fig. 1 is one embodiment of a wattmeter circuit forming part of a kilowatt hour meter circuit;
Fig. 2 is a clock circuit for use in the circuit of Fig. 1,
Fig. 3 shows an alternative counter circuit for use with the wattmeter circuit of Fig. 1; and
Fig. 4 illustrates a circuit for use with the circuit of Fig. 3.
The watt meter circuit of Fig. 1 comprises first and second delta sigma modulation (DSM) systems for receiving first and second analogue input signals representative of the voltage V and current I across a load in which the power is to be measured. Each DSM system encodes the analogue input signal into binary pulses which are transmitted to the system output. The binary pulses are also supplied to a feedback loop in which they are decoded back into an analogue waveform for supply, to a comparator. The comparator output is connected to a sampler for
periodically sampling the output to produce the output binary pulses. The binary pulse outputs of the two DSM systems are connected to inputs of an exclusive NOR gate the
5 output of which is the output of the wattmeter circuit. In the drawing the samplers of the two DSM systems are shown as comprising respective clocks 1 and 2 which are coherent but in phase opposition so that the output from the exclusive-NOR gate has a low
10 noise level at low frequencies. A suitable clock circuit is illustrated in Fig. 2 and comprises a clock generator, the output of which is connected to the clock input of a divide-by-two stage the Q and bar outputs of which are fed to the two DSM systems.
15 The output of the exclusive NOR gate is connected to one input of an AND gate of which the output is connected to a counter. The other input of the AND gate is connected by a delay to a counter clock which may be the clock generator shown in Fig.
'-'-> 2. Thus the output from the exclusive NOR gate is used to gate the clock waveform onto the counter the output of which is therefore representative of total energy consumption. An output of zero counts represents maximum negative power in the circuit 5 being measured, half the maximum counts corresponds to zero power in the circuit and the maximum number of counts is generated by the maximum positive power in the circuit. This simple form of counting is quite satisfactory for a remote-transmitting wattmeter which may be feeding information to a computer by outputting a pulse to the computer after reaching a certain count. The computer would be programmed to expect x pulses per second for zero input and hence the total range would be 0 to 2x
35 pulses per second. An advantage of such a counting arrangement is that there is automatic checking of
functionality of the circuit and that even if the circuit being measured were switched off a predetermined number of pulses would be transmitted by the measuring circuit thus enabling the computer to verify automatically that the transmitting kilowatt-hour meter was in fact working correctly.
Fig. 3 shows a slightly more complex system such as might be used for an indicating-kilowatt-hour meter in a domestic environment. In this case, the output from the exclusive NOR gate is used as the control input for an up-down counter which increments on the falling edge of each of the counter clock pulses when the output is high and decrements when the output is low. Kilowatt-hours are thus accummulated directly and it is possible to divide down the number of pulses to produce e.g. one pulse out per 0.1 kilowatt hour, this pulse train then being used to drive the standard electromechanical counter system. Modified forms of delta sigma modulations may be used as an alternative to the simple modulators illustrated in the drawings. For example the input signals to the modulators may be delayed to improve performance in known manner. In the arrangement of Fig. 3 the less significant bits of the up-down counter will be changing binary states at a relatively high ripple frequency. To avoid problems analogous to the problem of relay contact bounce in electromechanical systems digital hysteresis can be introduced into the counting circuit. An appropriate circuit is illustrated in Fig. 4.
The display in Fig. 3 may be electronic and the arrangement of Fig. 3 may be connected to other digital devices, e.g. remote reading equipment.