In Parts 1, 2, and 3 we took a closer look at calculating “ac” gain and how to desensitize the circuit to temperature and transistor parameter variations. In part 4 we consider the effects of a coupling capacitor and how to achieve higher gain.
In Figure 6, in Part 3, we added an input coupling capacitor (C1). The main purpose of the capacitor is to “decouple” the ac signal source from the DC bias network. However, the capacitor introduces a “pole” (frequency dependent XC ). XC interacts with the source impedance, the biasing network and with a finite beta, the base input resistance (generally dominated by beta*RE ).
Because of the capacitor, the gain of the amplifier at DC must be zero. Depending upon the R and C values selected and the particular non-ideal characteristics of the transistor, the resulting AC response could look like that below in Figure 7. Note that effects of beta, RO , RL and the biasing network have been taken into account to yield a mid-band gain of 10 (20dB).
The parasitic junction capacitances and other factors determine the transistors’ high-frequency performance. Ccb can be particularly significant due to gain multiplication (i.e., the Miller Effect). Depending upon the transistor characteristics and other layout-induced capacitive and inductive effects, a decrease in gain is to be expected at “high” frequencies.
Achieving higher gain
As suggested earlier, designs with resistive loads greatly limit the possible gain with a practical power supply voltage. You will recall that this is due primarily to the IC *RL voltage drop. What if we could produce a relatively high impedance load without the IC *RL voltage drop? Well, we can by using additional “active” components (transistors) to replace the passive resistive load. This is not to suggest that adding additional transistors in this way is necessarily practical for a discrete design. Rather, I simply wish to show the possibilities.
Transistors T2 and T3 form a “current mirror.” The current flowing in T2 is nominally V1/R (actually [V1-VbeT2 ]/R). If we assume that T2 and T3 are well matched and at the same temperature, the emitter current of both transistors will be the same. Note that their base-emitters are in parallel, so their VBE are the same. Actually, however, their collector currents will not be exactly the same. This is due to the finite output impedance of T3. Note that T2s collector-base voltage is zero, while VCB of T3 can change. However, to a first approximation, IT3 = V1/R.
This example is intended to demonstrate the concept of a transistor current source (e.g., high Ro) replacing a passive resistive load. Note that the R1 , R2 biasing suggested here is still too simplistic for a practical “discrete” circuit design. Again, the reason is that the DC operating point would be highly dependent upon the supply voltage, temperature, and transistor matching. If we were designing an integrated circuit, we would have the luxury of almost unlimited devices to compensate for the above limitations.
In Part 5 we will see how to minimize output loading to maintain high gain.