Clueless is nns project to create a digital delay (audio echo effect) from logic chips and SRAM. Since the project is µc-less, but in a musical context certainly not useless, the codename became scrambled to Clueless. It also seems fitting because it's my first real attempt at circuit design.
A delay effect takes a signal and spits it out after some time. This is used in music to create echo effects (by mixing the output of the delay with the original signal), often combined with feedback (feeding the output of the delay into the input) making the signal repeat several times. The feedback path often contains effects, especially gain reduction and filtering, so that repeats become progressively quieter and more muffled.
In software, this is easily implemented by having a buffer, a pointer to an address in the buffer, and an infinite loop such as this:
output(buffer[address]); buffer[address] = input(); address++;
Where the input() and output() functions read from and write to, respectively, the audio coming into and out of the programme.
The time of the delay is then a function of the size of the buffer and how fast we move through it (the sample rate). CD quality audio is 44100 samples per second, so 1 second of delay will require a buffer of 44100 samples (16 bit words on a CD).
Digital hardware overview
The same algorithm seems easy to implement with digital hardware.
Since we want to be able to attach analogue audio sources, the input and output functions of the above code correspond to analogue-to-digital and digital-to-analogue converters. I've got TLC0820 ADCs and TLC7524 DACs (incidentally, the same used in the original 8-bit Emulator) here, so that's what I'm using. These are both still available, although the DAC is a little more expensive than I'd like.
The buffer itself is just static RAM. Musical echo effects require delay times of maybe 100ms to 2s. We can accept sample rates down to maybe 40khz without too much loss of fidelity. Sometimes you want to go lower to get a crunchy, lofi sound, but it'd be nice to store 100000 samples. For the prototype, I'm using a chip I pulled off a PC motherboard (W24512), which doesn't look like it's in production anymore, but you can still get DIP SRAMs for cheap, and there's a standardised pinout, so it should be easy to update to something more current.
The address pointer in the above code just counts up, so it's natural to implement it as a couple of counters, which are obviously easily and cheaply avaiable in both 74xx and 40xx versions. To address 100000 samples, we need a 17 bit counter (giving us up to 128k). Since the largest parallel output counters I've found are 8 bit, a 16 bit counter is easier to make, so if we can accept the lower sampling rates needed for the longest delay times. We've decided that we can, so we're using two 74HC590 8-bit counters hooked up to form a 16 bit counter.
Most through-hole SRAM I've seen is only 8 bits wide. You could use two, of course, for lower and upper bytes, respectively, but then most of the ADCs and DACs with parallel input/output are also 8 or 12 bit, at least those in my price range. You can get very cheap 16b DACs and ADCs with serial input, but then you need to decode that from the parallel I/O of the memory, or use serial memory and try to get it to line up. For this application, though, the decreased fidelity of 8 bit conversion and storage might actually have a musically desirable quality, so we're just going to run with it.
The last bit that needs to be translated from the code is the sequencing - that is, we need to be able to perform the three logical operations in order. Thus can be done with what seems to be fairly standard scheme of a counter hooked up to a decoder. In our case, a 74LS161 counter into a 74LS139 2-4 decoder. The lower two bits of '161 drive the '139, which selects one of its four outputs based on the output. These outputs activate, in turn, the DAC (output()), the ADC (input()) and the cascaded '590s (address++), as well as the appropriate R/W operations on the memory (buffer).
As of Sept. 7th, 2013, this part of the circuit runs and gives a nice delay effect. It needs a 4x sample rate clock pulse on the input to the '161. A switch to halve the length of the buffer for shorter delays without requiring ludicrous sample rates needs to be added, and various other hacks could be fun to do, but the most pressing part is the analogue circuitry.
Analogue hardware overview
The TLC0820 ADC needs a unipolar input, so the first step is a bipolar to unipolar converter. This requires a single opamp and is already working. The 7524 DAC outputs a current, which can be turned into a bipolar voltage with two regular opamps. This works. My breadboard version has these parts working as well as somewhat variable feedback as of Dec. 23rd. This gives a nice delay effect, although there is a lot of noise. Hopefully that will magically go away when it's moved to a PCB and decoupling caps are added.
Most filter designs I've looked at require a bipolar power supply. Fortunately, the Shruthi synth contains a fairly simple way of converting ~6VDC to +/-5VDC. A lot of DIY analogue music electronics use +/-12 or +/-15, which gives better quality audio due to the added headroom. I want as compact a design as possible, and obviously the Shruthi sounds very nice, so I'm just going to nick that. All the digital chips I'm using run on 5VDC, so everything can be run from this supply.
It probably needs filters both pre-ADC and post-DAC to keep aliasing in check. The first of these will be some sort of simple high order lowpass filter, and the second will be a more regular switchable HP/LP/BP switchable voltage-controlled filter, probably a more or less direct clone of the Shruthi/Ambika SVF.
Having the address and data busses exposed provides interesting options for circuit bending and other glitchy nonsense. Feeding an address or clock line to a bit on the data buss or vice-versa can give cool unpredictable noises and I intend to take full advantage of this.
The clock, a 5VPP pulse wave, can be done with a simple inverter, a capacitor and a resistor. A 74LS14 hex inverter serves nicely for this purpose, although it seems suboptimal to have five unused inverters. These could obviously be brought out to a patch bay or similar, along with the buss lines themselves, and maybe with additional logical functions for weird circuit bending effects. A voltage controlled oscillator for the clock would be nice, though, to make flanging and pitchshifting delay possible. This is TBD.
It'd be nice to easily be able to set the buffer length to a musically useful value. Sync'ing to a modularesque line 16th note pulses seems hard: at 120BPM, that amounts to an 8Hz clock and I don't how to go from that to a useful sampling rate in any predictable manner. Tap tempo, however, could probably be implemented with a suitable set of a extra counters, clocked from the same source as the address counters, and digital comparators and AND gates: the first tap starts the extra counters running, the second stops them; the digital comparators are used to reset the address counters whenever they reach this number. This is for version 2, though :)
It should be possible to make Clueless stereo. Multiplexing the ADCs and DACs is feasible, and the RAM chip I'm looking to use (AS6C1008, 1.72eur at Mouser in onesies) is 128kb which is too big for the 16 bit addresses -- and arguably, even 64k is too much for what we're doing. Dividing the RAM into two is simple: just drive the highest address bit from the (at the moment unused) third bit of the '161 so it changes every other cycle of the sequence. Peasy.
However, this'd mean that the delays had to be equally long, which seems like a missed opportunity. Switching or augmenting the variable clock with a divide-by-n scheme would allow us to add an extra set of counters might be able to fix this, using a magnitude comparator to reset the counters at some point through the buffer.