LVDS is a differential signaling system, which means that it transmits two different voltages which are compared at the receiver. LVDS uses this difference in voltage between the two wires to encode the information. The transmitter injects a small current, nominally 3.5 mA, into one wire or the other, depending on the logic level to be sent. The current passes through a resistor of about 100 to 120 Ω (matched to the characteristic impedance of the cable) at the receiving end, then returns in the opposite direction along the other wire. From Ohm's law, the voltage difference across the resistor is therefore about 350 mV. The receiver senses the polarity of this voltage to determine the logic level. This type of signalling is called a current loop.
The small amplitude of the signal and the tight electric- and magnetic-field coupling between the two wires reduces the amount of radiated electromagnetic noise.
The low common-mode voltage (the average of the voltages on the two wires) of about 1.25 V allows LVDS to be used with a wide range of integrated circuits with power supply voltages down to 2.5 V or lower. The low differential voltage, about 350 mV as stated above, causes LVDS to consume very little power compared to other systems. For example, the static power dissipation in the LVDS load resistor is 1.2 mW, compared to the 90 mW dissipated by the load resistor for an RS-422 signal. Without a load resistor the whole wire has to be loaded and unloaded for every bit of data. Using high frequencies and a load resistor so that a single bit only covers a part of the wire (while traveling near light speed) is more power efficient.
|GND||1.0 V||1.4 V||2.5–3.3 V||1.2 V|
LVDS is not the only differential signaling system in use, but is currently the only scheme that combines low power dissipation with high speed.
Two examples of LVDS use in computer buses come from HyperTransport and FireWire, both of which trace their ancestry back to the post-Futurebus work which also led to SCI. LVDS is supported in SCSI standards (Ultra-2 SCSI and later) to allow higher data rates and longer cable lengths. Serial ATA, RapidIO, and SpaceWire utilize LVDS to allow high speed data transfer.
LVDS can also transport video data from graphics adapters to computer monitors, particularly flat panels, using the Flat Panel Display Link (FPD-Link), LVDS Display Interface (LDI), or OpenLDI standards. These standards allow a maximum pixel clock of 112 MHz, which suffices for a display resolution of 1400 x 1050 (SXGA+) at 60 Hz refresh. A dual link can boost the maximum display resolution to 2048 x 1536 (QXGA) at 60 Hz. FPD-Link works with cable lengths up to about 5 m, and LDI extends this to about 10 m.
MLVDS has two types of receivers. Type-1 are nearly compatible with LVDS and use a 0 Volt threshold. Type-2 use a 100 mV threshold to handle in a consistent way various errors such as open and short circuits. For MLVDS:
|Input Min/Max||Output Common Mode Min/Max||Output Amplitude Min/Max|
|-1.4 / 3.8 V||0.3 / 2.1 V||0.480 / 0.650 V|