Student Projects 1999
|Microprocessor Performance||Hardware||1999||Student Projects||NetOS|
Contact: Ian Pratt email
Nemesis, along with other real-time operating systems, is designed to enable fine-grained quality of service guarantees to be made to applications. This means that the processor must context switch between different applications at a much higher frequency than on conventional operating systems.
Modern processors are not designed to do this- they are pretty fast but they can't turn corners. They contain internal state that records past behaviour of a program in order to optimize current execution (instruction, data, branch prediction, and jump target caches etc.) Unfortunately, context switches typically cause all the accumulated state to be discarded.
The aim of this project is to measure how context switch frequency affects the performance of modern processors like the Alpha 21164 and Pentium Pro. This can be done by devising suitable experiments in which multiple applications (such as those in the SPEC benchmark suite) are run in parallel on a single processor. The end result could be a new set of Operating System and processor benchmarks which give an indication of how well the CPU can be multiplexed between a number of concurrent tasks.
This project is research. It requires some good experimental computer science, but needn't be particularly difficult for someone with reasonable knowledge of C and the operation of microprocessors.
|Simple Super-Scalar CPU design||Hardware||1999||Student Projects||NetOS|
Contact: Ian Pratt email
Modern CPUs such as the Pentium II, R10000 and Alpha 21264 use a technique called `dynamic execution' to enable them to execute instructions out-of-order relative to the order they appear in the program. Instructions are executed when all of their input operands become ready. This technique enables such processors to seek out Instruction Level Parallelism in the code, and hence execute multiple instructions in a single clock cycle.
The aim of this project is to write a Verilog implementation of a dynamic execution CPU that executes a simple instruction set. The Verilog simulator can be used to `execute' short programs on the CPU, enabling correct behaviour to be verified, and number of execution cycles to be counted. The design should be modular, to enable different numbers of functional units to be experimented with, along with different dynamic-scheduling algorithms.
A further aim of the project will be to use a synthesis tool to generate a structural net-list for the design. This can then be examined to understand the number of transistors required by different parts of the design, and to assess what the critical paths that would limit the clock rate are.
This could be a really good project. There are endless extensions, features and experiments that could be conducted with the virtual CPU that would allow for a very interesting dissertation.
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