4-bit Twisted Ring Counter
Created: Jan 28, 2014
No description available.
The ring counter is useful in hardware logic design such as Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA). The ring counter is also ideal in creating simple finite state machines.
The diagram is a circuit of a 4-bit twisted ring counter which can function in 4 different modes, namely: Serial-Input-Serial-Output (SISO), Serial-Input-Parallel-Output (SIPO), Parallel-Input-Serial-Output (PISO), and Parallel-Input-Parallel-Output, by applying Qo to the serial input, the resulting circuit will be a twisted ring or a Johnson Counter. Twisted ring counters are shift registers where the output from the last flip-flop becomes the input of the first flip-flop; it will result in a closed loop circuit which recirculates the data bits around a continuous loop for every sequence state.
The circuit is composed of NAND gates, flip-flops, voltage sources, and clocking system. The NAND gates are incorporated in a Quad-2 input NAND Gate integrated circuit with part number 74ABT00D. The NAND gates receive the inputs from D0, D1, D2, and D3. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. The circuit also uses JK flip flops as the memory element. For this circuit, the dual JK flip-flop IC with part number 74HC109D is used. Two 74HC109D chips are used since the circuit needs four JK flip-flops and each IC has two JK flip-flops in it. The 74HC109 is a dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The supply voltages used to power the ICs are set at 5V for 74ABT00D IC and -1.5V for the 74ABT00D IC. The clocking system connected to the flip-flops provide synchronization pulses and timing for the circuit.