Issue No.08 - August (1994 vol.43)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.295859
<p>This paper describes a new method for polynomial interpolation in hardware, with advantages demonstrated by its application to an accurate logarithmic number system (LNS) arithmetic unit. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy can be shown to always use fewer words of memory than an optimized polynomial with stored polynomial coefficients. Interleaved memory function interpolators are then applied to the specific goal of an accurate logarithmic number system arithmetic unit. Many accuracy requirements for the LNS arithmetic unit are possible. Although a round to nearest would be desirable, it cannot be easily achieved. The goal suggested is to insure that the worst case LNS relative error is smaller than the worst case floating point (FP) relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second order polynomial interpolator including approximately 91K bits of ROM. This arithmetic unit has better accuracy and less complexity than previous LNS units.</p>
interpolation; approximation theory; polynomials; digital arithmetic; error analysis; read-only storage; interleaved memory function interpolators; accurate LNS arithmetic unit; polynomial interpolation; storage requirements; accuracy requirements; round to nearest; floating point; ROM; 32 bit; 91 kbit.
D.M. Lewis, "Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit", IEEE Transactions on Computers, vol.43, no. 8, pp. 974-982, August 1994, doi:10.1109/12.295859