Following are a few questions posed to Federico Faggin, intended to
further clarify the early history of the microprocessor.
Q.: When did you start your employment with Intel?
F.F.: On April 3, 1970
Q.: Who hired you and who supervised your work?
F.F.: I was hired by and I reported to Leslie [Les] Vadasz, who was the manager of the MOS Design group in the R&D organization. At that time, the only other major R&D group was the Bipolar Design group, headed by H.T. Chua. All MOS chips were designed in Lesí organization. Les and H.T. reported to Andy Grove, the vice president of Operations. Andy reported to Gordon Moore, the executive vice president and co-founder of Intel. The other co-founder was Bob Noyce. Although Bob Noyce was officially the President and CEO of Intel, Bob and Gordon in practice shared the office of the president.
Q.: How big was Intel?
F.F.: In April 1970, Intel had approximately 150 employees, most of them operators working in the wafer fabrication and chip assembly lines. The entire R&D organization was about 20 people
Q.: Was Ted Hoff working in R&D?
F.F.: No. Ted Hoff was the manager in charge of the Application Research group, reporting to Gordon Moore. That group was comprised of two engineers (Stan Mazor and Tor Lund) and a few technicians. The primary purpose of the Application Research group was to explore new application areas for Intel's memory chips.
Q.: What was your first project?
F.F.: I was hired to be the project leader for the "Busicom project." In 1969, Busicom had developed the design for a family of calculators and they wanted Intel to transfer their design into silicon. Their design was a special-purpose, CPU-based machine with macro-instructions, ROM and shift-register read-write memory, partitioned in 7 different chips. The CPU function was distributed onto three separate chips. When Ted Hoff saw the Busicom design, he was surprised by its complexity and proposed a simplified architecture based on a more general-purpose, single-chip, 4-bit CPU, and separate chips for ROM with I/O, RAM with I-/O and shift register. After the basic architecture and specification of this four-chip set, called MCS-4, was completed, the project was transferred to the MOS Design group for implementation.
Q.: How were custom circuits developed in those days?
F.F.: For a typical custom design, the customer usually provided a verified logic design to the MOS vendor for implementation in silicon. The semiconductor company would then translate the customerís logic design into appropriate MOS circuits, do the chip layout, create the masks, the customized testing software and finally produce the chips for the customer. Companies doing MOS custom chips over a number of years had developed a design methodology and a number of pre-characterized circuit building blocks to aid in error-free and rapid chip development. The original design that Busicom wanted Intel to translate into seven custom chips was accordingly already designed, and it was built and verified to be correct at the logic gate level. Hoffís proposal, however, was only conceptual and no logic design or verification had been done. Since Intel was dedicated to memory chip design, it had no experience with random logic chip design; it had no design methodology and no pre-characterized circuit building blocks. Furthermore, the style of design required with silicon gate technology was quite different than random logic with metal gate, for which methodologies already existed. The characterization and production testing required testers and testing methods that Intel also didnít have. The day I joined Intel, I had in front of me the task of performing the entire logic, circuit and layout design of the four chips, characterizing and transferring them to production, in six months. Thatís the schedule Intel had agreed with Busicom six months earlier, but no work had been done since then! I also ended up designing and building the characterization and the wafer sorting testers as well, while the final-test tester was being purchased.
Q.: How much help did you receive from Hoff, Mazor and other Intel personnel?
F.F.: After completing the product specification in October-November 1969, consisting of the basic block diagram of the four chips and the instruction set of the CPU, Hoff considered his job done and had not been further involved with the project since that time. When I joined Intel, Stan Mazor, who helped Ted with the product specification, described the project to me, gave me the existing documentation and remained available for questions. Since neither Stan nor Ted knew how to design MOS circuits and none of the logic design of the microprocessor had been done, their help in the implementation was near zero. I also found a few problems at the architectural level that I had to solve by myself. Vadasz, my direct supervisor, was entirely preoccupied with the first 1k-bit dynamic memory design (the 1103) serving the primary business direction of Intel, which was semiconductor memories, and felt that the Busicom project was an unwelcome diversion imposed by top management. This feeling was even more forcefully shared by Andy Grove, Lesí boss. Furthermore, Vadasz had no experience with logic design and random logic chips, therefore he could not guide me, and there were no other design engineers who knew about random logic whom I could ask for guidance. I was entirely on my own, with only minor support from the personnel department to find a couple of layout draftsmen. The entire responsibility for designing and managing the project rested on me.
Q: Did you work for or with Ted Hoff on the design/development of the circuit family?
F.F: No. I never worked for or with Ted Hoff on the 4004 and the other chips of the Busicom project. In fact, I only asked him once, soon after I joined, a question about an architectural issue that seemed to be wrong and for which Stan had no explanation. He answered curtly: "Itís your project now. You solve your own problems!" I ended up figuring out the solution and correcting the architecture and I had no further exchange with Hoff throughout the duration of the project.
Q: Did Mazor work for you or with you on the MCS-4 implementation?
F.F.: No. Stan Mazor reported to Ted Hoff, not to me, and he helped him on the architecture definition that was completed around October-November 1969. After that time, Mazor made no further contributions to either the logic design, the circuit design or the layout of the first microprocessor.
Q.: What were the other major MOS projects going on at Intel in 1970?
F.F.: The most important project for the future of the company was the 1103, the first 1k-bit dynamic memory, using 3-transistors per memory cell. Next was the 1702, a 2k-bit EPROM, invented and designed by Dov Frohman. The 1702 was the world's first non-volatile, electrically programmable, UV-erasable ROM. Then there was a 512-bit shift-register, adding to Intelís shift registers family of products. Finally, the 1201, an 8-bit microprocessor, assigned to Hal Feeney who was trained in metal gate technology, had already started a few weeks before I joined Intel. The 1201 was a custom design for Computer Terminal Corporation (which later became Datapoint) based on a CTC architecture. The 1201, eventually called 8008, was however suspended after a few months of work. The project was later assigned to me, at the completion of the 4004. Using the design methodology I developed for the 4004, and following the example of the 4004, Hal Feeney did the detailed design of the 8008 under my supervision.
Q.: What were the products Intel was producing in early 1970?
F.F.: Intel had a couple of bipolar memories, consisting of a 64-bit static RAM and a 1024-bit ROM, and a few MOS chips: the 1101(a 256-bit static RAM) and a family of MOS dynamic shift registers. The bipolar memories were not particularly competitive since Intel had no unique bipolar process technology, and the 1101 was too slow, too power hungry and too expensive. The only products that were selling well were the shift registers. They were pin-compatible versions of the National Semiconductor line of shift registers. Because Intel chips used silicon gate technology, they were smaller, faster and had a lower minimum frequency of operation than National parts (silicon gate technology made possible lower junction leakage than metal gate technology). Therefore Intel chips could advantageously replace National chips at the same price and in the same system.
In those days, solid-state, read-write memory was realized with MOS dynamic shift registers, used in computer terminals and in calculators (thatís why the Busicom CPU was based on shift register memory, instead of RAM like all other calculators of the day.) The lack of early commercial success of Intelís RAM memory chips forced Intel to develop shift registers and also to entertain a number of custom chip designs to make up for the revenue shortfall. Custom chips, like the Busicom chips and the 1201 were considered as "fillers," by Intelís management, while waiting for the memory business to grow.
Q.: Was there anything unique about the 4004?
F.F.: The architecture of the 4004 was a fairly straightforward register-based architecture with an address stack, typical of small CPUs of the day (in fact, it was very similar to the architecture of the Datapoint terminal CPU -- independently developed by Computer Terminal Corp., at about the same time Ė which became the architecture of the 8008.) The 4004, however, operated on 4-bit data words, contrary to the 8-, 12- or 16-bit words of most other small CPUs. This was done to minimize the number of transistors required for its implementation, taking advantage of the fact that the target application was calculators. The 4004 instructions were stored in ROM memory, while data was stored in separate register memory. The addressing of the data memory was rather cumbersome. The most unusual feature was the use of a 4-bit bus where addresses, instructions and data were multiplexed. This choice was determined by the requirement that all the chips of the 4000 family be packaged in a 16-pin, dual-in-line (DIP) package. At that time Intelís management had decided that all its chips had to be packaged in 16-pin DIP packages for obscure reasons. This "feature" of the 4004 actually cost a major speed penalty since 5 clock cycles were required to fetch and execute an instruction (3 cycles to send the 12-bit address and 2 cycles to fetch the 8-bit instruction.) The other concession to the intended calculator application was the existence of an instruction to convert the content of the 4-bit accumulator from binary to decimal. Overall, the most important contribution of the Hoff-Mazor team was to create a rather economical architecture by leaving out all unnecessary baggage, but at the cost of rigid ROM/RAM partitioning and an awkward addressing scheme for data stored in RAM.
Q.: Why didnít other companies develop a microprocessor?
F.F.: There were other companies developing MOS CPU chips: Lee Boysel, at Fairchild, had conceived a CPU, using a few MOS chips with four-phase logic, and he left the company in 1968 to start Four-Phase Systems, Inc., where he implemented and commercialized an entire computer system in 1970, based on that simple CPU. That CPU, however, was not a single chip and was never commercialized separately; it was part of an entire computer system, sold as a system. In 1970, another microprocessor project was going on at Texas Instrument, based on the Computer Terminal Corporation architecture. This was a single chip, exactly like the 8008, and was intended as a custom design for CTC. That chip was completed in mid 1971, only months after the 4004 was completed and sold to Busicom, and was also described in the press by Texas Instrument. Vic Poor, the VP of Engineering of CTC, told me in a private communication that the TI chip did not work and it was never used by CTC, nor was it introduced in the market. Had that chip functioned before the 4004, it would have been the worldís first microprocessor. Another company developing a microprocessor in 1970 was Rockwell International. Rockwell had a MOS operation in the Los Angeles area, specialized in random logic with four-phase design, aided by internally developed computerized design tools. Rockwell had developed the worldís first commercial chip set for hand held calculators for the Japanese Sharp Corp. in 1968. In 1971, they announced the PPS-4, a chip set similar to Intelís MCS-4 with a single-chip microprocessor at its heart. These facts show that there was a race going on in the market and Intel was the winner because of the timely and flawless implementation of the 4004 before the competition, and not because of the novelty of the idea or the uniqueness of the architecture. To make a microprocessor viable in 1971, it was necessary to design in a single chip a CPU with an instruction cycle of better than 10 microseconds, a maximum power dissipation of less than 1 Watt and a manufacturing cost of less than $5-10. Any implementation outside of these targets would not be commercially successful. It was the silicon gate technology that made possible to achieve such objectives. In 1970, only Intel and Fairchild had the silicon gate technology. Fairchild chip designers, however, were proficient in designing metal gate MOS random logic chips and had not fully appreciated the advantages of the silicon gate technology, despite my urgings.
Q.: Was Intel enthusiastic about the microprocessor?
F.F.: Only a few people were, and only as custom circuits. There was no plan to commercialize microprocessors beyond the specific customers for which they were designed. Intelís mission was semiconductor memory chips. Custom circuits, not to mention microprocessors, were seen as an unnecessary diversion by Andy Grove and Les Vadasz, my boss. The decision to develop custom circuits was made at the top because the revenues of semiconductor memory chips were not growing as fast as expected. Intel, however, had no engineering infrastructure and no commitment to the custom circuit business. In upper management only Bob Noyce and Bob Graham, who was then the VP of marketing, were favorable to the microprocessor, the rest of Intel was either indifferent or hostile.
Q: What was your biggest challenge in the development of the 4004?
F.F.: It was the lack of any design methodology and engineering infrastructure for the design of complex random logic integrated circuits. Other MOS semiconductor companies, experienced in random logic design, had a methodology based on metal gate MOS technology. Silicon gate technology, however, was sufficiently different from metal gate to require many important changes from the existing methods and Intel had not developed such infrastructure because the design of memory chips did not require it. Furthermore, nobody at Intel had experience in random logic design. I was completely on my own. I could have been totally discouraged because the 4004 was much more complex than anything I, or anybody else, had designed before, but I was young and confident and I wholeheartedly embraced the challenge. I started by developing the basic design rules and the core building blocks of the methodology for random logic design with silicon gate. This new methodology, which can be called "Silicon Gate Structured Design Method," did not exist before at Intel nor anywhere else in the world, and it allowed the design of random logic chips in a power-efficient, area-efficient and time-efficient manner. It required the use of Bootstrap Load in Silicon Gate and Buried Contact (I came up with both ideas at Fairchild Semiconductor, where I developed the original Silicon Gate Technology, and where I also successfully implemented them) with many other design innovations. The methodology employed a number of rules based on graphic design that made use of normalized, static and dynamic transistor characteristics to find the proper transistor sizes, according to the speed requirement, to minimize power dissipation. With this method it was possible to rapidly and correctly size the devices, bypassing computer simulation, because the graphics were based on measured data from actual transistors and not from equations. I also developed techniques to asses the sizes of major building blocks and to draw the circuit schematic directly from the logic equations, entirely bypassing the logic design, and in a way that would reflect the actual layout, facilitating the creation of a dense and correct chip layout. With the assistance of Busicomís Masatoshi Shima, I developed a way to do the control logic in a structured way. It was done in 3 levels: slow signals were combined first, followed by intermediate speed signals at the second stage, and finally clocking the results into the specific control lines going to the various building blocks. In this manner, the whole information would flow properly, in the shortest time and with lowest power dissipation, from the instruction decoder all the way to the various functional blocks: register file, ALU, internal bus control, etc.
Q.: What role did Shima play in the development of the chips?
F.F.: Shima was the Busicom engineer responsible for the development of the calculator firmware. His visit at Intel in early April, 1970 was intended to check the logic design of the 4004 together with the progress of the other chips, according to the project schedule agreed between Busicom and Intel. However, Intel had made no progress since the signing of the agreement six months earlier. Because of the delay, Shima ended up staying at Intel until October 1970 to help me with the project. Shima assisted me in all the phases of the project and over time learned how integrated circuits were designed. His help was particularly valuable in checking the logic design, the layout and the rubylith artwork for the various chips. He also did most of the logic design of the 4004 under my supervision, applying the methodology I devised.
Q.: Was the first microprocessor intended for general use?
F.F.: No. The 4004 was primarily intended for calculators and for other calculator-like products (cash registers, banking teller equipment, etc.). There was no plan to broadly commercialize the 4004. As a matter of fact, Busicom had the exclusive license for the use of the 4004.