The Rio Rancho fabrication facility, called Fab 11X, will contain more than 1 million square feet and 200,000 feet of clean room space, the area where chips are made. The facility is designed to process wafers with 300-millimeter diameters.
These wafers have a surface area that is 225 percent larger than the 200-millimeter wafers that are standard in the industry today, but the 300-millimeter wafers do not cost much more to process. As a result, chipmakers can produce more chips without greatly increasing their bottom-line costs.
The additional factory space, combined with the increased output that will come from 300-millimeter wafers, will give Intel the capacity to produce a wide variety of products, including processors, flash memory, Wi-Fi chips, and chips for telecommunications equipment.
In its biannual conference with investors, Intel executives reiterated its plans to get intochip markets as possible.
"This expansion is the embodiment of our long-held belief that especially in the face of challenging economic times we must continue to invest in new products and manufacturing," Paul Otellini, Intel's president, said in a statement. "As computing and communications devices converge, the need for increasingly complex components with more capabilities will grow."
Although 300-millimeter production will help Intel cut costs, these facilities aren't cheap. The New Mexico facility will cost around $2 billion. In 1965, these facilities cost $1.5 million, according to Dan Hutcheson, CEO of VLSI Research.
"One of the corollaries to Moore's Law is that with every doubling (of transistor count on chips) your equipment costs increase by 50 percent or so," he said in a recent interview.
By the first half of 2004, Intel will have production fabrication facilities in Ireland, Oregon and New Mexico churning 300-millimeter wafers, and one 300-millimeter development facility in Oregon dedicated primarily to research.
The New Mexico facility will initially manufacture chips made on the 130-nanometer process but will convert next year to making 90-nanometer chips. Ninety nanometers refers to the average size of components on the chip.