FPGAs are clearly the go-to technology for prototyping large ASIC/SoC designs. Whether you’re custom-designing your own prototype, using an off-the-shelf prototyping board, or plunking down the really big bucks for a full-blown emulator, FPGAs are at the heart of the prototyping system. Their reprogrammability allows you to get hardware-speed performance out of your prototype orders of magnitude faster than simulation-based methods. If you’re trying to verify a complex SoC or write and debug software before the hardware is ready, there is really no option but an FPGA-based hardware prototype.
There are basically two options for FPGA-based prototyping – simple prototyping boards and emulators. Simple prototyping boards – whether you design one yourself or buy one from a supplier like Synopsys, Aldec, or Dini – are (by far) the less expensive option. They give you maximum performance of your prototype, often allowing “at speed” operation of your prototype, which can be important if you’re doing real-time operations, processing vast streams of data such as video, or booting and testing complex operating systems on your design.
The downside of simple prototyping boards is that you have limited visibility and control of your prototype design and long iteration times when you make a design change and want to re-run your tests. That’s where emulators come in. If you’ve got the (considerable) budget for an emulator, you can get much greater visibility into the internal signals of your design, more control over the operation and debugging of your prototype, and much faster iteration times in making changes and re-running your tests. However, if you’re interested in developing embedded software before the hardware is ready, which usually involves large teams of software engineers, the deployment of emulators can quickly become cost prohibitive. Also, there is typically a performance penalty for all that visibility and control, and most emulators will not be able to operate “at speed” as often as simple prototyping boards.
We are thus left with a tradeoff between better cost and performance with simple prototyping boards versus better visibility, control, and iteration time with emulators.
Tektronix (yep, THAT Tektronix – the one that makes scopes and logic analyzers) has just released a system that closes the gap considerably between prototyping boards and emulators. “Certus” is a new embedded instrumentation product from Tektronix aimed specifically at ASIC prototyping. Coming from Tek, you might be picturing something with a screen, knobs, buttons, and probes. You’d be wrong about that. Certus is a completely virtual product – consisting of IP that you include in your design – that helps with visibility, control, and iteration time (the exact areas we identified where prototyping boards are weaker than emulators).
Typically (without Certus), if you’re using a simple FPGA prototyping board, your primary tools for getting visibility into the signals in your design are the embedded logic analyzer tools from your FPGA company, such as ChipScope (Xilinx) and SignalTap (Altera). These tools are designed for debugging FPGA designs, so they’re not a perfect match for debugging an SoC prototype design – which can sometimes be partitioned across multiple FPGAs. They generally require you to specify up-front which signals you’d like to monitor, and then your FPGA design is synthesized and placed-and-routed so that those signals can be watched. If you want to monitor different signals, you have a re-run of synthesis and place-and-route (which can take hours) to get monitoring on the new signals. This means you need to know which signals to monitor before you do your initial compile (and we all know exactly which signals will be involved in our first bug, right? Uh, NO.) It also means that you may have problems with the partitioned design across multiple FPGAs, signals that cross clock domains, and other limitations.
Every time you find a bug, you probably need to re-build your design. With a large FPGA prototype, that usually ends up being a “go home for the day” situation because the remainder of your workday (and often into the night) will be spent on the new synthesis->place-and-route run.
Certus is a lightweight set of IP blocks designed to solve these problems. Tektronix claims that the overhead is about one LUT per signal. With Certus 2.0 (announced today), you can capture essentially all of the signals inside your FPGA for debug – without any special probes or additional hardware. That means that you won’t have to re-build your design in order to observe a different set of signals, and you get something very close to emulator-level visibility of your design using a simple FPGA-based prototyping board.
The company claims that by allocating somewhere in the range of 5%-10% of your FPGA LUTs to their debug IP, you will be able to automatically identify all critical design components such as flip-flops, critical interfaces, and state machines, and then intelligently select a subset to monitor (using what the company calls their “Optirank algorithm”). Then, you can trace any subset of signals without having to re-build your FPGA design.
Certus uses on-chip memory (FPGA block RAM) to store trace data, and it takes advantage of lossless compression and data-packing to maximize the amount of information that can be stored in the available RAM. Tektronix cites examples such as an AMBA AHB Linux Boot – using 2 block RAMs, storing 3.1M clock cycles of trace, with a claimed compression ratio of 2,873X. This kind of compression, combined with the ability to do targeted-event data capture, should allow you to do true system-level trace capture with Certus.
The cockpit for the system runs on an attached PC, and it gives a time-correlated view of your design – even across multiple FPGAs. This is something you clearly cannot do with off-the-shelf FPGA-vendor logic-analyzer IP, and this feature is something that puts Certus-enabled prototyping boards in the realm of much more expensive emulation systems.
While this may not be the kind of product that people traditionally associate with Tek, it is exciting to see the company putting energy into the FPGA-based prototyping business, particularly with a product that has this much potential to change the landscape.