The CLCxPOL Register, contained in the Configurable Logic Cell (CLC), controls the polarity of the data gating outputs and also the polarity of the CLC output.
CLC Data Gate Outputs
The table below summarizes the basic logic that can be obtained in a gate by using the gate logic select bits.
The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. The output polarity is controlled by the CLCxPOL register.
CLC Output Control
The output of the entire CLC can also be inverted in the CLCxPOL register by setting the 7th bit in the register. Clearing the bit will make the CLC output non-inverted.
1 - Invert the CLC output
0 - Non-invert the CLC output