Once again, the semiconductor industry finds itself at the dawn of a new process generation for high-performance logic. Intel Corp.'s 90-nanometer Prescott MPU first appeared early in 2004. This time, it is 65 nm, and once again, Intel leads the pack.
The introduction of 90-nm process technology two years ago represented the launch of some innovations manufactured for the first time in high volume. These new features were all centered on enhancing the mobility of charge carriers in the channel region of MOS devices. The most talked-about and significant enhancement was strained silicon.
Straining the silicon channels allowed the vendors to cheat some of the physical scaling limits while staying true to the Moore's Law vision. Strained silicon offers a way around the brick wall at 32 nm and below. It also gave semiconductor fabs an easier and cheaper alternative to meeting the performance requirements dictated by Moore's Law. With exceptional foresight, the Semiconductor Industry Association had already highlighted mobility enhancements like strained silicon on its road map, the International Technology Roadmap for Semiconductors (ITRS).
Several means of enhancing electron and hole mobilities were used at 90 nm. There were also different methods of straining device channels. Electrons and holes react differently to physical effects in the silicon substrate. Tensile strain improves electron mobility and, hence, NMOS drive current, while compressive strain increases hole mobility to improve PMOS transistor performance.
It was well-known in the industry that many of the features required in advanced silicon manufacturing produced unintentional strain in deep-submicron devices. For example, standard high-density plasma fill for shallow-trench isolation imparts a tensile strain to the channel. Nitride stops for contact etch produced similar effects. Talented process engineers wasted no time experimenting with the various deposition recipes to control the strain effects.
IBM Corp. engineers tailored the strain of the nitride layer deposited after gate definition to enhance NMOS performance. Later in 90-nm development, this so-called stress liner was modified to create compressive stress in the PMOS devices. The IBM approach of straining both transistor polarities with the nitride etch stop layer became known as dual stress liner. While the stress liner was the method that IBM publicized, it is difficult to know what other techniques, including trench fill, may have also increased drive current and reduced delays in IBM devices.
Of course, IBM's 90-nm ICs continued to use silicon-on-insulator (SOI) substrates. IBM was the only high-performance logic manufacturer using SOI at 90 nm, as seen in the Power PC 970FX .
Intel seemed to plant two feet firmly into the future by using selective epitaxy of silicon germanium in PMOS sources and drains to compressively strain the p-channel. The SiGe deposition gave Intel better control over the strain placed on the p-channel. The SiGe deposition for PMOS transistors had the additional benefit of raising the source and drain regions, which reduced parasitic contact resistance, thereby also improving drive current.
One might argue that there was a down side to Intel's adoption of selective SiGe epitaxy. It was more costly than the other alternatives, since it added a completely new process to the existing flow. It also meant that Intel delivered a technical first: It used nickel for the metal silicide. Cobalt does not get along well with germanium, which caused Intel to change its process. Nickel silicidation of the gates is an improvement over cobalt, however, and is required at 65 nm. Intel was actually getting ahead of the game to prepare for future generations.
Texas Instruments Inc. took a different approach to mobility enhancement for increasing PMOS drive current. The company's 90-nm devices were laid out with a new wafer orientation. The wafers were turned so that the channels of the PMOS transistors were oriented along the preferred plane for maximum hole mobility. It may not seem as if this scheme would provide a huge benefit, but the proof is in the performance. Semiconductor Insights' independent benchmarking of transistor performance reported the on/off current ratios of TI devices to be the best in the industry at 90 nm.