The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.
Who should attend?VHDL users with intermediate knowledge of VHDL
- Designing with VHDL course or equivalent knowledge of modeling, simulation, and RTL coding
- At least 6 months of coding experience beyond an introductory course
• Vivado® Design or System Edition 2015.3Hardware:
- Demo board: None*
Skills Gained: After completing this training, you will be able to:
Write efficient and reusable RTL, testbenches, and packages
- Create self-testing testbenches
- Create realistic models
- Use the text IO capabilities of the VHDL language
- Store simulation data dynamically
- Create parameterized designs
- Create parameterized code for design reuse
Lab 1: Flexible Functions – Construct and use predefined attributes to build functions and procedures that automatically adjust to the size of the passed arguments as well as creating a reusable module with unconstrained ports.
Lab 2: Linked Lists with Access Types – Create linked lists to capture arbitrarily large data sets. Also included in this lab is a reusable helper package for managing singly linked lists.
Lab 3: TextIO Techniques – Load memory for synthesis via a text file using the TextIO extensions for std_logic and std_logic_vector as provided by the std_logic_TextIO package.
Lab 4: Creating Real-World Simulations – Create spread-spectrum clocks with jitter and other real-world factors. Model board and behavioral component delay.
Lab 5: Supporting Multiple Platforms – Effectively use configuration statements, conditional generates, and scripts to build variations on VHDL themes.
Lab 6: Implementing Fixed and Floating Point Numbers – Construct a simple fixed point math example and compare to the IEEE_PROPOSED fixed and floating point models.
1. Review of Current Knowledge
2. Simulation Concepts
3. Advanced Data Types
4. Subprograms and Design Attributes
5. Lab 1: Flexible Functions
6. Access Type Techniques and Blocks
7. Lab 2: Linked Lists with Access Types
8. Utilizing File IO
9. Lab 3: TextIO Techniques
10. RTL Design and Xilinx
11. Cool Stuff with VHDL
12. Lab 4: Creating Real-World Simulations
13. Supporting Multiple Platforms
14. Lab 5: Supporting Multiple Platforms
15. Non-Integer Numbers
16. Lab 6: Implementing Fixed and Floating Point Numbers
17. Course Summary