This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: . 2. Familiarity with Verilog logic design . . Wakerly Material Covered Chapter 4 – Combinational Logic Design Principles Section 5.4 -- Verilog Possible Problems Karnaugh maps 4- or 5-variable SOP or POS Regular or with don’t cares Hazards Verilog design of simple SOP or POS circuits Any problems like assigned homework problems Test Format 4-6 Problems, some with multiple parts 1 2...
View Full Document
- Spring '07
- Logic, Boolean Algebra, Karnaugh map, Don't-care, Logic in computer science