Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Case Study: Sizing A Design
Last Edit July 22, 2001
For cell usage, timing, power, and added ground requirements, the basic OE14S solution is the best pro-posed so far.
Table A-7 OE14S Solution
Table A-8 OE14S Solution
This version used GT87D instead of a GT08L. It uses GT60S macros in the gate tree instead of GT60L macros. Do the MUX and reset buffer trees need S-macros or could L-option macros be used? (Watch it - the options have different maximum frequency of operation numbers! This is often overlooked in choosing options.)
Table A-8b Macro Occurrence Report Continued
Add a design objective to reduce power to 5 Watts or as close to it as possible and modify this circuit using the latest library information. The frequency of operation requirement remains.
This same exercise was used in the AMCC training classes through several library releases. This problem, or one close to it, was actually used for over eleven years with several technology libraries, bipolar, Bi-squared MOS and CMOS. It demonstrates nearly 85% of the array design rules.
Today's designers would create this circuit in Verilog or VHDL and a control script for the synthesis tool. Constraints can drive area reduction, speed improvements or power reduction. The script can also set the priority for the different design constraints.