Image text transcribed for accessibility: Connect the buffer output to the input of the 145106, and change the divide-by-N value while observing the dc value at pin 7 of the 145106. This dc value should increase for divide-by-N values above 58 and decrease for values below 58. Show that you understand these results. Construct and connect the LP filter. Calculate the cutoff frequency of this filter and discuss why it was set at this value. Construct the upper, two-op-amp buffer/level shifter. Do not connect either end of this circuit into the overall PLL until the buffer/level shifter is fully operational. This circuit should cause a 0 V input to become a high output and a + 10 V input to become a low output, which is inversion and level shifting. Discuss the operation of this circuit. Connect the entire PLL circuit except pin 7 of the 565. Ensure that the entire circuit is working without connecting to pin 7 of the 565 by changing the 565 free-running frequency and noting the dc voltage value that occurs at the input to the 565. Discuss the result of this test and your understanding of the operation of the circuit. Completing the Circuit Reset the VCO free-running frequency to 100 kHz. Set the divide-by-N value to 58. Explain why this number is significant. (NOTE: You may need to break the circuit, which resets it. if the value of N that you set is too high or low. Keep the connection to pin 7 of the 565 easily accessible, since this is a good place to break the loop.) Connect the complete PLL circuit. Vary the divide-by-N input to 10 different values within the operating range of the 565 (approximately 23 to 157), and make a chart of the input digital number, the calculated frequency, and the actual output frequency from a frequency counter. Make a graph of this chart. Comment on the linearity of the resulting graph. Determine the limits of the frequency ranges available by changing the divide-by-N number until the calculations no longer match the actual output of the VCO. Record and comment on these limits. Questions/Problems Design a similar digital frequency synthesizer using higher output frequencies with the MCI648 VCO. Calculate the divide-by-N value required to produce a 1.190 MHz frequency using a 10.24 MHz crystal on the 145106 with a divide-by-1024 crystal circuit. What is the range of frequencies directly usable with this configuration?