A consortium has introduced a design kit for low-power 45 nm process technology. Do we need it so soon?
In a society where bigger is almost always better, the semiconductors industry acts as a contrarian. To the electronic industry smaller is macho. Driven by nature's imperative to reach the ultimate smallness, eager to play with individual atoms and electrons, and fearful of the ultimate curse should they dare not to follow Moore's Law, semiconductor foundries continue their relentless march toward the next process node.
And so, a consortium of companies that include IBM, Chartered, Infineon, and Samsung has just announced the first commercially available design kits for low-power 45 nm process. The consortium expects to be in production with the new process by the end of 2007. There is no question that the introduction represents a significant technological achievement, but it is too much too soon?
Various industry projections show that less than 300 new designs will target the 65 nm process node this year. The majority of new designs targets either 130 or 90 nm processes, and you can still find many mixed signal designs fabricated with either 180 or 250 nanometer processes. Most fabs that handle 300 mm wafers have just come on line this year to support the 65 nm process and these same fabs are the ones that will also have to run the new 45 nm process, at least as far as this four manufacturers are concerned. It is estimated that the new process can offer up to 30% greater performance than 65 nm, a very attractive number to system designers. But I am more interested in total system performance than device performance. And the rest of the components in the devices I own will not see that much of an increase. So which designs will use it? Memories and programmable logic are the obvious candidates, while IDMs like Intel and AMD will use the new process to manufacture multicore microprocessors with lots of on die memory. And there is still room to improve graphics, but how much is really needed? It came as a surprise to the technocrats that Japanese teenagers did not show much interest in watching TV programs on their cell phones. Even the most gadget hungry consumer class has its limits. With one exception, compute intensive applications do not need to be portable and, more importantly, there is no need to have one in every household. The exception is portable gaming. I concede that should someone develop something that looks like a laptop, because I want excellent graphics and cannot stand a small screen, and allows me to play all of the games offered by the Xbox or Nintendo, and would also let me keep addresses and notes, I would buy it. But this is not even at the top of my want list! Let's not forget that, at least in the US, retirees will constitute the largest class with disposable income. The baby boomers want devices that offer basic functions and are simple to operate.
It is a good bet that all designs that are today targeting the low power 65 nm node will move to the new 45 nm node. But who will take their place, and in what time frame? The EDA industry has yet to properly finish developing and deploying tools to support 65 nm process technology. It will have to invest in tools for 45 nm before it has fully recovered its 65 nm investment. Is this really the way to increase market size and improve margins? The major barrier that keeps design companies committed to 90 nm is the cost of uncertainty associated with 65 nm designs. it takes a significant commitment to change methods both in engineering and management to take the leap from 90 to 65, in spite of the reassuring messages broadcast by the foundries. Systems companies need a very good market imperative to convince them to take the risk, both in terms of manufacturing costs and re-spin costs, before they decide to move. Will 65 nm be the Pluto of the semi industry, a minor-node orbiting between 90 and 45? Will the fabs look at the 65 nm process as mostly a test tool for 300 mm wafers equipment?
Write to me and let me know what you think.