- Aiming for world's first CMOS UWB radio
- Design verification tools for the nano-scale
- Building scientists their own accelaration pedal
Virginia Tech researchers have successfully implemented analog ultra-wide band (UWB) radio components in a CMOS process, which typically accommodates only digital circuits. The CMOS process allows low-cost implementation and low-power dissipation. The radio components are a major milestone toward the goal of producing the world’s first CMOS single-chip UWB radio.
Test fixture for a CMOS UWB radio being developed by a Virginia Tech team aiming to build the world's first CMOS single-chip UWB radio. Commercial UWB devises are manufactured with standard SiGe bi-polar technology. Implementing UWB in CMOS would save power and cost, allowing both digital and analog circuits on a single chip.
Compared to traditional narrowband radio communication systems, UWB uses narrow pulses that occupy a wide bandwidth. The technology has both communications and radar potential in a variety of applications including wireless personal area networks (WPANs), home networking, sensor networks, through-wall imaging, and ground penetrating radar.
Several research groups worldwide are pursuing development of a CMOS UWB radio however, the wideband nature of UWB pushes the physical limits of CMOS. As a result, commercial UWB radios to date have been implemented in SiGe, a more expensive, higher power process. In order to include digital features, UWB radios typically employ two chips: a CMOS chip for digital functions and a SiGe chip for analog functions.
The Virginia Tech VLSI for Telecommunications (VTVT) group recently became one of the first groups to successfully fabricate and test key blocks of UWB radios in CMOS. The group hopes to develop the world’s first complete CMOS UWB solution by the close of the year. The target data rate is 220 Mbps at a 10 meter distance. The effort is sponsored by the Electronics and Telecommunications Research Institute (ETRI).
This photo shows the four key building blocks of a UWB radio.
The group uses an innovative iterative design and testing process because of the inadequacy of current simulation models for UWB implementation. Dong Ha, VTVT director, explained, “SPICE simulations are insufficient to estimate the performance of CMOS in this high-frequency region. Since we cannot accurately predict performance, it is essential to measure the performance of fabricated chips.” He continued, “We fabricate test chips about every six months, which is a rare opportunity for a university research team. We are very fortunate to collaborate with ETRI, which not only pays for the fabrication cost, but also provides great assistance from the design review to the final testing.”
An increase in nano-scale products will introduce greater uncertainty and unreliability into circuit and system design, according to ECE’s Sandeep Shukla. Shukla is working to develop reliability techniques for defect-tolerant architectures at the nano scale. “With uncertainties being rampant in nano-technology, we can only rely on the measures of the probability that a transistor will behave correctly, or a logic gate function correctly," he said. Engineers will have to build redundancy in the design, but increased redundancy may lead to reduced reliability. His team is using formal methods applied to probabilistic models and their verification. The goal is to build tools for designers to model the probabilistic nature of defects and automatically evaluate the reliability-redundancy trade-offs.
James Armstrong is developing automatic acceleration tools for scientists who are not computer experts and need to model complex physical and biological processes. Working with researchers in mechanical engineering, he has implemented a cascading cellular automata algorithm that they developed by using FPGAs to speed up scientific modeling and simulation. Shown above are results from modeling the chemical reactions in a curing process in a material consisting of a matrix with embedded, separated particles. “Most approaches to acceleration with physical equations rely on super computers,” Armstrong said. “Our technique enables a scientist to formulate model equations on a PC and have the solution accelerated locally on a low-cost attached platform.”