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Lavoisier S.A.S.
In Print (Delivery period: 15 days).
Subject to availability at the publisher.
240 p.
This study is an introduction to the use of VHDL logic (RTL) synthesis tools in circuit design. The modelling styles proposed are independent of specific market tools and focus on constructs widely recognized as synthesizable by synthesis tools.
1. About Synthesis. 2. VHDL Concepts. 3. Mapping VHDL to Hardware. 4. Mapping Hardware to VHDL. 5. Design Methodology. 6. Synthesis Standard Environment. 7. Case Study. 8. Appendix. Index.
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