{"repository":{"watchers":1,"pushed_at":"2012/04/09 13:51:45 -0700","has_downloads":true,"has_issues":true,"forks":1,"fork":false,"language":"C++","size":632,"private":false,"has_wiki":true,"created_at":"2012/04/04 18:07:49 -0700","owner":"dgsmith","description":"A simulator for Verilog written in C++","open_issues":0},"actor_attributes":{"name":"Grayson Smith","blog":"graysonsmith.me","type":"User","email":"a8cc47f90f4883e85c2f097d69393902346431fc@graysonsmith.me"},"url":"https://github.com/dgsmith/Verilog-Simulator/compare/0a2c9cdc23...44d250c1eb"}