{"repository":{"homepage":"https://github.com/BigEd/verilog-6502/wiki","watchers":2,"has_downloads":true,"master_branch":"65Org16-master","fork":true,"language":"Verilog","has_issues":false,"has_wiki":true,"forks":0,"size":152,"private":false,"created_at":"2012/02/21 15:25:12 -0800","owner":"ElEctric-EyE","description":"This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL","open_issues":0,"pushed_at":"2012/04/24 06:13:55 -0700"},"actor_attributes":{"name":"Sam Gaskill","location":"NC, USA","type":"User","email":"77908e2a64d232409b511cb56f39e95b56fb82a1@gmail.com"},"url":"https://github.com/ElEctric-EyE/verilog-6502/compare/33faa7be84...91bc8b8b99"}