  Deep learning accelerators address the computational demands of Deep Neural
Networks (DNNs), departing from the traditional Von Neumann execution model.
They leverage specialized hardware to align with the application domain's
structure. Compilers for these accelerators face distinct challenges compared
to those for general-purpose processors. These challenges include exposing and
managing more micro-architectural features, handling software-managed scratch
pads for on-chip storage, explicitly managing data movement, and matching DNN
layers with varying hardware capabilities. These complexities necessitate a new
approach to compiler design, as traditional compilers mainly focused on
generating fine-grained instruction sequences while abstracting
micro-architecture details. This paper introduces the Architecture Covenant
Graph (ACG), an abstract representation of an architectural structure's
components and their programmable capabilities. By enabling the compiler to
work with the ACG, it allows for adaptable compilation workflows when making
changes to accelerator design, reducing the need for a complete compiler
redevelopment. Codelets, which express DNN operation functionality and evolve
into execution mappings on the ACG, are key to this process. The Covenant
compiler efficiently targets diverse deep learning accelerators, achieving
93.8% performance compared to state-of-the-art, hand-tuned DNN layer
implementations when compiling 14 DNN layers from various models on two
different architectures.
