  We present a circuit-compatible compact model of the intrinsic capacitances
of graphene field-effect transistors (GFETs). Together with a compact drain
current model, a large-signal model of GFETs is developed combining both models
as a tool for simulating the electrical behavior of graphene-based integrated
circuits, dealing with the DC, transient behavior, and frequency response of
the circuit. The drain current model is based in a drift-diffusion mechanism
for the carrier transport coupled with an appropriate field-effect approach.
The intrinsic capacitance model consists of a 16-capacitance matrix including
self-capacitances and transcapacitances of a four-terminal GFET. To guarantee
charge conservation, a Ward-Dutton linear charge partition scheme has been
used. The large-signal model has been implemented in Verilog-A, being
compatible with conventional circuit simulators and serving as a starting point
toward the complete GFET device model that could incorporate additional
non-idealities.
