  This paper proposes and evaluates a novel architecture for a low-power
Time-to-Digital Converter with high resolution, optimized for both integration
in multichannel chips and high rate operation (40 Mconversion/s/channel). This
converter is based on a three-step architecture. The first step uses a counter
whereas the following ones are based on two kinds of Delay Line structures. A
programmable time amplifier is used between the second and third steps to reach
the final resolution of 24.4 ps in the standard mode of operation. The system
makes use of common continuously stabilized master blocks that control
trimmable slave blocks, in each channel, against the effects of global PVT
variations. Thanks to this structure, the power consumption of a channel is
considerably reduced when it does not process a hit, and limited to 2.2 mW when
it processes a hit. In the 130 nm CMOS technology used for the prototype, the
area of a TDC channel is only 0.051 mm2. This compactness combined with low
power consumption is a key advantage for integration in multi-channel front-end
chips. The performance of this new structure has been evaluated on prototype
chips. Measurements show excellent timing performance over a wide range of
operating temperatures (-40{\deg}C to 60{\deg}C) in agreement with our
expectations. For example, the measured timing integral nonlinearity is better
than 1 LSB (25 ps) and the overall timing precision is better than 21 ps RMS.
