  The trap-induced hysteresis on the performance of a graphene field-effect
transistor is experimentally diminished here by applying consecutive
gate-to-source voltage pulses of opposing polarity. This measurement scheme is
a practical and suitable approach to obtain reproducible device
characteristics. Trap-affected and trap-free experimental data enable a
discussion regarding the impact of traps on static and dynamic device
performance. An analytical drain current model calibrated with the experimental
data enables the study of the traps effects on the channel potential within the
device. High-frequency figures of merit and the intrinsic gain of the device
obtained from both experimental and synthetic data with and without hysteresis
show the importance of considering the generally overlooked impact of traps for
analog and high-frequency applications.
