  Standard cell libraries are the foundation for the entire backend design and
optimization flow in modern application-specific integrated circuit designs. At
7nm technology node and beyond, standard cell library design and optimization
is becoming increasingly difficult due to extremely complex design constraints,
as described in the ASAP7 process design kit (PDK). Notable complexities
include discrete transistor sizing due to FinFETs, complicated design rules
from lithography and restrictive layout space from modern standard cell
architectures. The design methodology presented in this paper enables efficient
and high-quality standard cell library design and optimization with the ASAP7
PDK. The key techniques include exhaustive transistor sizing for cell timing
optimization, transistor placement with generalized Euler paths and back-end
design prototyping for library-level explorations.
