  Adopting FPGA as an accelerator in datacenters is becoming mainstream for
customized computing, but the fact that FPGAs are hard to program creates a
steep learning curve for software programmers. Even with the help of high-level
synthesis (HLS), accelerator designers still have to manually perform code
reconstruction and cumbersome parameter tuning to achieve the optimal
performance. While many learning models have been leveraged by existing work to
automate the design of efficient accelerators, the unpredictability of modern
HLS tools becomes a major obstacle for them to maintain high accuracy. To
address this problem, we propose an automated DSE framework-AutoDSE- that
leverages a bottleneck-guided coordinate optimizer to systematically find a
better design point. AutoDSE detects the bottleneck of the design in each step
and focuses on high-impact parameters to overcome it. The experimental results
show that AutoDSE is able to identify the design point that achieves, on the
geometric mean, 19.9x speedup over one CPU core for Machsuite and Rodinia
benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx
Vitis libraries, AutoDSE can reduce their optimization pragmas by 26.38x while
achieving similar performance. With less than one optimization pragma per
design on average, we are making progress towards democratizing customizable
computing by enabling software programmers to design efficient FPGA
accelerators.
