  Recent developments in High Level Synthesis tools have attracted software
programmers to accelerate their high-performance computing applications on
FPGAs. Even though it has been shown that FPGAs can compete with GPUs in terms
of performance for stencil computation, most previous work achieve this by
avoiding spatial blocking and restricting input dimensions relative to FPGA
on-chip memory. In this work we create a stencil accelerator using Intel FPGA
SDK for OpenCL that achieves high performance without having such restrictions.
We combine spatial and temporal blocking to avoid input size restrictions, and
employ multiple FPGA-specific optimizations to tackle issues arisen from the
added design complexity. Accelerator parameter tuning is guided by our
performance model, which we also use to project performance for the upcoming
Intel Stratix 10 devices. On an Arria 10 GX 1150 device, our accelerator can
reach up to 760 and 375 GFLOP/s of compute performance, for 2D and 3D stencils,
respectively, which rivals the performance of a highly-optimized GPU
implementation. Furthermore, we estimate that the upcoming Stratix 10 devices
can achieve a performance of up to 3.5 TFLOP/s and 1.6 TFLOP/s for 2D and 3D
stencil computation, respectively.
