  Programmable Logic Devices (PLDs) continue to grow in size and currently
contain several millions of gates. At the same time, research effort is going
into higher-level hardware synthesis methodologies for reconfigurable computing
that can exploit PLD technology. In this paper, we explore the effectiveness
and extend one such formal methodology in the design of massively parallel
algorithms. We take a step-wise refinement approach to the development of
correct reconfigurable hardware circuits from formal specifications. A
functional programming notation is used for specifying algorithms and for
reasoning about them. The specifications are realised through the use of a
combination of function decomposition strategies, data refinement techniques,
and off-the-shelf refinements based upon higher-order functions. The
off-the-shelf refinements are inspired by the operators of Communicating
Sequential Processes (CSP) and map easily to programs in Handel-C (a hardware
description language). The Handel-C descriptions are directly compiled into
reconfigurable hardware. The practical realisation of this methodology is
evidenced by a case studying the matrix multiplication algorithm as it is
relatively simple and well known. In this paper, we obtain several hardware
implementations with different performance characteristics by applying
different refinements to the algorithm. The developed designs are compiled and
tested under Celoxica's RC-1000 reconfigurable computer with its 2 million
gates Virtex-E FPGA. Performance analysis and evaluation of these
implementations are included.
