  Due to cost benefits, supply chains of integrated circuits (ICs) are largely
outsourced nowadays. However, passing ICs through various third-party providers
gives rise to many security threats, like piracy of IC intellectual property or
insertion of hardware Trojans, i.e., malicious circuit modifications.
  In this work, we proactively and systematically protect the physical layouts
of ICs against post-design insertion of Trojans. Toward that end, we propose
TroLLoc, a novel scheme for IC security closure that employs, for the first
time, logic locking and layout hardening in unison. TroLLoc is fully integrated
into a commercial-grade design flow, and TroLLoc is shown to be effective,
efficient, and robust. Our work provides in-depth layout and security analysis
considering the challenging benchmarks of the ISPD'22/23 contests for security
closure. We show that TroLLoc successfully renders layouts resilient, with
reasonable overheads, against (i) general prospects for Trojan insertion as in
the ISPD'22 contest, (ii) actual Trojan insertion as in the ISPD'23 contest,
and (iii) potential second-order attacks where adversaries would first (i.e.,
before Trojan insertion) try to bypass the locking defense, e.g., using
advanced machine learning attacks. Finally, we release all our artifacts for
independent verification [2].
