  Scalable memories that can match the speeds of superconducting logic circuits
have long been desired to enable a superconducting computer. A superconducting
loop that includes a Josephson junction can store a flux quantum state in
picoseconds. However, the requirement for the loop inductance to create a
bi-state hysteresis sets a limit on the minimal area occupied by a single
memory cell. Here, we present a miniaturized superconducting memory cell based
on a Three-Dimensional (3D) Nb nano-Superconducting QUantum Interference Device
(nano-SQUID). The major cell area here fits within an 8*9 {\mu}m^2 rectangle
with a cross-selected function for memory implementation. The cell shows
periodic tunable hysteresis between two neighbouring flux quantum states
produced by bias current sweeping because of the large modulation depth of the
3D nano-SQUID (~66%). Furthermore, the measured Current-Phase Relations (CPRs)
of nano-SQUIDs are shown to be skewed from a sine function, as predicted by
theoretical modelling. The skewness and the critical current of 3D nano-SQUIDs
are linearly correlated. It is also found that the hysteresis loop size is in a
linear scaling relationship with the CPR skewness using the statistics from
characterisation of 26 devices. We show that the CPR skewness range of
{\pi}/4~3{\pi}/4 is equivalent to a large loop inductance in creating a stable
bi-state hysteresis for memory implementation. Therefore, the skewed CPR of 3D
nano-SQUID enables further superconducting memory cell miniaturization by
overcoming the inductance limitation of the loop area.
