  Compiler backends should be automatically generated from hardware design
language (HDL) models of the hardware they target. Generating compiler
components directly from HDL can provide stronger correctness guarantees, ease
development effort, and encourage hardware exploration. Past work has already
championed this idea; here we argue that advances in program synthesis make the
approach more feasible. We present a concrete example by demonstrating how FPGA
technology mappers can be automatically generated from SystemVerilog models of
an FPGA's primitives using program synthesis.
