  Modern technology-independent logic synthesis has been developed to optimize
for the size and depth of AND-Inverter Graphs (AIGs) as a proxy of CMOS circuit
area and delay. However, for non-CMOS-based emerging technologies, AIG size and
depth may not be good cost estimations. Dedicated algorithms optimizing for
more complex cost functions have been proven effective for their specific
target applications yet require time and experts in both logic synthesis and
the targeted technology to develop. In this work, we propose AnySyn, a
cost-generic optimization framework for agile experimentation and prototyping
of various customized cost functions before investing in developing specialized
algorithms. Experimental results show that AnySyn outperforms non-specialized
size and depth optimization algorithms by 14% and 19% on average and achieves
comparable results to specialized algorithms within acceptable CPU time.
