  The use of three extractors, fed by linear feedback shift registers (LFSR)
for generating pseudo-random bit streams is investigated. Specifically, a
standard LFSR is combined with a von Neumann extractor, a modified LFSR,
extended by the all-zero state, is combined with an output logic, which
translates every three bits from the LFSR into up to two output bits and a run
extraction of the input bit stream into single output bits are investigated.
The latter two achieve better efficiency in using bits from the primary bit
stream, the last one reaches 50\%. Compared to other generator logics, the
three extractors investigated are less performant in terms of their
cryptographic strength. However, the focus of this report is on the quality of
the pseudo-random bit stream in comparison to really random bits and on the
efficiency of using the bits of the primary stream from the LFSR and generating
valid output bits, while fulfilling a minimum cryptographic strength only,
beyond that of the pure LFSR.
