  High-quality system-level message flow specifications can lead to
comprehensive validation of system-on-chip (SoC) designs. We propose a
disruptive method that utilizes an attention mechanism to produce accurate flow
specifications from SoC IP communication traces. The proposed method can
overcome the inherent complexity of SoC traces induced by the concurrency and
parallelism of multicore designs that existing flow specification mining tools
often find extremely challenging. Experiments on highly interleaved traces show
promising flow reconstruction compared to several tools dedicated to the flow
specification mining problem.
