  Many performance critical systems today must rely on performance
enhancements, such as multi-port memories, to keep up with the increasing
demand of memory-access capacity. However, the large area footprints and
complexity of existing multi-port memory designs limit their applicability.
This paper explores a coding theoretic framework to address this problem. In
particular, this paper introduces a framework to encode data across multiple
single-port memory banks in order to {\em algorithmically} realize the
functionality of multi-port memory.
  This paper proposes three code designs with significantly less storage
overhead compared to the existing replication based emulations of multi-port
memories. To further improve performance, we also demonstrate a memory
controller design that utilizes redundancy across coded memory banks to more
efficiently schedule read and write requests sent across multiple cores.
Furthermore, guided by DRAM traces, the paper explores {\em dynamic coding}
techniques to improve the efficiency of the coding based memory design. We then
show significant performance improvements in critical word read and write
latency in the proposed coded-memory design when compared to a traditional
uncoded-memory design.
