  Systolic Array (SA) architectures are well suited for accelerating matrix
multiplications through the use of a pipelined array of Processing Elements
(PEs) communicating with local connections and pre-orchestrated data movements.
Even though most of the dynamic power consumption in SAs is due to
multiplications and additions, pipelined data movement within the SA
constitutes an additional important contributor. The goal of this work is to
reduce the dynamic power consumption associated with the feeding of data to the
SA, by synergistically applying bus-invert coding and zero-value clock gating.
By exploiting salient attributes of state-of-the-art CNNs, such as the value
distribution of the weights, the proposed SA applies appropriate encoding only
to the data that exhibits high switching activity. Similarly, when one of the
inputs is zero, unnecessary operations are entirely skipped. This selectively
targeted, application-aware encoding approach is demonstrated to reduce the
dynamic power consumption of data streaming in CNN applications using Bfloat16
arithmetic by 1%-19%. This translates to an overall dynamic power reduction of
6.2%-9.4%.
