  Modern processors such as ARMv8 and RISC-V allow executions in which
independent instructions within a process may be reordered. To cope with such
phenomena, so called promising semantics have been developed, which permit
threads to read values that have not yet been written. Each promise is a
speculative update that is later validated (fulfilled) by an actual write.
Promising semantics are operational, providing a pathway for developing proof
calculi. In this paper, we develop an incorrectness-style logic, resulting in a
framework for reasoning about state reachability. Like incorrectness logic, our
assertions are underapproximating, since the set of all valid promises are not
known at the start of execution. Our logic uses event structures as assertions
to compactly represent the ordering among events such as promised and fulfilled
writes. We prove soundness and completeness of our proof calculus and
demonstrate its applicability by proving reachability properties of standard
weak memory litmus tests.
