  In the ever-evolving landscape of Deep Neural Networks (DNN) hardware
acceleration, unlocking the true potential of systolic array accelerators has
long been hindered by the daunting challenges of expertise and time investment.
Large Language Models (LLMs) offer a promising solution for automating code
generation which is key to unlocking unprecedented efficiency and performance
in various domains, including hardware descriptive code. The generative power
of LLMs can enable the effective utilization of preexisting designs and
dedicated hardware generators. However, the successful application of LLMs to
hardware accelerator design is contingent upon the availability of specialized
datasets tailored for this purpose. To bridge this gap, we introduce the
Systolic Array-based Accelerator Data Set (SA-DS). SA-DS comprises a diverse
collection of spatial array designs following the standardized Berkeley's
Gemmini accelerator generator template, enabling design reuse, adaptation, and
customization. SA-DS is intended to spark LLM-centered research on DNN hardware
accelerator architecture. We envision that SA-DS provides a framework that will
shape the course of DNN hardware acceleration research for generations to come.
SA-DS is open-sourced under the permissive MIT license at
https://github.com/ACADLab/SA-DS.git}{https://github.com/ACADLab/SA-DS.
