  L-band digital aeronautical communication system type-1 (L-DACS1) is an
emerging standard that aims at enhancing air traffic management by
transitioning the traditional analog aeronautical communication systems to the
superior and highly efficient digital domain. L-DACS1 employs modern and
efficient orthogonal frequency-division multiplexing (OFDM) modulation
technique to achieve more efficient and higher data rate in comparison to the
existing aeronautical communication systems. However, the performance of OFDM
systems is very sensitive to synchronization errors such as symbol timing
offset (STO) and carrier frequency offset (CFO). STO and CFO estimations are
extremely important for maintaining orthogonality among the subcarriers for the
retrieval of information. This paper proposes a novel efficient hardware
synchronizer for L-DACS1 systems that offers robust performance at low power
and low hardware resource usage. Monte Carlo simulations show that the proposed
synchronization algorithm provides accurate STO estimation as well as
fractional CFO estimation. Implementation of the proposed synchronizer on a
widely used field-programmable gate array (FPGA) (Xilinx xc7z020clg484-1)
results in a very low hardware usage which consumed 6.5%, 3.7%, and 6.4% of the
total number of lookup tables, flip-flops, and digital signal processing
blocks, respectively. The dynamic power of the proposed synchronizer is below 1
mW.
