  There has been growing interest in using photonic processors for performing
neural network inference operations; however, these networks are currently
trained using standard digital electronics. Here, we propose on-chip training
of neural networks enabled by a CMOS-compatible silicon photonic architecture
to harness the potential for massively parallel, efficient, and fast data
operations. Our scheme employs the direct feedback alignment training
algorithm, which trains neural networks using error feedback rather than error
backpropagation, and can operate at speeds of trillions of multiply-accumulate
(MAC) operations per second while consuming less than one picojoule per MAC
operation. The photonic architecture exploits parallelized matrix-vector
multiplications using arrays of microring resonators for processing
multi-channel analog signals along single waveguide buses to calculate the
gradient vector for each neural network layer in situ. We also experimentally
demonstrate training deep neural networks with the MNIST dataset using on-chip
MAC operation results. Our novel approach for efficient, ultra-fast neural
network training showcases photonics as a promising platform for executing AI
applications.
