  Recent advances in logic schemes and fabrication processes have renewed
interest in using superconductor electronics for energy-efficient computing and
quantum control processors. However, scalable superconducting memory still
poses a challenge. To address this issue, we present an alternative to
approaches that solely emphasize storage cell miniaturization by exploiting the
minimal attenuation and dispersion properties of superconducting passive
transmission lines to develop a delay-line memory system. This fully
superconducting design operates at speeds between 20 GHz and 100 GHz, with
$\pm$24\% and $\pm$13\% bias margins, respectively, and demonstrates data
densities in the 10s of Mbit/cm$^2$ with the MIT Lincoln Laboratory SC2
fabrication process. Additionally, the circulating nature of this design allows
for minimal control circuitry, eliminates the need for data splitting and
merging, and enables inexpensive implementations of sequential access and
content-addressable memories. Further advances in fabrication processes suggest
data densities of 100s of Mbit/cm$^2$ and beyond
