  By advances in technology, integrated circuits have come to include more
functionality and more complexity in a single chip. Although methods of testing
have improved, but the increase in complexity of circuits, keeps testing a
challenging problem. Two important challenges in testing of digital circuits
are test time and accessing the circuit under test (CUT) for testing. These
challenges become even more important in complex system on chip (SoC) zone.
This paper presents a multistage test strategy to be implemented on a BIST
architecture for reducing test time of a simple core as solution for more
global application of SoC testing strategy. This strategy implements its test
pattern generation and output response analyzer in a BILBO architecture. The
proposed method benefits from an irregular polynomial BILBO (IP-BILBO)
structure to improve its test results. Experimental results on ISCAS-89
benchmark circuits show an average of 35% improvement in test time in
proportion to pervious work.
