  Optimal deployment of deep neural networks (DNNs) on state-of-the-art
Systems-on-Chips (SoCs) is crucial for tiny machine learning (TinyML) at the
edge. The complexity of these SoCs makes deployment non-trivial, as they
typically contain multiple heterogeneous compute cores with limited,
programmer-managed memory to optimize latency and energy efficiency. We propose
HTVM - a compiler that merges TVM with DORY to maximize the utilization of
heterogeneous accelerators and minimize data movements. HTVM allows deploying
the MLPerf(TM) Tiny suite on DIANA, an SoC with a RISC-V CPU, and digital and
analog compute-in-memory AI accelerators, at 120x improved performance over
plain TVM deployment.
