  All-spin logic devices are promising candidates to augment and complement
beyond-CMOS integrated circuit computing due to non-volatility, ultra-low
operating voltages, higher logical efficiency, and high density integration.
However, the path to reach lower energy-delay product performance compared to
CMOS transistors currently is not clear. We show that scaling and engineering
the nanoscale magnetic materials and interfaces is the key to realizing spin
logic devices that can surpass energy-delay performance of CMOS transistors.
With validated stochastic nano-magnetic and vector spin transport numerical
models, we derive the target material and interface properties for the
nanomagnets and channels. We identified promising new directions for material
engineering/discovery focusing on systematic scaling of magnetic anisotropy
(Hk) with saturation magnetization (Ms), use of perpendicular magnetic
anisotropy, and interface spin mixing conductance of ferromagnet/spin channel
interface (Gmix). We provide systematic targets for scaling spin logic
energy-delay product toward a 2 aJ.ns energy-delay product, comprehending the
stochastic noise for nanomagnets.
