  Software messaging frameworks help avoid errors and reduce engineering
efforts in building distributed systems by (1) providing an interface
definition language (IDL) to specify precisely the structure of the message
(i.e., the message schema), and (2) automatically generating the serialization
and deserialization functions that transform user data structures into binary
data for sending across the network and vice versa. Similarly, a
hardware-accelerated system, which consists of host software and multiple
FPGAs, could also benefit from a messaging framework to handle messages both
between software and FPGA and also between different FPGAs. The key challenge
for a hardware messaging framework is that it must be able to support large
messages with complex schema while meeting critical constraints such as clock
frequency, area, and throughput.
  In this paper, we present HGum, a messaging framework for hardware
accelerators that meets all the above requirements. HGum is able to generate
high-performance and low-cost hardware logic by employing a novel design that
algorithmically parses the message schema to perform serialization and
deserialization. Our evaluation of HGum shows that it not only significantly
reduces engineering efforts but also generates hardware with comparable quality
to manual implementation.
