  On real-time systems running under timing constraints, scheduling can be
performed when one is aware of the worst case execution time (WCET) of tasks.
Usually, the WCET of a task is unknown and schedulers make use of safe
over-approximations given by static WCET analysis. To reduce the
over-approximation, WCET analysis has to gain information about the underlying
hardware behavior, such as pipelines and caches. In this paper, we focus on the
cache analysis, which classifies memory accesses as hits/misses according to
the set of possible cache states. We propose to refine the results of classical
cache analysis using a model checker, introducing a new cache model for the
least recently used (LRU) policy.
