  Hard real-time systems like image processing, autonomous driving, etc.
require an increasing need of computational power that classical multi-core
platforms can not provide, to fulfill with their timing constraints.
Heterogeneous Instruction Set Architecture (ISA) platforms allow accelerating
real-time workloads on application-specific cores (e.g. GPU, DSP, ASICs) etc.
and are suitable for these applications. In addition, these platforms provide
larger design choices as a given functionnality can be implemented onto several
types of compute elements. HPC-DAG (Heterogeneous Parallel Directed Acyclic
Graph) task model has been recently proposed to capture real-time workload
execution on heterogeneous platforms. It expresses the ISA heterogeneity, and
some specific characteristics of hardware accelerators, as the absence of
preemption or costly preemption, alternative implementations and on-line
conditional execution. In this paper, we propose a time-table scheduling
approach to allocate and schedule a set of HPC-DAG tasks onto a set of
heterogeneous cores, by the mean Integer Linear Programming (ILP). Our design
allows to handle heterogeniety of resources, on-line execution costs, and a
faster solving time, by exploring gradually the design space
