  By advances in technology, integrated circuits have come to include more
functionality and more complexity in a single chip. Although methods of testing
have improved, but the increase in complexity of circuits, keeps testing a
challenging problem. Two important challenges in testing of digital circuits
are test time and accessing the circuit under test (CUT) for testing. These
challenges become even more important in complex system on chip (SoC) zone.
This paper presents an improved scheme for generating precomputed test patterns
in core based systems on chip. This approach reduces the number of pre computed
test patterns and as the result, test application time (TAT) will be decreased.
Experimental results on ISCAS89 benchmark circuits show improvement in the
number of test clock cycles.
