  3D integration technologies are seeing widespread adoption in the
semiconductor industry to offset the limitations and slowdown of
two-dimensional scaling. High-density 3D integration techniques such as
face-to-face wafer bonding with sub-10 $\mu$m pitch can enable new ways of
designing SoCs using all 3 dimensions, like folding a microprocessor design
across multiple 3D tiers. However, overlapping thermal hotspots can be a
challenge in such 3D stacked designs due to a general increase in power
density. In this work, we perform a thorough thermal simulation study on
sign-off quality physical design implementation of a state-of-the-art,
high-performance, out-of-order microprocessor on a 7nm process technology. The
physical design of the microprocessor is partitioned and implemented in a
2-tier, 3D stacked configuration with logic blocks and memory instances in
separate tiers (logic-over-memory 3D). The thermal simulation model was
calibrated to temperature measurement data from a high-performance, CPU-based
2D SoC chip fabricated on the same 7nm process technology. Thermal profiles of
different 3D configurations under various workload conditions are simulated and
compared. We find that stacking microprocessor designs in 3D without
considering thermal implications can result in maximum die temperature up to
12{\deg}C higher than their 2D counterparts under the worst-case
power-indicative workload. This increase in temperature would reduce the amount
of time for which a power-intensive workload can be run before throttling is
required. However, logic-over-memory partitioned 3D CPU implementation can
mitigate this temperature increase by half, which makes the temperature of the
3D design only 6$^\circ$C higher than the 2D baseline. We conclude that using
thermal aware design partitioning and improved cooling techniques can overcome
the thermal challenges associated with 3D stacking.
