  Basic Linear Algebra Subprograms (BLAS) play key role in high performance and
scientific computing applications. Experimentally, yesteryear multicore and
General Purpose Graphics Processing Units (GPGPUs) are capable of achieving up
to 15 to 57% of the theoretical peak performance at 65W to 240W respectively
for compute bound operations like Double/Single Precision General Matrix
Multiplication (XGEMM). For bandwidth bound operations like Single/Double
precision Matrix-vector Multiplication (XGEMV) the performance is merely 5 to
7% of the theoretical peak performance in multicores and GPGPUs respectively.
Achieving performance in BLAS requires moving away from conventional wisdom and
evolving towards customized accelerator tailored for BLAS through
algorithm-architecture co-design. In this paper, we present acceleration of
Level-1 (vector operations), Level-2 (matrix-vector operations), and Level-3
(matrix-matrix operations) BLAS through algorithm architecture co-design on a
Coarse-grained Reconfigurable Architecture (CGRA). We choose REDEFINE CGRA as a
platform for our experiments since REDEFINE can be adapted to support domain of
interest through tailor-made Custom Function Units (CFUs). For efficient
sequential realization of BLAS, we present design of a Processing Element (PE)
and perform micro-architectural enhancements in the PE to achieve up-to 74% of
the theoretical peak performance of PE in DGEMM, 40% in DGEMV and 20% in double
precision inner product (DDOT). We attach this PE to REDEFINE CGRA as a CFU and
show the scalability of our solution. Finally, we show performance improvement
of 3-140x in PE over commercially available Intel micro-architectures,
ClearSpeed CSX700, FPGA, and Nvidia GPGPUs.
