  This paper introduces the problem of learning to place logic blocks in
Field-Programmable Gate Arrays (FPGAs) and a learning-based method. In contrast
to previous search-based placement algorithms, we instead employ Reinforcement
Learning (RL) with the goal of minimizing wirelength. In addition to our
preliminary learning results, we also evaluated a novel decomposition to
address the nature of large search space when placing many blocks on a
chipboard. Empirical experiments evaluate the effectiveness of the learning and
decomposition paradigms on FPGA placement tasks.
