  IUCAA Digital Sampling Array Controller (IDSAC) is a flexible and generic yet
powerful CCD controller which can handle a wide range of scientific detectors.
Based on an easily scalable modular backplane architecture consisting of Single
Board Controllers (SBC), IDSAC can control large detector arrays and mosaics.
Each of the SBCs offers the full functionality required to control a CCD
independently. The SBCs can be cold swapped without the need to reconfigure
them. Each SBC can handle data from up to four video channels with or without
dummy outputs at speeds up to 500 kilo Pixels Per Second (kPPS) Per Channel
with a resolution of 16 bits. Communication with Linux based host computer is
through a USB3.0 interface, with the option of using copper or optical fibers.
A Field Programmable Gate Array (FPGA) is used as the master controller in each
SBC which allows great flexibility in optimizing performance by adjusting gain,
timing signals, bias levels, etc. using user-editable configuration files
without altering the circuit topology. Elimination of thermal kTC noise is
achieved via Digital Correlated Double Sampling (DCDS). We present the results
of noise performance characterization of IDSAC through simulation, theoretical
modeling, and actual measurements. The contribution of different types of noise
sources is modeled using a tool to predict noise of a generic DCDS signal chain
analytically. The analytical model predicts the net input referenced noise of
the signal chain to be 5 electrons for 200k pixels per second per channel
readout rate with 3 samples per pixel. Using a cryogenic test set up in the
lab, the noise is measured to be 5.4 e (24.3 \muV), for the same readout
configuration.
