  In this paper we report a new PNP Surface Accumulation Layer Transistor
(SALTran) on SOI which uses the concept of surface accumulation of holes near
the emitter contact to significantly improve the current gain. Using
two-dimensional simulation, we have evaluated the performance of the proposed
device in detail by comparing its characteristics with those of the previously
published conventional PNP lateral bipolar transistor (LBT) structure. From our
simulation results it is observed that depending on the choice of the emitter
doping and the emitter length, the proposed SALTran exhibits a current gain
enhancement of around 20 times that of the compatible lateral bipolar
transistor without deteriorating the cut-off frequency. We have discussed the
reasons for the improved performance of the SALTran based on our detailed
simulation results.
