  Design flows use graph partitioning both as a precursor to place and route
for single devices, and to divide netlists or task graphs among multiple
devices. Partitioners have accommodated FPGA heterogeneity via multi-resource
constraints, but have not yet exploited the corresponding ability to implement
some computations in multiple ways (e.g., LUTs vs. DSP blocks), which could
enable a superior solution. This paper introduces multi-personality graph
partitioning, which incorporates aspects of resource mapping into partitioning.
We present a modified multi-level KLFM partitioning algorithm that also
performs heterogeneous resource mapping for nodes with multiple potential
implementations (multiple personalities). We evaluate several variants of our
multi-personality FPGA circuit partitioner using 21 circuits and benchmark
graphs, and show that dynamic resource mapping improves cut size on average by
27% over static mapping for these circuits. We further show that it improves
deviation from target resource utilizations by 50% over post-partitioning
resource mapping.
