  Reconstructing system-level behavior from silicon traces is a critical
problem in post-silicon validation of System-on-Chip designs. Current
industrial practice in this area is primarily manual, depending on
collaborative insights of the architects, designers, and validators. This paper
presents a trace analysis approach that exploits architectural models of the
system-level protocols to reconstruct design behavior from partially observed
silicon traces in the presence of ambiguous and noisy data. The output of the
approach is a set of all potential interpretations of a system's internal
executions abstracted to the system-level protocols. To support the trace
analysis approach, a companion trace signal selection framework guided by
system-level protocols is also presented, and its impacts on the complexity and
accuracy of the analysis approach are discussed. That approach and the
framework have been evaluated on a multi-core system-on-chip prototype that
implements a set of common industrial system-level protocols.
