  FinFETs are predicted to advance semiconductorscaling for sub-20nm devices.
In order to support their intro-duction into research and universities it is
crucial to develop anopen source predictive process design kit. This paper
discussesin detail the design process for such a kit for 15nm FinFETdevices,
called the FreePDK15. The kit consists of a layerstack with thirteen-metal
layers based on hierarchical-scalingused in ASIC architecture, Middle-of-Line
local interconnectlayers and a set of Front-End-of-Line layers. The physical
andgeometrical properties of these layers are defined and theseproperties
determine the density and parasitics of the design. Thedesign rules are laid
down considering additional guidelines forprocess variability, challenges
involved in FinFET fabrication anda unique set of design rules are developed
for critical dimensions.Layout extraction including modified rules for
determining thegeometrical characteristics of FinFET layouts are implementedand
discussed to obtain successful Layout Versus Schematicchecks for a set of
layouts. Moreover, additional parasiticcomponents of a standard FinFET device
are analyzed andthe parasitic extraction of sample layouts is performed.
Theseextraction results are then compared and assessed against thevalidation
models.
