  We present a design and implementation of the Thomas algorithm optimized for
hardware acceleration on an FPGA, the Thomas Core. The hardware-based algorithm
combined with the custom data flow and low level parallelism available in an
FPGA reduces the overall complexity from 8N down to 5N serial arithmetic
operations, and almost halves the overall latency by parallelizing the two
costly divisions. Combining this with a data streaming interface, we reduce
memory overheads to 2 N-length vectors per N-tridiagonal system to be solved.
The Thomas Core allows for multiple independent tridiagonal systems to be
continuously solved in parallel, providing an efficient and scalable
accelerator for many numerical computations. Finally we present applications
for derivatives pricing problems using implicit finite difference schemes on an
FPGA accelerated system and we investigate the use and limitations of
fixed-point arithmetic in our algorithm.
