  For decades, advances in electronics were directly driven by the scaling of
CMOS transistors according to Moore's law. However, both the CMOS scaling and
the classical computer architecture are approaching fundamental and practical
limits, and new computing architectures based on emerging devices, such as
resistive random-access memory (RRAM) devices, are expected to sustain the
exponential growth of computing capability. Here we propose a novel
memory-centric, reconfigurable, general purpose computing platform that is
capable of handling the explosive amount of data in a fast and energy-efficient
manner. The proposed computing architecture is based on a uniform, physical,
resistive, memory-centric fabric that can be optimally reconfigured and
utilized to perform different computing and data storage tasks in a massively
parallel approach. The system can be tailored to achieve maximal energy
efficiency based on the data flow by dynamically allocating the basic computing
fabric for storage, arithmetic, and analog computing including neuromorphic
computing tasks.
