  Transistor-based memories are rapidly approaching their maximum density per
unit area. Resistive crossbar arrays enable denser memory due to the small size
of switching devices. However, due to the resistive nature of these memories,
they suffer from current sneak paths complicating the readout procedure. In
this paper, we propose a row readout technique with circuitry that can be used
to read {selector-less} resistive crossbar based memories. High throughput
reading and writing techniques are needed to overcome the memory-wall
bottleneck problem and to enable near memory computing paradigm. The proposed
technique can read the entire row of dense crossbar arrays in one cycle, unlike
previously published techniques. The requirements for the readout circuitry are
discussed and satisfied in the proposed circuit. Additionally, an approximated
expression for the power consumed while reading the array is derived. A figure
of merit is defined and used to compare the proposed approach with existing
reading techniques. Finally, a quantitative analysis of the effect of biasing
mismatch on the array size is discussed.
