  The performance of a D-Wave Vesuvius quantum annealer was recently compared
to a suite of classical algorithms on a class of constraint satisfaction
instances based on frustrated loops. However, the construction of these
instances leads the maximum coupling strength to increase with problem size. As
a result, larger instances are subject to amplified analog control error, and
are effectively annealed at higher temperatures in both hardware and software.
We generate similar constraint satisfaction instances with limited range of
coupling strength and perform a similar comparison to classical algorithms. On
these instances the D-Wave Vesuvius processor, run with a fixed 20$\mu$s anneal
time, shows a scaling advantage over the software solvers for the hardest
regime studied. This scaling advantage opens the possibility of quantum speedup
on these problems. Our results support the hypothesis that performance of
D-Wave Vesuvius processors is heavily influenced by analog control error, which
can be reduced and mitigated as the technology matures.
