  As the number of cores scales to tens and hundreds, the energy consumption of
routers across various types of on-chip networks in chip muiltiprocessors
(CMPs) increases significantly. A major source of this energy consumption comes
from the input buffers inside Network-on-Chip (NoC) routers, which are
traditionally designed to maximize performance. To mitigate this high energy
cost, many works propose bufferless router designs that utilize deflection
routing to resolve port contention. While this approach is able to maintain
high performance relative to its buffered counterparts at low network traffic,
the bufferless router design suffers performance degradation under high network
load.
  In order to maintain high performance and energy efficiency under both low
and high network loads, this chapter discusses critical drawbacks of
traditional bufferless designs and describes recent research works focusing on
two major modifications to improve the overall performance of the traditional
bufferless network-on-chip design. The first modification is a
minimally-buffered design that introduces limited buffering inside critical
parts of the on-chip network in order to reduce the number of deflections. The
second modification is a hierarchical bufferless interconnect design that aims
to further improve performance by limiting the number of hops each packet needs
to travel while in the network. In both approaches, we discuss design tradeoffs
and provide evaluation results based on common CMP configurations with various
network topologies to show the effectiveness of each proposal.
