  In 2008, Salahuddin and Datta proposed that a ferroelectric material
operating in the negative capacitance region could act as a step-up converter
of the surface potential in a MOS structure, opening a new route for the
realization of transistors with steeper subthreshold characteristics (S<60
mV/decade). In this letter, a comprehensive physics-based surface potential and
drain current model for the negative capacitance field-effect transistor is
reported. The model is aimed to evaluate the potentiality of such transistors
for low-power switching applications. Moreover it provides a model core for
memories devices relying on the hysteretic behavior of the ferroelectric gate
insulator.
