  Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAM in
on-chip caches due to several advantages. These advantages include
non-volatility, low leakage, high integration density, and CMOS compatibility.
Prior studies have shown that relaxing and adapting the STTRAM retention time
to runtime application needs can substantially reduce overall cache energy
without significant latency overheads, due to the lower STTRAM write energy and
latency in shorter retention times. In this paper, as a first step towards
efficient prefetching across the STTRAM cache hierarchy, we study prefetching
in reduced retention STTRAM L1 caches. Using SPEC CPU 2017 benchmarks, we
analyze the energy and latency impact of different prefetch distances in
different STTRAM cache retention times for different applications. We show that
expired_unused_prefetches---the number of unused prefetches expired by the
reduced retention time STTRAM cache---can accurately determine the best
retention time for energy consumption and access latency. This new metric can
also provide insights into the best prefetch distance for memory bandwidth
consumption and prefetch accuracy. Based on our analysis and insights, we
propose Prefetch-Aware Retention time Tuning (PART) and Retention time-based
Prefetch Control (RPC). Compared to a base STTRAM cache, PART and RPC
collectively reduced the average cache energy and latency by 22.24% and 24.59%,
respectively. When the base architecture was augmented with the
state-of-the-art near-side prefetch throttling (NST), PART+RPC reduced the
average cache energy and latency by 3.50% and 3.59%, respectively, and reduced
the hardware overhead by 54.55%
