  Similar to other programming models, compilers for SYCL, the open programming
model for heterogeneous computing based on C++, would benefit from access to
higher-level intermediate representations. The loss of high-level structure and
semantics caused by premature lowering to low-level intermediate
representations and the inability to reason about host and device code
simultaneously present major challenges for SYCL compilers. The MLIR compiler
framework, through its dialect mechanism, allows to model domain-specific,
high-level intermediate representations and provides the necessary facilities
to address these challenges. This work therefore describes practical experience
with the design and implementation of an MLIR-based SYCL compiler. By modeling
key elements of the SYCL programming model in host and device code in the MLIR
dialect framework, the presented approach enables the implementation of
powerful device code optimizations as well as analyses across host and device
code. Compared to two LLVM-based SYCL implementations, this yields speedups of
up to 4.3x on a collection of SYCL benchmark applications. Finally, this work
also discusses challenges encountered in the design and implementation and how
these could be addressed in the future.
