  Polar codes, as the first provable capacity-achieving error-correcting codes,
have received much attention in recent years. However, the decoding performance
of polar codes with traditional successive-cancellation (SC) algorithm cannot
match that of the low-density parity-check (LDPC) or turbo codes. Because SC
list (SCL) decoding algorithm can significantly improve the error-correcting
performance of polar codes, design of SCL decoders is important for polar codes
to be deployed in practical applications. However, because the prior latency
reduction approaches for SC decoders are not applicable for SCL decoders, these
list decoders suffer from the long latency bottleneck. In this paper, we
propose a multi-bit-decision approach that can significantly reduce latency of
SCL decoders. First, we present a reformulated SCL algorithm that can perform
intermediate decoding of 2 bits together. The proposed approach, referred as
2-bit reformulated SCL (2b-rSCL) algorithm, can reduce the latency of SCL
decoder from (3n-2) to (2n-2) clock cycles without any performance loss. Then,
we extend the idea of 2-bit-decision to general case, and propose a general
decoding scheme that can perform intermediate decoding of any 2K bits
simultaneously. This general approach, referred as 2K-bit reformulated SCL
(2Kb-rSCL) algorithm, can reduce the overall decoding latency to as short as
n/2K-2-2 cycles. Furthermore, based on the proposed algorithms, VLSI
architectures for 2b-rSCL and 4b-rSCL decoders are synthesized. Compared with a
prior SCL decoder, the proposed (1024, 512) 2b-rSCL and 4b-rSCL decoders can
achieve 21% and 60% reduction in latency, 1.66 times and 2.77 times increase in
coded throughput with list size 2, and 2.11 times and 3.23 times increase in
coded throughput with list size 4, respectively.
