  Globalization of IC manufacturing has led to increased security concerns,
notably IP theft. Several logic locking techniques have been developed for
protecting designs, but they typically display very large overhead, and are
generally susceptible to deciphering attacks. In this paper, we propose
latch-based logic locking, which manipulates both the flow of data and logic in
the design. This method converts an interconnected subset of existing
flip-flops to pairs of latches with programmable phase. In tandem, decoy
latches and logic are added, inhibiting an attacker from determining the actual
design functionality. To validate this technique, we developed and verified a
locking insertion flow, analyzed PPA and ATPG overhead on benchmark circuits
and industry cores, extended existing attacks to account for the technique, and
taped out a demonstration chip. Importantly, we show that the design overhead
with this approach is significantly less than with previous logic locking
schemes, while resisting model checker-based, oracle-driven attacks. With
minimal delay overhead, large numbers of decoy latches can be added, cheaply
increasing attack resistance.
