  The need of surface-localized thermal processing is strongly increasing
especially w.r.t three-dimensionally (3D) integrated electrical devices. UV
laser annealing (UV-LA) technology well addresses this challenge. Particularly
UV-LA can reduce resistivity by enlarging metallic grains in lines or thin
films, irradiating only the interconnects for short timescales. However, the
risk of failure in electrical performance must be correctly managed, and that
of UV-LA has not been deeply studied yet. In this work microsecond-scale UV-LA
is applied on a stack comparable to an interconnect structure
(dielectric/Cu/Ta/SiO2/Si) in either melt or sub-melt regime for grain growth.
The failure modes such as (i) Cu diffusion into SiO2, (ii) O incorporation into
Cu, and (iii) intermixing between Cu and Ta are investigated.
