  The Rocket Chip Generator uses a collection of parameterized processor
components to produce RISC-V-based SoCs. It is a powerful tool that can produce
a wide variety of processor designs ranging from tiny embedded processors to
complex multi-core systems. In this paper we extend the features of the Memory
Management Unit of the Rocket Chip Generator and specifically the TLB
hierarchy. TLBs are essential in terms of performance because they mitigate the
overhead of frequent Page Table Walks, but may harm the critical path of the
processor due to their size and/or associativity. In the original Rocket Chip
implementation the L1 Instruction/Data TLB is fully-associative and the shared
L2 TLB is direct-mapped. We lift these restrictions and design and implement
configurable, set-associative L1 and L2 TLB templates that can create any
organization from direct-mapped to fully-associative to achieve the desired
ratio of performance and resource utilization, especially for larger TLBs. We
evaluate different TLB configurations and present performance, area, and
frequency results of our design using benchmarks from the SPEC2006 suite on the
Xilinx ZCU102 FPGA.
