  Power dissipation in the sequential systems of modern CPU integrated chips
(CPU-IC viz., Silicon Chip) is in discussion since the last decade. Researchers
have been cultivating many low power design methods to choose the best
potential candidate for reducing both static and dynamic power of a chip.
Though, clock gating (CG) has been an accepted technique to control dynamic
power dissipation, question still loiters on its credibility to handle the
static power of the system. Therefore in this paper, we have revisited the
popular CG schemes and found out some scope of improvisation to support the
simultaneous reduction of static and dynamic power dissipation. Our proposed CG
is simulated for 90nm CMOS using Cadence Virtuoso and has been tested on a
conventional Master-Slave Flip-flop at 5GHz clock with a power supply of
1.1Volt. This assignment clearly depicts its supremacy in terms of power and
timing metrics in comparison to the implementation of existing CG schemes.
