  With data-driven analytics becoming mainstream, the global demand for
dedicated AI and Deep Learning accelerator chips is soaring. These
accelerators, designed with densely packed Processing Elements (PE), are
especially vulnerable to the manufacturing defects and functional faults common
in the advanced semiconductor process nodes resulting in significant yield
loss. In this work, we demonstrate an application-driven methodology of binning
the AI accelerator chips, and yield loss reduction by correlating the circuit
faults in the PEs of the accelerator with the desired accuracy of the target AI
workload. We exploit the inherent fault tolerance features of trained deep
learning models and a strategy of selective deactivation of faulty PEs to
develop the presented yield loss reduction and test methodology. An analytical
relationship is derived between fault location, fault rate, and the AI task's
accuracy for deciding if the accelerator chip can pass the final yield test. A
yield-loss reduction aware fault isolation, ATPG, and test flow are presented
for the multiply and accumulate units of the PEs. Results obtained with widely
used AI/deep learning benchmarks demonstrate that the accelerators can sustain
5% fault-rate in PE arrays while suffering from less than 1% accuracy loss,
thus enabling product-binning and yield loss reduction of these chips.
