  While discrete-event simulators are essential tools for architecture
research, design, and development, their practicality is limited by an
extremely long time-to-solution for realistic applications under investigation.
This work describes a concerted effort, where machine learning (ML) is used to
accelerate discrete-event simulation. First, an ML-based instruction latency
prediction framework that accounts for both static instruction properties and
dynamic processor states is constructed. Then, a GPU-accelerated parallel
simulator is implemented based on the proposed instruction latency predictor,
and its simulation accuracy and throughput are validated and evaluated against
a state-of-the-art simulator. Leveraging modern GPUs, the ML-based simulator
outperforms traditional simulators significantly.
