  GPGPUs use the Single-Instruction-Multiple-Thread (SIMT) execution model
where a group of threads-wavefront or warp-execute instructions in lockstep.
When threads in a group encounter a branching instruction, not all threads in
the group take the same path, a phenomenon known as control-flow divergence.
The control-flow divergence causes performance degradation because both paths
of the branch must be executed one after the other. Prior research has
primarily addressed this issue through architectural modifications. We observe
that certain GPGPU kernels with control-flow divergence have similar
control-flow structures with similar instructions on both sides of a branch.
This structure can be exploited to reduce control-flow divergence by melding
the two sides of the branch allowing threads to reconverge early, reducing
divergence. In this work, we present DARM, a compiler analysis and
transformation framework that can meld divergent control-flow structures with
similar instruction sequences. We show that DARM can reduce the performance
degradation from control-flow divergence.
