  Erasure qubits offer a promising avenue toward reducing the overhead of
quantum error correction (QEC) protocols. However, they require additional
operations, such as erasure checks, that may add extra noise and increase
runtime of QEC protocols. To assess the benefits provided by erasure qubits, we
focus on the performance of the surface code as a quantum memory. In
particular, we analyze various erasure check schedules, find the correctable
regions in the phase space of error parameters and probe the subthreshold
scaling of the logical error rate. We then consider a realization of erasure
qubits in the superconducting hardware architectures via dual-rail qubits. We
use the standard transmon-based implementation of the surface code as the
performance benchmark. Our results indicate that QEC protocols with erasure
qubits can outperform the ones with state-of-the-art transmons, even in the
absence of precise information about the locations of erasure errors.
