  A three-dimensional (3D) Network-on-Chip (NoC) enables the design of high
performance and low power many-core chips. Existing 3D NoCs are inadequate for
meeting the ever-increasing performance requirements of many-core processors
since they are simple extensions of regular 2D architectures and they do not
fully exploit the advantages provided by 3D integration. Moreover, the
anticipated performance gain of a 3D NoC-enabled many-core chip may be
compromised due to the potential failures of through-silicon-vias (TSVs) that
are predominantly used as vertical interconnects in a 3D IC. To address these
problems, we propose a machine-learning-inspired predictive design methodology
for energy-efficient and reliable many-core architectures enabled by 3D
integration. We demonstrate that a small-world network-based 3D NoC (3D SWNoC)
performs significantly better than its 3D MESH-based counterparts. On average,
the 3D SWNoC shows 35% energy-delay-product (EDP) improvement over 3D MESH for
the PARSEC and SPLASH2 benchmarks considered in this work. To improve the
reliability of 3D NoC, we propose a computationally efficient spare-vertical
link (sVL) allocation algorithm based on a state-space search formulation. Our
results show that the proposed sVL allocation algorithm can significantly
improve the reliability as well as the lifetime of 3D SWNoC.
