  ATLAS LAr calorimeter will perform its Phase-I upgrade during the long shut
down (LS2) in 2018, a new LAr Trigger Digitizer Board (LTDB) will be designed
and installed. Several commercial-off-the-shelf (COTS) multichannel high-speed
ADCs have been selected as possible backups of the radiation tolerant ADC ASICs
for LTDB. In order to evaluate the radiation tolerance of these back up
commercial ADCs, we developed an ADC radiation tolerance characterization
system, which includes the ADC boards, data acquisition (DAQ) board, signal
generator, external power supplies and a host computer. The ADC board is custom
designed for different ADCs, which has ADC driver and clock distribution
circuits integrated on board. The Xilinx ZC706 FPGA development board is used
as DAQ board. The data from ADC are routed to the FPGA through the FMC (FPGA
Mezzanine Card) connector, de-serialized and monitored by the FPGA, and then
transmitted to the host computer through the Gigabit Ethernet. A software
program has been developed with Python, and all the commands are sent to the
DAQ board through Gigabit Ethernet by this program. Two ADC boards have been
designed for the TI ADS52J90 and ADI AD9249 respectively. TID test of both ADCs
have been performed at BNL, and SEE test for ADS52J90 has been performed at
Massachusetts General Hospital (MGH). Test results have been analyzed and
presented. The test results demonstrate that our test system is very versatile,
and working well for the radiation tolerance characterization of commercial
multi-channel high-speed ADC for the upgrade of the ATLAS LAr calorimeter. It
is applicable to other collider physics experiments where radiation tolerance
is required as well.
