  Embedded system performances are bounded by power consumption. The trend is
to offload greedy computations on hardware accelerators as GPU, Xeon Phi or
FPGA. FPGA chips combine both flexibility of programmable chips and
energy-efficiency of specialized hardware and appear as a natural solution.
Hardware compilers from high-level languages (High-level synthesis, HLS) are
required to exploit all the capabilities of FPGA while satisfying tight
time-to-market constraints. Compiler optimizations for parallelism and data
locality restructure deeply the execution order of the processes, hence the
read/write patterns in communication channels. This breaks most FIFO channels,
which have to be implemented with addressable buffers. Expensive hardware is
required to enforce synchronizations, which often results in dramatic
performance loss. In this paper, we present an algorithm to partition the
communications so that most FIFO channels can be recovered after a loop tiling,
a key optimization for parallelism and data locality. Experimental results show
a drastic improvement of FIFO detection for regular kernels at the cost of a
few additional storage. As a bonus, the storage can even be reduced in some
cases.
