  Two dimensional (2D) integration has been the traditional approach for IC
integration. Due to increasing demands for providing electronic devices with
superior performance and functionality in more efficient and compact packages,
has driven the semiconductor industry to develop more advanced packaging
technologies. Three-dimensional (3D) approaches address both miniaturization
and integration required for advanced and portable electronic products.
Vertical integration proved to be essential in achieving a greater integration
flexibility of disparate technologies, reason for which a general trend of
transition from 2D to 3D integration is currently being observed in the
industry. 3D chip integration using through silicon via (TSV) copper is
considered one of the most advanced technologies among all different types of
3D packaging technologies. Copper electrodeposition is one of technologies that
enable the formation of TSV structures. Because of its well-known application
for copper damascene, it was believed that its transfer to filling TSV vias
would be easily adopted. However, as any new technology at its beginning, there
are several challenges that need to be addressed and resolved before becoming a
fully mature technology. This paper will address the TSV fill processes using
copper electrodeposition, the advantages as well as difficulties associated
with this technology and approaches taken to overcome them. Electrochemical
characterization of the organics behavior and their effect on via filling will
be presented. The effect of wafer design on process performance and throughput,
including necessary process optimizations that are required for achieving
void-free via filling while reducing the processing time, will be discussed.
