  Decreasing transistor sizes and lower voltage swings cause two distinct
problems for communication in integrated circuits. First, decreasing inter-wire
spacing increases interline capacitive coupling, which adversely affects
transmission energy and delay. Second, lower voltage swings render the
transmission susceptible to various noise sources. Coding can be used to
address both these problems. So-called crosstalk-avoidance codes mitigate
capacitive coupling, and traditional error-correction codes introduce
resilience against channel errors.
  Unfortunately, crosstalk-avoidance and error-correction codes cannot be
combined in a straightforward manner. On the one hand, crosstalk-avoidance
encoding followed by error-correction encoding destroys the crosstalk-avoidance
property. On the other hand, error-correction encoding followed by
crosstalk-avoidance encoding causes the crosstalk-avoidance decoder to fail in
the presence of errors. Existing approaches circumvent this difficulty by using
additional bus wires to protect the parities generated from the output of the
error-correction encoder, and are therefore inefficient.
  In this work we propose a novel joint crosstalk-avoidance and
error-correction coding and decoding scheme that provides higher bus
transmission rates compared to existing approaches. Our joint approach
carefully embeds the parities such that the crosstalk-avoidance property is
preserved. We analyze the rate and minimum distance of the proposed scheme. We
also provide a density evolution analysis and predict iterative decoding
thresholds for reliable communication under random bus erasures. This density
evolution analysis is nonstandard, since the crosstalk-avoidance constraints
are inherently nonlinear.
