  All Spin Logic gates employ multiple nano-magnets interacting through
spin-torque using non-magnetic channels. Compactness, non-volatility and
ultra-low voltage operation are some of the attractive features of ASL, while,
low switching-speed (of nano-magnets as compared to CMOS gates) and
static-power dissipation can be identified as the major bottlenecks. In this
work we explore design techniques that leverage the specific device
characteristics of ASL to overcome the inefficiencies and to enhance the merits
of this technology, for a given set of device parameters. We exploit the
non-volatility of nano-magnets to model fully-pipelined ASL that can achieve
higher performance. Clocking of power supply in pipelined ASL would require
CMOS transistors that may consume significantly large voltage headroom and
area, as compared to the nano-magnets. We show that the use of leaky
transistors can significantly mitigate such bottlenecks, without sacrificing
energy-efficiency and robustness. Exploiting the inherent isolation between the
biasing charge current and spin-current paths in ASL, we propose to stack
multiple ASL metal layers, leading to ultra-high-density and energy-efficient
3-D computation blocks. Results for the design of an FIR filter show that ASL
can achieve performance and power consumption comparable to CMOS while the
ultra-high-density of ASL can be projected as its main advantage over CMOS.
