  As capacity and complexity of on-chip cache memory hierarchy increases, the
service cost to the critical loads from Last Level Cache (LLC), which are
frequently repeated, has become a major concern. The processor may stall for a
considerable interval while waiting to access the data stored in the cache
blocks in LLC, if there are no independent instructions to execute. To provide
accelerated service to the critical loads requests from LLC, this work
concentrates on leveraging the additional capacity offered by replacing
SRAM-based L2 with Spin-Transfer Torque Random Access Memory (STT-RAM) to
accommodate frequently accessed cache blocks in exclusive read mode in favor of
reducing the overall read service time. Our proposed technique partitions L2
cache into two STT-RAM arrangements with different write performance and data
retention time. The retention-relaxed STT-RAM arrays are utilized to
effectively deal with the regular L2 cache requests while the high retention
STT-RAM arrays in L2 are selected for maintaining repeatedly read accessed
cache blocks from LLC by incurring negligible energy consumption for data
retention. Our experimental results show that the proposed technique can reduce
the mean L2 read miss ratio by 51.4% and increase the IPC by 11.7% on average
across PARSEC benchmark suite while significantly decreasing the total L2
energy consumption compared to conventional SRAM-based L2 design.
