  Memory controller scheduling is crucial in multicore processors, where DRAM
bandwidth is shared. Since increased number of requests from multiple cores of
processors becomes a source of bottleneck, scheduling the requests efficiently
is necessary to utilize all the computing power these processors offer.
However, current multicore processors are using traditional memory controllers,
which are designed for single-core processors. They are unable to adapt to
changing characteristics of memory workloads that run simultaneously on
multiple cores. Existing schedulers may disrupt locality and bank parallelism
among data requests coming from different cores. Hence, novel memory
controllers that consider and adapt to the memory access characteristics, and
share memory resources efficiently and fairly are necessary. We introduce
Core-Aware Dynamic Scheduler (CADS) for multicore memory controller. CADS uses
Reinforcement Learning (RL) to alter its scheduling strategy dynamically at
runtime. Our scheduler utilizes locality among data requests from multiple
cores and exploits parallelism in accessing multiple banks of DRAM. CADS is
also able to share the DRAM while guaranteeing fairness to all cores accessing
memory. Using CADS policy, we achieve 20% better cycles per instruction (CPI)
in running memory intensive and compute intensive PARSEC parallel benchmarks
simultaneously, and 16% better CPI with SPEC 2006 benchmarks.
