  The present article introduces a novel ASIC architecture, designed in the
context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity
phase of the Large Hadron Collider at CERN. The architecture is based on
radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology,
embedding both analog and digital processing of detector signals. A detailed
description of the ASIC is given in terms of motivation, design characteristics
and simulated and measured performance. Experimental studies, based on 24
prototype units under real particle beam conditions are also presented in order
to demonstrate the potential of the architecture as a reliable front-end
readout electronic solution.
