  We describe critical processing issues in our development of single atom
devices for solid-state quantum information processing. Integration of single
31P atoms with control gates and single electron transistor (SET) readout
structures is addressed in a silicon-based approach. Results on electrical
activation of low energy (15 keV) P implants in silicon show a strong dose
effect on the electrical activation fractions. We identify dopant segregation
to the SiO2/Si interface during rapid thermal annealing as a dopant loss
channel and discuss measures of minimizing it. Silicon nanowire SET pairs with
nanowire width of 10 to 20 nm are formed by electron beam lithography in SOI.
We present first results from Coulomb blockade experiments and discuss issues
of control gate integration for sub-40nm gate pitch levels.
