  In general, real world signals are analog in nature. To capture these signals
for further processing, or transmission, signals are converted into digital
bits using analog-to-digital converter (ADC). In this conversion, a good amount
of signal energy is wasted because signal that is captured within the sampling
duration is utilized, while rest of the signal waveform is discarded. In this
context, this paper revisits the sampling process and proposes to utilize this
discarded signal for energy harvesting, naming the method as eSampling, i.e.,
sampling with energy harvesting. The proposed idea of \textit{eSampling} is
demonstrated via modifying the circuitry of the hold phase of ADC. The system
is designed using standard Complementary Metal Oxide Semiconductor (CMOS) 65 nm
technology and simulations are performed on Cadence Virtuoso platform with
input signal at different frequencies (100 Hz and 40 MHz). These results show
that 10\% of the sampling period is sufficient to sample the input analog
signal, while the remaining 90\% can be used for harvesting the energy from the
input analog signal. In order to validate eSampling for practical scenarios,
results with hardware setup have also been added.
