  A sample rate converter(SRC) is designed to adjust the sampling rate of
digital signals flexibly for different application requirements in the
broadband signal processing system. In this paper, a novel parallel-serial
structure is proposed to improve the bandwidth and flexibility of SRC. The core
of this structure is a parallel decimation filter followed by a serial
counterpart, the parallel part is designed to process high sampling rate data
streams, and the serial part provides high flexibility in decimation factor
configuration. A typical combination of cascaded integral comb filter(CIC) and
halfband filter is utilized in this structure, the serial recursive loop which
limits the processing ability of the CIC filter is transformed into a
parallel-pipeline recursive structure. In addition, the symmetry property and
zero coefficient of the halfband filter are exploited with the polyphase filter
structure to reduce resource utilization and design complexity. In the
meantime, the decimation factor of the CIC filter can be adjusted flexibly in a
wide range, which is used to improve the system configuration flexibility. This
parallel-serial SRC structure was implemented on Xilinx KU115 series field
programmable gate array(FPGA), and then applied in a synthetic instrument
system. The experiment results demonstrate that the proposed scheme
significantly improves the performance of SRC in bandwidth and flexibility.
