  There is a recent trend in artificial intelligence (AI) inference towards
lower precision data formats down to 8 bits and less. As multiplication is the
most complex operation in typical inference tasks, there is a large demand for
efficient small multipliers. The large DSP blocks have limitations implementing
many small multipliers efficiently. Hence, this work proposes a solution for
better logic-based multipliers that is especially beneficial for small
multipliers. Our work is based on the multiplier tiling method in which a
multiplier is designed out of several sub-multiplier tiles. The key observation
we made is that these sub-multipliers do not necessarily have to perform a
complete (rectangular) NxK multiplication and more efficient sub-multipliers
are possible that are incomplete (non-rectangular). This proposal first seeks
to identify efficient incomplete irregular sub-multipliers and then
demonstrates improvements over state-of-the-art designs. It is shown that
optimal solutions can be found using integer linear programming (ILP), which
are evaluated in FPGA synthesis experiments.
