  This paper proposes an efficient neural network (NN) architecture design
methodology called Chameleon that honors given resource constraints. Instead of
developing new building blocks or using computationally-intensive reinforcement
learning algorithms, our approach leverages existing efficient network building
blocks and focuses on exploiting hardware traits and adapting computation
resources to fit target latency and/or energy constraints. We formulate
platform-aware NN architecture search in an optimization framework and propose
a novel algorithm to search for optimal architectures aided by efficient
accuracy and resource (latency and/or energy) predictors. At the core of our
algorithm lies an accuracy predictor built atop Gaussian Process with Bayesian
optimization for iterative sampling. With a one-time building cost for the
predictors, our algorithm produces state-of-the-art model architectures on
different platforms under given constraints in just minutes. Our results show
that adapting computation resources to building blocks is critical to model
performance. Without the addition of any bells and whistles, our models achieve
significant accuracy improvements against state-of-the-art hand-crafted and
automatically designed architectures. We achieve 73.8% and 75.3% top-1 accuracy
on ImageNet at 20ms latency on a mobile CPU and DSP. At reduced latency, our
models achieve up to 8.5% (4.8%) and 6.6% (9.3%) absolute top-1 accuracy
improvements compared to MobileNetV2 and MnasNet, respectively, on a mobile CPU
(DSP), and 2.7% (4.6%) and 5.6% (2.6%) accuracy gains over ResNet-101 and
ResNet-152, respectively, on an Nvidia GPU (Intel CPU).
