  Due to the unavailability of routing information in design stages prior to
detailed routing (DR), the tasks of timing prediction and optimization pose
major challenges. Inaccurate timing prediction wastes design effort, hurts
circuit performance, and may lead to design failure. This work focuses on
timing prediction after clock tree synthesis and placement legalization, which
is the earliest opportunity to time and optimize a "complete" netlist. The
paper first documents that having "oracle knowledge" of the final post-DR
parasitics enables post-global routing (GR) optimization to produce improved
final timing outcomes. To bridge the gap between GR-based parasitic and timing
estimation and post-DR results during post-GR optimization, machine learning
(ML)-based models are proposed, including the use of features for macro
blockages for accurate predictions for designs with macros. Based on a set of
experimental evaluations, it is demonstrated that these models show higher
accuracy than GR-based timing estimation. When used during post-GR
optimization, the ML-based models show demonstrable improvements in post-DR
circuit performance. The methodology is applied to two different tool flows -
OpenROAD and a commercial tool flow - and results on 45nm bulk and 12nm FinFET
enablements show improvements in post-DR slack metrics without increasing
congestion. The models are demonstrated to be generalizable to designs
generated under different clock period constraints and are robust to training
data with small levels of noise.
