  Millimeter wave (mmW) codesigned 802.11ad-based joint radar communication
(JRC) systems have been identified as a potential solution for realizing high
bandwidth connected vehicles for next-generation intelligent transportation
systems. The radar functionality within the JRC enables accurate detection and
localization of mobile targets, which can significantly speed up the selection
of the optimal high-directional narrow beam required for mmW communications
between the base station and mobile target. To bring JRC to reality, a radar
signal processing (RSP) accelerator, co-located with the wireless communication
physical layer (PHY), on edge platforms is desired. In this work, we discuss
the three-dimensional digital hardware RSP framework for 802.11ad-based JRC to
detect the range, azimuth, and Doppler velocity of multiple targets. We present
a novel efficient reconfigurable architecture for RSP on multi-processor
system-on-chip (MPSoC) via hardware-software co-design, word-length
optimization, and serial-parallel configurations. We demonstrate the functional
correctness of the proposed fixed-point architecture and significant savings in
resource utilization (~40-70), execution time (1.5x improvement), and power
consumption (50%) over floating-point architecture. The acceleration on
hardware offers a 120-factor improvement in execution time over the benchmark
Quad-core processor. The proposed architecture enables on-the-fly
reconfigurability to support different azimuth precision and Doppler velocity
resolution, offering a real-time trade-off between functional accuracy and
detection time. We demonstrate end-to-end RSP on MPSoC with a user-friendly
graphical user interface (GUI).
