  Demands on Field-Programmable Gate Array (FPGA) data transport have been
increasing over the years as frame sizes and refresh rates increase. As the
bandwidths requirements increase the ability to implement data transport
protocol layers using "soft" programmable logic becomes harder and start to
require harden IP blocks implementation. To reduce the number of physical links
and interconnects, it is common for data acquisition systems to require
interleaving of streams on the same link (e.g. streaming data and streaming
register access). This paper presents a way to leverage existing FPGA harden IP
blocks to achieve a robust, low latency 100 Gb/s point-to-point link with
minimal programmable logic overhead geared towards the needs of data
acquisition systems with interleaved streaming requirements.
