  Neuromorphic systems typically use the Address-Event Representation (AER) to
transmit signals among nodes, cores, and chips. Communication of Address-Events
(AEs) between neuromorphic cores/chips typically requires two parallel digital
signal buses for Input/Output (I/O) operations. This requirement can become
very expensive for large-scale systems in terms of both dedicated I/O pins and
power consumption. In this paper we present a compact fully asynchronous
event-driven transmitter/receiver block that is both power efficient and I/O
efficient. This block implements high-throughput low-latency bi-directional
communication through a parallel AER bus. We show that by placing the proposed
AE transceiver block in two separate chips and linking them by a single AER
bus, we can drive the communication and switch the transmission direction of
the shared bus on a single event basis, from either side with low-latency. We
present experimental results that validate the circuits proposed and
demonstrate reliable bi-directional event transmission with high-throughput.
The proposed AE block, integrated in a neuromorphic chip fabricated using a 28
nm FDSOI process, occupies a silicon die area of 140 {\mu}m x 70 {\mu}m. The
experimental measurements show that the event-driven AE block combined with
standard digital I/Os has a direction switch latency of 5 ns and can achieve a
worst-case bi-directional event transmission throughput of 28.6M Events/second
while consuming 11 pJ per event (26-bit) delivery.
