  Quantum algorithms need to be compiled to respect the constraints imposed by
quantum processors, which is known as the mapping problem. The mapping
procedure will result in an increase of the number of gates and of the circuit
latency, decreasing the algorithm's success rate. It is crucial to minimize
mapping overhead, especially for Noisy Intermediate-Scale Quantum (NISQ)
processors that have relatively short qubit coherence times and high gate error
rates. Most of prior mapping algorithms have only considered constraints such
as the primitive gate set and qubit connectivity, but the actual gate duration
and the restrictions imposed by the use of shared classical control electronics
have not been taken into account. In this paper, we present a timing and
resource-aware mapper called Qmap to make quantum circuits executable on a
scalable superconducting processor named Surface-17 with the objective of
achieving the shortest circuit latency. In particular, we propose an approach
to formulate the classical control restrictions as resource constraints in a
conventional list scheduler with polynomial complexity. Furthermore, we
implement a routing heuristic to cope with the connectivity limitation. This
router finds a set of movement operations that minimally extends circuit
latency. To analyze the mapping overhead and evaluate the performance of
different mappers, we map 56 quantum benchmarks onto Surface-17. Compared to a
prior mapping strategy that minimizes the number of operations, Qmap can reduce
the latency overhead up to 47.3% and operation overhead up to 28.6%,
respectively.
