  The crosstalk delay associated with global on-chip interconnects becomes more
severe in deep submicron technology, and hence can greatly affect the overall
system performance. Based on a delay model proposed by Sotiriadis et al.,
transition patterns over a bus can be classified according to their delays.
Using this classification, crosstalk avoidance codes (CACs) have been proposed
to alleviate the crosstalk delays by restricting the transition patterns on a
bus. In this paper, we first propose a new classification of transition
patterns, and then devise a new family of CACs based on this classification. In
comparison to the previous classification, our classification has more classes
and the delays of its classes do not overlap, both leading to more accurate
control of delays. Our new family of CACs includes some previously proposed
codes as well as new codes with reduced delays and improved throughput. Thus,
this new family of crosstalk avoidance codes provides a wider variety of
tradeoffs between bus delay and efficiency. Finally, since our analytical
approach to the classification and CACs treats the technology-dependent
parameters as variables, our approach can be easily adapted to a wide variety
of technology.
