  As shown in our previous studies, geometrical field grading techniques such
as stacked and protruding substrate designs cannot well mitigate high electric
stress issue within power electronics modules. However, it was shown that a
combination of protruding substrate design and applying a nonlinear
field-dependent conductivity layer could address the issue. Electric field (E)
simulations were carried out according to IEC 61287-1 for the partial discharge
test measurement step, where a 50/60 Hz AC voltage was applied. However,
dielectrics, including ceramic substrate and silicone gel, in power devices
undergo high temperatures up to a few hundred degrees and frequencies up to 1
MHz. Thus, E values obtained with electrical parameters of the mentioned
dielectrics for room temperature and under 50/60 Hz may not be valid for high
temperatures and frequencies mentioned above. In this paper, we address this
technical gap through developing a finite element method (FEM) E calculation
model developed in COMSOL Multiphysics where E calculations are carried out for
different temperatures up to 250 C and frequencies up to 1 MHz. Using the
model, the influence of temperature and frequency on our proposed electric
field mitigation technique mentioned above is evaluated.
