  High-Level Synthesis (HLS) enables rapid prototyping of complex hardware
designs by translating C or C++ code to low-level RTL code. However, the
testing and evaluation of HLS designs still typically rely on slow RTL-level
simulators that can take hours to provide feedback, especially for complex
designs. A recent work, LightningSim, helps to solve this problem by providing
a simulation workflow one to two orders of magnitude faster than RTL
simulation. However, it still exhibits inefficiencies due to several types of
redundant computation, making it slow for large design simulation and design
space exploration. Addressing these inefficiencies, we introduce
LightningSimV2, a much faster and scalable simulation tool. LightningSimV2
features three main innovations. First, we perform compile-time static
analysis, exploiting the repetitive structures in HLS designs, e.g., loops, to
reduce the simulation workload. Second, we propose a novel graph-based
simulation approach, with decoupled simulation graph construction step and
graph traversal step, significantly reducing repeated computation. Third,
benefiting from the decoupled approach, LightningSimV2 can perform incremental
stall analysis extremely fast, enabling highly efficient design space
exploration of large numbers of complex hardware parameters, e.g., optimal FIFO
depths. Moreover, the DSE is well-suited for parallel computing, further
improving the DSE efficiency. Compared with LightningSim, LightningSimV2
achieves up to 3.5x speedup in full simulation and up to 577x speed up for
incremental DSE. Our code is open-source on GitHub at
https://github.com/sharc-lab/LightningSim/tree/v0.2.0.
