  Non-volatile memory arrays can deploy pre-trained neural network models for
edge inference. However, these systems are affected by device-level noise and
retention issues. Here, we examine damage caused by these effects, introduce a
mitigation strategy, and demonstrate its use in fabricated array of SONOS
(Silicon-Oxide-Nitride-Oxide-Silicon) devices. On MNIST, fashion-MNIST, and
CIFAR-10 tasks, our approach increases resilience to synaptic noise and drift.
We also show strong performance can be realized with ADCs of 5-8 bits
precision.
