  In order to tackle the charge injection issue that had perplexed the counting
type SOI pixel for years, two successive chips CPIXTEG3 and CPIXTEG3b were
developed utilizing two shielding mechanisms, Nested-well and Double-SOI, in
the LAPIS process. A TCAD simulation showed the shielding effectiveness
influenced by the high sheet resistance of shielding layers. Test structures
specially designed to measure the crosstalk associated to charge injection were
implemented in CPIXTEG3/3b. Measurement results proved that using shielding
layer is indispensable for counting type pixel and Double-SOI is superior to
Nested-well in terms of shielding effectiveness and design flexibility.
