  The rapid advancement of energy-efficient parallel ultra-low-power (ULP)
ucontrollers units (MCUs) is enabling the development of autonomous nano-sized
unmanned aerial vehicles (nano-UAVs). These sub-10cm drones represent the next
generation of unobtrusive robotic helpers and ubiquitous smart sensors.
However, nano-UAVs face significant power and payload constraints while
requiring advanced computing capabilities akin to standard drones, including
real-time Machine Learning (ML) performance and the safe co-existence of
general-purpose and real-time OSs. Although some advanced parallel ULP MCUs
offer the necessary ML computing capabilities within the prescribed power
limits, they rely on small main memories (<1MB) and ucontroller-class CPUs with
no virtualization or security features, and hence only support simple
bare-metal runtimes. In this work, we present Shaheen, a 9mm2 200mW SoC
implemented in 22nm FDX technology. Differently from state-of-the-art MCUs,
Shaheen integrates a Linux-capable RV64 core, compliant with the v1.0 ratified
Hypervisor extension and equipped with timing channel protection, along with a
low-cost and low-power memory controller exposing up to 512MB of off-chip
low-cost low-power HyperRAM directly to the CPU. At the same time, it
integrates a fully programmable energy- and area-efficient multi-core cluster
of RV32 cores optimized for general-purpose DSP as well as reduced- and
mixed-precision ML. To the best of the authors' knowledge, it is the first
silicon prototype of a ULP SoC coupling the RV64 and RV32 cores in a
heterogeneous host+accelerator architecture fully based on the RISC-V ISA. We
demonstrate the capabilities of the proposed SoC on a wide range of benchmarks
relevant to nano-UAV applications. The cluster can deliver up to 90GOp/s and up
to 1.8TOp/s/W on 2-bit integer kernels and up to 7.9GFLOp/s and up to
150GFLOp/s/W on 16-bit FP kernels.
