  As integrated circuits have become progressively more complex, constrained
random stimulus has become ubiquitous as a means of stimulating a designs
functionality and ensuring it fully meets expectations. In theory, random
stimulus allows all possible combinations to be exercised given enough time,
but in practice with highly complex designs a purely random approach will have
difficulty in exercising all possible combinations in a timely fashion. As a
result it is often necessary to steer the Design Verification (DV) environment
to generate hard to hit combinations. The resulting constrained-random approach
is powerful but often relies on extensive human expertise to guide the DV
environment in order to fully exercise the design. As designs become more
complex, the guidance aspect becomes progressively more challenging and time
consuming often resulting in design schedules in which the verification time to
hit all possible design coverage points is the dominant schedule limitation.
This paper describes an approach which leverages existing constrained-random DV
environment tools but which further enhances them using supervised learning and
reinforcement learning techniques. This approach provides better than random
results in a highly automated fashion thereby ensuring DV objectives of full
design coverage can be achieved on an accelerated timescale and with fewer
resources.
  Two hardware verification examples are presented, one of a Cache Controller
design and one using the open-source RISCV-Ariane design and Google's RISCV
Random Instruction Generator. We demonstrate that a machine-learning based
approach can perform significantly better on functional coverage and reaching
complex hard-to-hit states than a random or constrained-random approach.
