  Multiresolution Analysis (MRA) is a mathematical method that is based on
working on a problem at different scales. One of its applications is medical
imaging where processing at multiple scales, based on the concept of Gaussian
and Laplacian image pyramids, is a well-known technique. It is often applied to
reduce noise while preserving image detail on different levels of granularity
without modifying the filter kernel. In scientific computing, multigrid methods
are a popular choice, as they are asymptotically optimal solvers for elliptic
Partial Differential Equations (PDEs). As such algorithms have a very high
computational complexity that would overwhelm CPUs in the presence of real-time
constraints, application-specific processors come into consideration for
implementation. Despite of huge advancements in leveraging productivity in the
respective fields, designers are still required to have detailed knowledge
about coding techniques and the targeted architecture to achieve efficient
solutions. Recently, the HIPAcc framework was proposed as a means for automatic
code generation of image processing algorithms, based on a Domain-Specific
Language (DSL). From the same code base, it is possible to generate code for
efficient implementations on several accelerator technologies including
different types of Graphics Processing Units (GPUs) as well as reconfigurable
logic (FPGAs). In this work, we demonstrate the ability of HIPAcc to generate
code for the implementation of multiresolution applications on FPGAs and
embedded GPUs.
