  In the context of the Silicon tracking for a Linear Collider (SiLC) R&D
collaboration, a highly compact mixed-signal chip has been designed in 130nm
CMOS technology intended to read Silicon strip detectors for the experiments at
the future International Linear Collider. The chip includes eighty eight
channels of a full analog signal processing chain and analog to digital
conversion with the corresponding digital controls and readout channels. The
chip is 5x10mm2 where the analog implementation represents 4/5 of the total
Silicon area.
