  Low power design has become one of the most significant requirements when
CMOS technology entered the nanometer era. Therefore, timing budget is often
performed to slow down as many components as possible so that timing slacks can
be applied to reduce the power consumption while maintaining the performance of
the whole design. Retiming is a procedure that involves the relocation of
flip-flops (FFs) across logic gates to achieve faster clocking speed. In this
paper we show that the retiming and slack budgeting problem can be formulated
to a convex cost dual network flow problem. Both the theoretical analysis and
experimental results show the efficiency of our approach which can not only
reduce power consumption by 8.9%, but also speedup previous work by 500 times.
