  Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog
operational properties of DRAM circuitry to enable massively parallel in-DRAM
computation. PuD has the potential to reduce or eliminate costly data movement
between processing elements and main memory. Prior works experimentally
demonstrate three-input MAJ (MAJ3) and two-input AND and OR operations in
commercial off-the-shelf (COTS) DRAM chips. Yet, demonstrations on COTS DRAM
chips do not provide a functionally complete set of operations.
  We experimentally demonstrate that COTS DRAM chips are capable of performing
1) functionally-complete Boolean operations: NOT, NAND, and NOR and 2)
many-input (i.e., more than two-input) AND and OR operations. We present an
extensive characterization of new bulk bitwise operations in 256 off-the-shelf
modern DDR4 DRAM chips. We evaluate the reliability of these operations using a
metric called success rate: the fraction of correctly performed bitwise
operations. Among our 19 new observations, we highlight four major results.
First, we can perform the NOT operation on COTS DRAM chips with a 98.37%
success rate on average. Second, we can perform up to 16-input NAND, NOR, AND,
and OR operations on COTS DRAM chips with high reliability (e.g., 16-input
NAND, NOR, AND, and OR with an average success rate of 94.94%, 95.87%, 94.94%,
and 95.85%, respectively). Third, data pattern only slightly affects bitwise
operations. Our results show that executing NAND, NOR, AND, and OR operations
with random data patterns decreases the success rate compared to all
logic-1/logic-0 patterns by 1.39%, 1.97%, 1.43%, and 1.98%, respectively.
Fourth, bitwise operations are highly resilient to temperature changes, with
small success rate fluctuations of at most 1.66% when the temperature is
increased from 50C to 95C. We open-source our infrastructure at
https://github.com/CMU-SAFARI/FCDRAM
