  This paper investigates the use of Large Language Models (LLMs) for
automating the generation of hardware description code, aiming to explore their
potential in supporting and enhancing the development of efficient neuromorphic
computing architectures. Building on our prior work, we employ OpenAI's
ChatGPT4 and natural language prompts to synthesize a RTL Verilog module of a
programmable recurrent spiking neural network, while also generating test
benches to assess the system's correctness. The resultant design was validated
in three case studies, the exclusive OR,the IRIS flower classification and the
MNIST hand-written digit classification, achieving accuracies of up to 96.6%.
To verify its synthesizability and implementability, the design was prototyped
on a field-programmable gate array and implemented on SkyWater 130 nm
technology by using an open-source electronic design automation flow.
Additionally, we have submitted it to Tiny Tapeout 6 chip fabrication program
to further evaluate the system on-chip performance in the future.
