  Process variations and device aging impose profound challenges for circuit
designers. Without a precise understanding of the impact of variations on the
delay of circuit paths, guardbands, which keep timing violations at bay, cannot
be correctly estimated. This problem is exacerbated for advanced technology
nodes, where transistor dimensions reach atomic levels and established margins
are severely constrained. Hence, traditional worst-case analysis becomes
impractical, resulting in intolerable performance overheads. Contrarily,
process-variation/aging-aware static timing analysis (STA) equips designers
with accurate statistical delay distributions. Timing guardbands that are
small, yet sufficient, can then be effectively estimated. However, such
analysis is costly as it requires intensive Monte-Carlo simulations. Further,
it necessitates access to confidential physics-based aging models to generate
the standard-cell libraries required for STA.
  In this work, we employ graph neural networks (GNNs) to accurately estimate
the impact of process variations and device aging on the delay of any path
within a circuit. Our proposed GNN4REL framework empowers designers to perform
rapid and accurate reliability estimations without accessing transistor models,
standard-cell libraries, or even STA; these components are all incorporated
into the GNN model via training by the foundry. Specifically, GNN4REL is
trained on a FinFET technology model that is calibrated against industrial 14nm
measurement data. Through our extensive experiments on EPFL and ITC-99
benchmarks, as well as RISC-V processors, we successfully estimate delay
degradations of all paths -- notably within seconds -- with a mean absolute
error down to 0.01 percentage points.
