  Logic locking has emerged as a promising solution for protecting the
semiconductor intellectual Property (IP) from the untrusted entities in the
design and fabrication process. Logic locking hides the functionality of the IP
by embedding additional key-gates in the circuit. The correct output of the
chip is produced, once the correct key value is available at the input of the
key-gates. The confidentiality of the key is imperative for the security of the
locked IP as it stands as the lone barrier against IP infringement. Therefore,
the logic locking is considered as a broken scheme once the key value is
exposed. The research community has shown the vulnerability of the logic
locking techniques against different classes of attacks, such as Oracle-guided
and physical attacks. Although several countermeasures have already been
proposed against such attacks, none of them is simultaneously impeccable
against Oracle-guided, Oracle-less, and physical attacks. Under such
circumstances, a defense-in-depth approach can be considered as a practical
approach in addressing the vulnerabilities of logic locking. Defense-in-depth
is a multilayer defense approach where several independent countermeasures are
implemented in the device to provide aggregated protection against different
attack vectors. Introducing such a multilayer defense model in logic locking is
the major contribution of this paper. With regard to this, we first identify
the core components of logic locking schemes, which need to be protected.
Afterwards, we categorize the vulnerabilities of core components according to
potential threats for the locking key in logic locking schemes. Furthermore, we
propose several defense layers and countermeasures to protect the device from
those vulnerabilities. Finally, we turn our focus to open research questions
and conclude with suggestions for future research directions.
