  As the complexity of System-on-Chip (SoC) designs continues to increase,
ensuring thorough verification becomes a significant challenge for system
integrators. The complexity of verification can result in undetected bugs.
Unlike software or firmware bugs, hardware bugs are hard to fix after
deployment and they require additional logic, i.e., patching logic integrated
with the design in advance in order to patch. However, the absence of a
standardized metric for defining "patchability" leaves system integrators
relying on their understanding of each IP and security requirements to engineer
ad hoc patching designs. In this paper, we propose a theoretical patchability
quantification method to analyze designs at the Register Transfer Level (RTL)
with provided patching options. Our quantification defines patchability as a
combination of observability and controllability so that we can analyze and
compare the patchability of IP variations. This quantification is a systematic
approach to estimate each patching architecture's ability to patch at run-time
and complements existing patching works. In experiments, we compare several
design options of the same patching architecture and discuss their differences
in terms of theoretical patchability and how many potential weaknesses can be
mitigated.
