  This dissertation develops hardware that automatically reduces the effective
latency of accessing memory in both single-core and multi-core systems. To
accomplish this, the dissertation shows that all last level cache misses can be
separated into two categories: dependent cache misses and independent cache
misses. Independent cache misses have all of the source data that is required
to generate the address of the memory access available on-chip, while dependent
cache misses depend on data that is located off-chip. This dissertation
proposes that dependent cache misses are accelerated by migrating the
dependence chain that generates the address of the memory access to the memory
controller for execution. Independent cache misses are accelerated using a new
mode for runahead execution that only executes filtered dependence chains. With
these mechanisms, this dissertation demonstrates a 62% increase in performance
and a 19% decrease in effective memory access latency for a quad-core processor
on a set of high memory intensity workloads.
