  Priority-aware networks-on-chip (NoCs) are used in industry to achieve
predictable latency under different workload conditions. These NoCs incorporate
deflection routing to minimize queuing resources within routers and achieve low
latency during low traffic load. However, deflected packets can exacerbate
congestion during high traffic load since they consume the NoC bandwidth.
State-of-the-art analytical models for priority-aware NoCs ignore deflected
traffic despite its significant latency impact during congestion. This paper
proposes a novel analytical approach to estimate end-to-end latency of
priority-aware NoCs with deflection routing under bursty and heavy traffic
scenarios. Experimental evaluations show that the proposed technique
outperforms alternative approaches and estimates the average latency for real
applications with less than 8% error compared to cycle-accurate simulations.
