  We present the design and performance of a prototype ASIC digitizer for
integrated wire chamber readout, implemented in 65 nm commercial CMOS
technology. Each channel of the 4-channel prototype is composed of two 16-bit
Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC),
a front-end preamplifier and shaper, plus digital and analog buffers that
support a variety of digitization chains. The prototype has a multiplexed
digital backend that executes a state machine, distributes control and timing
signals, and buffers data for serial output. Laboratory bench tests measure the
absolute TDC resolution between 74 ps and 480 ps, growing with the absolute
delay, and a relative time resolution of 19 ps. Resolution outliers due to
cross-talk between clock signals and supply or reference voltages are seen.
After calibration, the ADC displays good linearity and noise performance, with
an effective number of bits of 6.9. Under normal operating conditions the
circuit consumes 32 mW per channel. Potential design improvements to address
the resolution drift and tails are discussed.
