  Fabrication errors pose a significant challenge in scaling up solid-state
quantum devices to the sizes required for fault-tolerant (FT) quantum
applications. To mitigate the resource overhead caused by fabrication errors,
we combine two approaches: (1) leveraging the flexibility of a modular
architecture, (2) adapting the procedure of quantum error correction (QEC) to
account for fabrication defects. We simulate the surface code adapted to qubit
arrays with arbitrarily distributed defects to find metrics that characterize
how defects affect fidelity. We then determine the impact of defects on the
resource overhead of realizing a fault-tolerant quantum computer, on a
chiplet-based modular architecture. Our strategy for dealing with fabrication
defects demonstrates an exponential suppression of logical failure where error
rates of non-faulty physical qubits are ~0.1% in a circuit-based noise model.
This is a typical regime where we imagine running the defect-free surface code.
We use our numerical results to establish post-selection criteria for building
a device from defective chiplets. Using our criteria, we then evaluate the
resource overhead in terms of the average number of fabricated physical qubits
per logical qubit. We find that an optimal choice of chiplet size, based on the
defect rate and target fidelity, is essential to limiting any additional error
correction overhead due to defects. When the optimal chiplet size is chosen, at
a defect rate of 1% the resource overhead can be reduced to below 3X and 6X
respectively for the two defect models we use, for a wide range of target
performance. We also determine cutoff fidelity values that help identify
whether a qubit should be disabled or kept as part of the error correction
code.
