  We describe the implementation of Boosted Decision Trees in the hls4ml
library, which allows the translation of a trained model into FPGA firmware
through an automated conversion process. Thanks to its fully on-chip
implementation, hls4ml performs inference of Boosted Decision Tree models with
extremely low latency. With a typical latency less than 100 ns, this solution
is suitable for FPGA-based real-time processing, such as in the Level-1 Trigger
system of a collider experiment. These developments open up prospects for
physicists to deploy BDTs in FPGAs for identifying the origin of jets, better
reconstructing the energies of muons, and enabling better selection of rare
signal processes.
