  More computational resources (i.e., more physical qubits and qubit
connections) on a superconducting quantum processor not only improve the
performance but also result in more complex chip architecture with lower yield
rate. Optimizing both of them simultaneously is a difficult problem due to
their intrinsic trade-off. Inspired by the application-specific design
principle, this paper proposes an automatic design flow to generate simplified
superconducting quantum processor architecture with negligible performance loss
for different quantum programs. Our architecture-design-oriented profiling
method identifies program components and patterns critical to both the
performance and the yield rate. A follow-up hardware design flow decomposes the
complicated design procedure into three subroutines, each of which focuses on
different hardware components and cooperates with corresponding profiling
results and physical constraints. Experimental results show that our design
methodology could outperform IBM's general-purpose design schemes with better
Pareto-optimal results.
