  This paper reports on the design optimization done for Double Sided silicon
microStrip Detectors(DSSDs) to reduce the Equivalent Noise Charge (ENC) and to
maximize the breakdown voltage and Charge Collection Efficiency. Various
isolation techniques have been explored and a detailed comparison has been
studied to optimize the detector performance. For the evaluation of the
performance of the silicon detectors, a radiation damage model has been
included. The neutron fluence is expected to be 2x10^{13}n_{eq} cm$^{-2}$ per
year for five years of expected CBM run with intermediate periods of warm
maintenance, cold maintenance and shutdown. Transient simulations have been
performed to estimate the charge collection performance of the irradiated
detectors and simulations have been verified with experimental data.
