  We present the test results of a low jitter Phase Locked Loop (PLL) prototype
chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based
on the improved version of a clock synthesis circuit named ljCDR from the
Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL
mode. An automatic frequency calibration (AFC) block with the Triple Modular
Redundancy (TMR) register is developed for the LC-oscillator calibration. The
chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip
has been extensively tested, including Total Ionizing Dose (TID) testing up to
300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a
Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.
