  The on-chip implementation of learning algorithms would speed-up the training
of neural networks in crossbar arrays. The circuit level design and
implementation of backpropagation algorithm using gradient descent operation
for neural network architectures is an open problem. In this paper, we proposed
the analog backpropagation learning circuits for various memristive learning
architectures, such as Deep Neural Network (DNN), Binary Neural Network (BNN),
Multiple Neural Network (MNN), Hierarchical Temporal Memory (HTM) and
Long-Short Term Memory (LSTM). The circuit design and verification is done
using TSMC 180nm CMOS process models, and TiO2 based memristor models. The
application level validations of the system are done using XOR problem, MNIST
character and Yale face image databases
