  Charge collection properties of depleted CMOS pixel detector prototypes
produced on p-type substrate of 2 k$\Omega$cm initial resistivity (by LFoundry
150 nm process) were studied using Edge-TCT method before and after neutron
irradiation. The test structures were produced for investigation of CMOS
technology in tracking detectors for experiments at HL-LHC upgrade.
Measurements were made with passive detector structures in which current pulses
induced on charge collecting electrodes could be directly observed. Thickness
of depleted layer was estimated and studied as function of neutron irradiation
fluence. An increase of depletion thickness was observed after first two
irradiation steps to 1$\cdot$10$^{13}$ n/cm$^{2}$ and 5$\cdot$10$^{13}$
n/cm$^{2}$ and attributed to initial acceptor removal. At higher fluences the
depletion thickness at given voltage decreases with increasing fluence because
of radiation induced defects contributing to the effective space charge
concentration. The behaviour is consistent with that of high resistivity
silicon used for standard particle detectors. The measured thickness of the
depleted layer after irradiation with 1$\cdot$10$^{15}$ n/cm$^{2}$ is more than
50 $\mu$m at 100 V bias. This is sufficient to guarantee satisfactory
signal/noise performance on outer layers of pixel trackers in HL-LHC
experiments.
