  High-Level Synthesis (HLS) has transformed the development of complex
Hardware IPs (HWIP) by offering abstraction and configurability through
languages like SystemC/C++, particularly for Field Programmable Gate Array
(FPGA) accelerators in high-performance and cloud computing contexts. These IPs
can be synthesized for different FPGA boards in cloud, offering compact area
requirements and enhanced flexibility. HLS enables designs to execute directly
on ARM processors within modern FPGAs without the need for Register Transfer
Level (RTL) synthesis, thereby conserving FPGA resources. While HLS offers
flexibility and efficiency, it also introduces potential vulnerabilities such
as the presence of hidden circuitry, including the possibility of hosting
hardware trojans within designs. In cloud environments, these vulnerabilities
pose significant security concerns such as leakage of sensitive data, IP
functionality disruption and hardware damage, necessitating the development of
robust testing frameworks. This research presents an advanced testing approach
for HLS-developed cloud IPs, specifically targeting hidden malicious
functionalities that may exist in rare conditions within the design. The
proposed method leverages selective instrumentation, combining greybox fuzzing
and concolic execution techniques to enhance test generation capabilities.
Evaluation conducted on various HLS benchmarks, possessing characteristics of
FPGA-based cloud IPs with embedded cloud related threats, demonstrates the
effectiveness of our framework in detecting trojans and rare scenarios,
showcasing improvements in coverage, time efficiency, memory usage, and testing
costs compared to existing methods.
