  Globalization in the semiconductor industry enables fabless design houses to
reduce their costs, save time, and make use of newer technologies. However, the
offshoring of Integrated Circuit (IC) fabrication has negative sides, including
threats such as Hardware Trojans (HTs) - a type of malicious logic that is not
trivial to detect. One aspect of IC design that is not affected by
globalization is the need for thorough verification. Verification engineers
devise complex assets to make sure designs are bug-free, including assertions.
This knowledge is typically not reused once verification is over. The premise
of this paper is that verification assets that already exist can be turned into
effective security checkers for HT detection. For this purpose, we show how
assertions can be used as online monitors. To this end, we propose a security
metric and an assertion selection flow that leverages Cadence JasperGold
Security Path Verification (SPV). The experimental results show that our
approach scales for industry-size circuits by analyzing more than 100
assertions for different Intellectual Properties (IPs) of the OpenTitan
System-on-Chip (SoC). Moreover, our detection solution is pragmatic since it
does not rely on the HT activation mechanism.
