  In this paper, we present an energy-efficient, yet high-speed approximate
maximally redundant signed digit (MRSD) multiplier (called AMR-MUL) based on a
parallel structure. For the reduction stage, we suggest several approximate
Full-Adder (FA) reduction cells with average positive and negative errors
obtained by simplifying the structure of an exact FA cell. The optimum
selection of these cells for each partial product reduction stage provides the
lowest possible error, turning this task into a design space exploration
problem. We also provide a branch-and-bound design space exploration algorithm
to find the optimal assignment of reduction cells based on a predefined
constraint (i.e., the width of the approximate part) by the user. The
effectiveness of the proposed (Radix-16) multiplier design is assessed under
different digit counts and approximate border column. The results show that the
energy consumption of the MRSD multiplier is reduced by 7x at the cost of a
1.6% accuracy loss.
