  Split manufacturing (SM) and layout camouflaging (LC) are two promising
techniques to obscure integrated circuits (ICs) from malicious entities during
and after manufacturing. While both techniques enable protecting the
intellectual property (IP) of ICs, SM can further mitigate the insertion of
hardware Trojans (HTs). In this paper, we strive for the "best of both worlds,"
that is we seek to combine the individual strengths of SM and LC. By jointly
extending SM and LC techniques toward 3D integration, an up-and-coming paradigm
based on stacking and interconnecting of multiple chips, we establish a modern
approach to hardware security. Toward that end, we develop a security-driven
CAD and manufacturing flow for 3D ICs in two variations, one for IP protection
and one for HT prevention. Essential concepts of that flow are (i) "3D
splitting" of the netlist to protect, (ii) obfuscation of the vertical
interconnects (i.e., the wiring between stacked chips), and (iii) for HT
prevention, a security-driven synthesis stage. We conduct comprehensive
experiments on DRC-clean layouts of multi-million-gate DARPA and OpenCores
designs (and others). Strengthened by extensive security analysis for both IP
protection and HT prevention, we argue that entering the third dimension is
eminent for effective and efficient hardware security.
