  Putting the DRAM on the same package with a processor enables several times
higher memory bandwidth than conventional off-package DRAM. Yet, the latency of
in-package DRAM is not appreciably lower than that of off-package DRAM. A
promising use of in-package DRAM is as a large cache. Unfortunately, most
previous DRAM cache designs mainly optimize for hit latency and do not consider
off-chip bandwidth efficiency as a first-class design constraint. Hence, as we
show in this paper, these designs are suboptimal for use with in-package DRAM.
  We propose a new DRAM cache design, Banshee, that optimizes for both in- and
off-package DRAM bandwidth efficiency without degrading access latency. The key
ideas are to eliminate the in-package DRAM bandwidth overheads due to costly
tag accesses through virtual memory mechanism and to incorporate a
bandwidth-aware frequency-based replacement policy that is biased to reduce
unnecessary traffic to off-package DRAM. Our extensive evaluation shows that
Banshee provides significant performance improvement and traffic reduction over
state-of-the-art latency-optimized DRAM cache designs.
