  Gate-layouts of spin qubit devices are commonly adapted from previous
successful devices. As qubit numbers and the device complexity increase,
modelling new device layouts and optimizing for yield and performance becomes
necessary. Simulation tools from advanced semiconductor industry need to be
adapted for smaller structure sizes and electron numbers. Here, we present a
general approach for electrostatically modelling new spin qubit device layouts,
considering gate voltages, heterostructures, reservoirs and an applied
source-drain bias. Exemplified by a specific potential, we study the influence
of each parameter. We verify our model by indirectly probing the potential
landscape of two design implementations through transport measurements. We use
the simulations to identify critical design areas and optimize for robustness
with regard to influence and resolution limits of the fabrication process.
