  The ATLAS detector at LHC will require a Trigger system to efficiently select
events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC
instantaneous luminosity will be increased up to 3 x 10^34 cm-2s-1, this
represents an unprecedented challenge faced by the ATLAS Trigger system. To
cope with the higher event rate and efficiently select relevant events from a
physics point of view, a new element will be included in the Level-1 Trigger
scheme after 2015: the Topological Processor (L1Topo). The L1Topo system,
currently developed at CERN, will consist initially of an ATCA crate and two
L1Topo modules. A high density opto-electroconverter (AVAGO miniPOD) drives up
to 1.6 Tb/s of data from the calorimeter and muon detectors into two high-end
FPGA (Virtex7-690), to be processed in about 200 ns. The design has been
optimized to guarantee excellent signal in- tegrity of the high-speed links and
low latency data transmission on the Real Time Data Path (RTDP). The L1Topo
receives data in a standalone protocol from the calorimeters and muon detectors
to be processed into several VHDL topological algorithms. Those algorithms
perform geometrical cuts, correlations and calculate complex observables such
as the invariant mass. The output of such topological cuts is sent to the
Central Trigger Processor. This talk focuses on the relevant high-density
design characteristic of L1Topo, which allows several hundreds optical links to
processed (up to 13 Gb/s each) using ordinary PCB material. Relevant test
results performed on the L1Topo prototypes to characterize the high-speed links
latency (eye diagram, bit error rate, margin analysis) and the logic resource
utilization of the algorithms are discussed.
