  Cryogenic microsystems that utilize different 3D integration techniques are
being actively developed, e.g., for the needs of quantum technologies. 3D
integration can introduce opportunities and challenges to the thermal
management of low temperature devices. In this work, we investigate sub-1 K
inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon
chips are interconnected by compression bonding via indium bumps. The total
thermal contact area between the chips is 0.306 mm$^2$ and we find that the
temperature dependence of the inter-chip thermal resistance follows the power
law of $\alpha T^{-3}$, with $\alpha = 7.7-15.4$ K$^4$$\mu$m$^2$/nW. The
$T^{-3}$ relation indicates phononic interfacial thermal resistance, which is
supported by the vanishing contribution of the electrons to the thermal
conduction, due to the superconducting interconnections. Such a thermal
resistance value can introduce a thermalization bottleneck in particular at
cryogenic temperatures. This can be detrimental for some applications, yet it
can also be harnessed. We provide an example of both cases by estimating the
parasitic overheating of a cryogenic flip-chip assembly operated under various
heat loads as well as simulate the performance of solid-state junction
microrefrigerators utilizing the observed thermal isolation.
