  Standard cells are essential components of modern digital circuit designs.
With process technologies advancing toward 2nm, more routability issues have
arisen due to the decreasing number of routing tracks, increasing number and
complexity of design rules, and strict patterning rules. The state-of-the-art
standard cell design automation framework is able to automatically design
standard cell layouts in advanced nodes, but it is still struggling to generate
highly competitive Performance-Power-Area (PPA) and routable cell layouts for
complex sequential cell designs. Consequently, a novel and efficient
methodology incorporating the expertise of experienced human designers to
incrementally optimize the PPA of cell layouts is highly necessary and
essential. High-quality device clustering, with consideration of netlist
topology, diffusion sharing/break and routability in the layouts, can reduce
complexity and assist in finding highly competitive PPA, and routable layouts
faster. In this paper, we leverage the natural language and reasoning ability
of Large Language Model (LLM) to generate high-quality cluster constraints
incrementally to optimize the cell layout PPA and debug the routability with
ReAct prompting. On a benchmark of sequential standard cells in 2nm, we
demonstrate that the proposed method not only achieves up to 19.4% smaller cell
area, but also generates 23.5% more LVS/DRC clean cell layouts than previous
work. In summary, the proposed method not only successfully reduces cell area
by 4.65% on average, but also is able to fix routability in the cell layout
designs.
