  Microarchitectural timing channels enable unwanted information flow across
security boundaries, violating fundamental security assumptions. They leverage
timing variations of several state-holding microarchitectural components and
have been demonstrated across instruction set architectures and hardware
implementations. Analogously to memory protection, Ge et al. have proposed time
protection for preventing information leakage via timing channels. They also
showed that time protection calls for hardware support. This work leverages the
open and extensible RISC-V instruction set architecture (ISA) to introduce the
temporal fence instruction fence.t, which provides the required mechanisms by
clearing vulnerable microarchitectural state and guaranteeing a
history-independent context-switch latency. We propose and discuss three
different implementations of fence.t and implement them on an experimental
version of the seL4 microkernel and CVA6, an open-source, in-order, application
class, 64-bit RISC-V core. We find that a complete, systematic, ISA-supported
erasure of all non-architectural core components is the most effective
implementation while featuring a low implementation effort, a minimal
performance overhead of approximately 2%, and negligible hardware costs.
