  To increase density of superconductor digital and neuromorphic circuits by
10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip,
we developed a new fabrication process on 200-mm wafers, using self-shunted
Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a
layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers
and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet
inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by
two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in
Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced
chemical vapor deposition (PECVD) using
Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of
NbN was investigated to obtain conformal deposition and filling narrow trenches
and vias with high depth-to-width ratios, which was not possible to achieve
using sputtering and other physical vapor deposition (PVD) methods at
temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb
junctions. Nb layers with 200 nm thickness are used in the process layer stack
as ground planes to maintain a high level of interlayer shielding and low
intralayer mutual coupling, for passive transmission lines with wave impedances
matching impedances of JJs, typically <=50 $\Omega$, and for low-value
inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb
bilayers and individual pattering of both layers to form inductors allowed us
to minimize parasitic kinetic inductance associated with interlayer vias and
connections to JJs as well as to increase critical currents of the vias.
Fabrication details and results of electrical characterization of NbN films,
wires, and vias, and comparison with Nb properties are given.
