  A clock synchronizing circuit for repeaterless low swing interconnects is
presented in this paper. The circuit uses a delay locked loop (DLL) to generate
multiple phases of the clock, of which the one closest to the center of the eye
is picked by a phase detector loop. The picked phase is then further fine tuned
by an analog voltage controlled delay to position the sampling clock at the
center of the eye. A clock domain transfer circuit then transfers the sampled
data to the receiver clock domain with a maximum latency of three clock cycles.
The proposed synchronizer has been designed and fabricated in 130 nm UMC MM
CMOS technology. The circuit consumes 1.4 mW from a 1.2 V supply at a data rate
of 1.3 Gbps. Further, the proposed synchronizer has been designed and simulated
in TSMC 65 nm CMOS technology. Post layout simulations show that the
synchronizer consumes 1.5 mW from a 1 V supply, at a data rate of 4 Gbps in
this technology.
