  FPGA accelerators for lightweight neural convolutional networks (LWCNNs) have
recently attracted significant attention. Most existing LWCNN accelerators
focus on single-Computing-Engine (CE) architecture with local optimization.
However, these designs typically suffer from high on-chip/off-chip memory
overhead and low computational efficiency due to their layer-by-layer dataflow
and unified resource mapping mechanisms. To tackle these issues, a novel
multi-CE-based accelerator with balanced dataflow is proposed to efficiently
accelerate LWCNN through memory-oriented and computing-oriented optimizations.
Firstly, a streaming architecture with hybrid CEs is designed to minimize
off-chip memory access while maintaining a low cost of on-chip buffer size.
Secondly, a balanced dataflow strategy is introduced for streaming
architectures to enhance computational efficiency by improving efficient
resource mapping and mitigating data congestion. Furthermore, a resource-aware
memory and parallelism allocation methodology is proposed, based on a
performance model, to achieve better performance and scalability. The proposed
accelerator is evaluated on Xilinx ZC706 platform using MobileNetV2 and
ShuffleNetV2.Implementation results demonstrate that the proposed accelerator
can save up to 68.3% of on-chip memory size with reduced off-chip memory access
compared to the reference design. It achieves an impressive performance of up
to 2092.4 FPS and a state-of-the-art MAC efficiency of up to 94.58%, while
maintaining a high DSP utilization of 95%, thus significantly outperforming
current LWCNN accelerators.
