  The deep trapping gate pixel device was described recently as an alternative
to CMOS 3T pixel. The feasibilty of this device was studied with technological
and transport simulations used in classical electron devices and process
design. A buried gate containing localized deep level centers (Deep Trapping
Gate or DTG) is the key for the operation of this field effect pixel detector.
This can be made with deep levels or a quantum box. This buried gate can
modulates the drain-source current, the same way the upper gate does. This
principle was evaluated with realistic simulations physical parameters and this
shows that the signal magnitude is sufficient for an energy deposition of a
Minimum Ionizing Particle within a limited silicon thickness (a few microns).
We will study here the potential techniques usable for the fabrication of the
device with their drawbacks, advantages and limits. The first technique
introduced is impurity implantation, followed by annealing. The problems
related to the control of the defects in the DTG will be examined in the light
of recent work on ion implantation. As an alternative recent work on quantum
dots opens the possibility to the use Ge dots as a DTG. Ion implantation can
again be used with some limitations. As an alternative to ion implantation an
epitaxial DTG could be fabricated using standard techniques. The first
conclusion of this study is that all the established techniques necessary for
the development of the DTG pixel can reasonably be successful because the
related bottlenecks may be overcome. The deep levels concentration in the DTG
(above 10^18 cm-3) is higher than the concentration of radiation induced
defects for integrated fluences lower than 1x10^16 cm-3.
