  We propose a dedicated winner-take-all circuit to efficiently implement the
intra-column competition between cells in Hierarchical Temporal Memory which is
a crucial part of the algorithm. All inputs and outputs are charge-based for
compatibility with standard CMOS. The circuit incorporates memristors for
competitive advantage to emulate a column with a cell in a predictive state.
The circuit can also detect columns 'bursting' by passive averaging and
comparison of the cell outputs. The proposed spintronic devices and circuit are
thoroughly described and a series of simulations are used to predict the
performance. The simulations indicate that the circuit can complete a
nine-cell, nine-input competition operation in under 15 ns at a cost of about
25 pJ.
