  The presented paper introduces a design for a phase-locked loop (PLL) that is
utilized in frequency synthesis and modulation-demodulation within
communication systems and in VLSI applications. The CMOS PLL is designed using
180 nm Fabrication Technology on Cadence Virtuoso Tool with a supply voltage of
1.8 V. The performance is evaluated through simulations and measurements, which
demonstrate its ability to track and lock onto the input frequency. The PLL is
a frequency synthesizer implemented to generate 2.4 GHz frequency. The input
reference clock from a crystal oscillator is 150 MHz square wave. Negative
feedback is given by divide-by-16 frequency divider, ensuring the phase and
frequency synchronization between the divided signal and the reference signal.
The design has essential components such as a phase frequency detector, charge
pump, loop filter, current-starved voltage-controlled oscillator (CSVCO), and
frequency divider. Through their collaborative operation, the system generates
an output frequency that is 16 times the input frequency. The centre frequency
of the 3-stage CSVCO is 3.208 GHz at 900 mV input voltage. With an input
voltage ranging from 0.4 V to 1.8 V, the VCO offers a tuning range that spans
from 1.066 GHz to 3.731 GHz.PLL demonstrates a lock-in range spanning from 70.4
MHz to 173 MHz, with an output frequency range of 1.12 GHz to 2.78 GHz. It
achieves a lock time of 260.03 ns and consumes a maximum power of 5.15 mW at
2.4 GHz.
