  This paper presents a hardware architecture of fast simplified successive
cancellation (fast-SSC) algorithm for polar codes, which significantly reduces
the decoding latency and dramatically increases the throughput.
Algorithmically, fast-SSC algorithm suffers from the fact that its decoder
scheduling and the consequent architecture depends on the code rate; this is a
challenge for rate-compatible system. However, by exploiting the
homogeneousness between the decoding processes of fast constituent polar codes
and regular polar codes, the presented design is compatible with any rate. The
scheduling plan and the intendedly designed process core are also described.
Results show that, compared with the state-of-art decoder, proposed design can
achieve at least 60% latency reduction for the codes with length N = 1024. By
using Nangate FreePDK 45nm process, proposed design can reach throughput up to
5.81 Gbps and 2.01 Gbps for (1024, 870) and (1024, 512) polar code,
respectively.
