  Predictable execution time upon accessing shared memories in multi-core
real-time systems is a stringent requirement. A plethora of existing works
focus on the analysis of Double Data Rate Dynamic Random Access Memories (DDR
DRAMs), or redesigning its memory to provide predictable memory behavior. In
this paper, we show that DDR DRAMs by construction suffer inherent limitations
associated with achieving such predictability. These limitations lead to 1)
highly variable access latencies that fluctuate based on various factors such
as access patterns and memory state from previous accesses, and 2) overly
pessimistic latency bounds. As a result, DDR DRAMs can be ill-suited for some
real-time systems that mandate a strict predictable performance with tight
timing constraints. Targeting these systems, we promote an alternative off-chip
memory solution that is based on the emerging Reduced Latency DRAM (RLDRAM)
protocol, and propose a predictable memory controller (RLDC) managing accesses
to this memory. Comparing with the state-of-the-art predictable DDR
controllers, the proposed solution provides up to 11x less timing variability
and 6.4x reduction in the worst case memory latency.
