  New technologies such as Quantum-dot Cellular Automata (QCA), Single Electron
Tunneling (SET), Tunneling Phase Logic (TPL) and all-spin logic (ASL) devices
have been widely advocated in nanotechnology as a response to the physical
limits associated with complementary metal oxide semiconductor (CMOS)
technology in atomic scales. Some of their peculiar features are their smaller
size, higher speed, higher switching frequency, lower power consumption, and
higher scale integration. In these technologies, the majority (or minority) and
inverter gates are employed for the production of the functions as this set of
gates makes a universal set of Boolean primitives in these technologies. An
important step in the generation of Boolean functions using the majority gate
is reducing the number of involved gates. In this paper, a multi-objective
synthesis methodology (with the objective priority of gate counts, gate levels
and the number of inverter gates) is presented for finding the minimal number
of possible majority gates in the synthesis of Boolean functions using the
proposed Majority Specification Matrix (MSM) concept. Moreover, based on MSM, a
synthesis flow is proposed for the synthesis of multi-output Boolean functions.
To reveal the efficiency of the proposed method, it is compared with a
meta-heuristic method, multi-objective Genetic Programing (GP). Besides, it is
applied to synthesize MCNC benchmark circuits. The results are indicative of
the outperformance of the proposed method in comparison to multi-objective GP
method. Also, for the MCNC benchmark circuits, there is an average reduction of
10.5% in the number of levels as well as 16.8% and 33.5% in the number of
majority and inverter gates, as compared to the best available method
respectively.
