  Portability of hardware designs between Programmable Logic Devices (PLD) can
be accomplished through the use of device-agnostic hardware description
languages (HDL) such as Verilog or VHDL. Hardware designers can use HDLs to
migrate hardware designs between devices and explore performance, area and
power tradeoffs, as well as, port designs to an alternative device. However, if
design files are corrupt or missing, the portability of the design is lost.
While reverse engineering efforts may be able to recover an HDL-netlist of the
original design, HDL-netlists use device-specific primitives, restricting
portability. Additionally, the recovered design may benefit from other
computational technologies (e.g., $\mu$P, GPGPUs), but is restricted to the
domain of PLDs. In this work, we provide a new framework, vlang, which
automatically maps Verilog-netlists into LLVM's intermediate representation
(IR). The remapped design can use the LLVM-framework to target many device
technologies such as: x86-64 assembly, RISC-V, ARM or to other PLDs with a
modern high-level synthesis tool. Our framework is able to preserve the exact
functionality of the original design within the software executable. The
vlang-produced software executable can be used with other software programs, or
to verify the functionality and correctness of the remapped design. We evaluate
our work with a suite of hardware designs from OpenCores. We compare our
framework against state-of-the-art simulators, thereby outlining our
framework's ability to produce a fully-functional, cycle accurate
software-executable. We also explore the usage of vlang as a front-end for
high-level synthesis tools.
