  Pseudorandom number generation (PRNG) is a key element in hardware security
platforms like field-programmable gate array FPGA circuits. In this article, 18
PRNGs belonging in 4 families (xorshift, LFSR, TGFSR, and LCG) are physically
implemented in a FPGA and compared in terms of area, throughput, and
statistical tests. Two flows of conception are used for Register Transfer Level
(RTL) and High-level Synthesis (HLS). Additionally, the relations between
linear complexity, seeds, and arithmetic operations on the one hand, and the
resources deployed in FPGA on the other hand, are deeply investigated. In order
to do that, a SoC based on Zynq EPP with ARM Cortex-$A9$ MPSoC is developed to
accelerate the implementation and the tests of various PRNGs on FPGA hardware.
A case study is finally proposed using chaotic iterations as a post processing
for FPGA. The latter has improved the statistical profile of a combination of
PRNGs that, without it, failed in the so-called TestU01 statistical battery of
tests.
