  In this work we report a study and a co-design methodology of an analog SNN
crossbar output circuit designed in a 28nm FD-SOI technology node that
comprises a tunable current attenuator and a leak-integrate and fire neurons
that would enable the integration of emerging non-volatile memories (eNVMs) for
synaptic arrays based on various technologies including phase change (PCRAM),
oxide-based (OxRAM), spin transfer and spin orbit torque magnetic memories
(STT, SOT-MRAM). Circuit SPICE simulation results and eNVM experimental data
are used to showcase and estimate the neurons fan-in for each type of eNVM
considering the technology constraints and design trade-offs that set its
limits such as membrane capacitance and supply voltage, etc.
