  For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the
addition of a High Granularity Timing Detector (HGTD) in the forward region to
mitigate the effects of the increased pile-up. The chosen detection technology
is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an
excellent timing resolution below 50 ps. The front-end read-out ASIC must
maintain the performance of the sensor, while keeping low power consumption.
This paper presents the results on the first prototype of a front-end ASIC,
named ALTIROC0, which contains the analog stages (preamplifier and
discriminator) of the read-out chip. The ASIC was characterised both alone and
as part of a module with a 2$\times$2 LGAD array of 1.1$\times$1.1 mm$^2$ pads
bump-bonded to it. The various contributions of the electronics to the time
resolution were investigated in test-bench measurements with a calibration
setup. Both when the ASIC is alone or with a bump-bonded sensor, the jitter of
the ASIC is better than 20 ps for an injected charge of 10 fC. The time walk
effect that arises from the different response of the preamplifier for various
injected charges can be corrected up to 10 ps using a Time Over Threshold
measurement. The combined performance of the ASIC and the LGAD sensor, which
was measured during a beam test campaign in October 2018 with pions of 120 GeV
energy at the CERN SPS, is around 40 ps for all measured modules. All tested
modules show good efficiency and time resolution uniformity.
