  The recent breakthroughs in deep neural networks (DNNs) have spurred a
tremendously increased demand for DNN accelerators. However, designing DNN
accelerators is non-trivial as it often takes months/years and requires
cross-disciplinary knowledge. To enable fast and effective DNN accelerator
development, we propose DNN-Chip Predictor, an analytical performance predictor
which can accurately predict DNN accelerators' energy, throughput, and latency
prior to their actual implementation. Our Predictor features two highlights:
(1) its analytical performance formulation of DNN ASIC/FPGA accelerators
facilitates fast design space exploration and optimization; and (2) it supports
DNN accelerators with different algorithm-to-hardware mapping methods (i.e.,
dataflows) and hardware architectures. Experiment results based on 2 DNN models
and 3 different ASIC/FPGA implementations show that our DNN-Chip Predictor's
predicted performance differs from those of chip measurements of FPGA/ASIC
implementation by no more than 17.66% when using different DNN models, hardware
architectures, and dataflows. We will release code upon acceptance.
