  We propose without loss of generality strategies to achieve a high-throughput
FPGA-based architecture for a QC-LDPC code based on a circulant-1 identity
matrix construction. We present a novel representation of the parity-check
matrix (PCM) providing a multi-fold throughput gain. Splitting of the node
processing algorithm enables us to achieve pipelining of blocks and hence
layers. By partitioning the PCM into not only layers but superlayers we derive
an upper bound on the pipelining depth for the compact representation. To
validate the architecture, a decoder for the IEEE 802.11n (2012) QC-LDPC is
implemented on the Xilinx Kintex-7 FPGA with the help of the FPGA IP compiler
[2] available in the NI LabVIEW Communication System Design Suite (CSDS) which
offers an automated and systematic compilation flow where an optimized hardware
implementation from the LDPC algorithm was generated in approximately 3
minutes, achieving an overall throughput of 608Mb/s (at 260MHz). As per our
knowledge this is the fastest implementation of the IEEE 802.11n QC-LDPC
decoder using an algorithmic compiler.
