  As semiconductor devices continue to scale down, process vari- ations become
more relevant for circuit design. Facing such variations, statistical static
timing analysis is introduced to model variations more accurately so that the
pessimism in tra- ditional worst case timing analysis is reduced. Because all
de- lays are modeled using correlated random variables, most statis- tical
timing methods are much slower than corner based timing analysis. To speed up
statistical timing analysis, we propose a method to extract timing models for
flip-flop and latch based sequential circuits respectively. When such a circuit
is used as a module in a hierarchical design, the timing model instead of the
original circuit is used for timing analysis. The extracted timing models are
much smaller than the original circuits. Ex- periments show that using
extracted timing models accelerates timing verification by orders of magnitude
compared to previ- ous approaches using flat netlists directly. Accuracy is
main- tained, however, with the mean and standard deviation of the clock period
both showing usually less than 1% error compared to Monte Carlo simulation on a
number of benchmark circuits.
