  This paper presents a low hardware consumption, resolution-configurable,
automatically calibrating Gray code oscillator time-to-digital converter (TDC)
in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7
field-programmable gate arrays (FPGAs). The proposed TDC has several
innovations: 1) a sampling matrix to improve the resolution. 2) a virtual bin
calibration method (VBCM) to realize resolution configuration and automatic
calibration. 3) a hardware implementation of the VBCM in standard FPGA devices.
We implemented and evaluated a 16-channel TDC system in all three FPGAs. The
UltraScale+ version achieved the best resolution (least significant bit, LSB)
of 20.97 ps with 0.09 LSB averaged peak-peak differential linearity (DNLpk-pk).
The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps
with 0.10 LSB averaged DNLpk-pk and 34.84 ps with 0.08 LSB averaged DNLpk-pk,
respectively.
