  Machine learning is a computational process. To that end, it is inextricably
tied to computational power - the tangible material of chips and semiconductors
that the algorithms of machine intelligence operate on. Most obviously,
computational power and computing architectures shape the speed of training and
inference in machine learning, and therefore influence the rate of progress in
the technology. But, these relationships are more nuanced than that: hardware
shapes the methods used by researchers and engineers in the design and
development of machine learning models. Characteristics such as the power
consumption of chips also define where and how machine learning can be used in
the real world.
  Despite this, many analyses of the social impact of the current wave of
progress in AI have not substantively brought the dimension of hardware into
their accounts. While a common trope in both the popular press and scholarly
literature is to highlight the massive increase in computational power that has
enabled the recent breakthroughs in machine learning, the analysis frequently
goes no further than this observation around magnitude. This paper aims to dig
more deeply into the relationship between computational power and the
development of machine learning. Specifically, it examines how changes in
computing architectures, machine learning methodologies, and supply chains
might influence the future of AI. In doing so, it seeks to trace a set of
specific relationships between this underlying hardware layer and the broader
social impacts and risks around AI.
