  Integrating workloads with differing criticality levels presents a formidable
challenge in achieving the stringent spatial and temporal isolation
requirements imposed by safety-critical standards such as ISO26262. The shift
towards high-performance multicore platforms has been posing increasing issues
to the so-called mixed-criticality systems (MCS) due to the reciprocal
interference created by consolidated subsystems vying for access to shared
(microarchitectural) resources (e.g., caches, bus interconnect, memory
controller). The research community has acknowledged all these challenges.
Thus, several techniques, such as cache partitioning and memory throttling,
have been proposed to mitigate such interference; however, these techniques
have some drawbacks and limitations that impact performance, memory footprint,
and availability. In this work, we look from a different perspective. Departing
from the observation that safety-critical workloads are typically event- and
thus interrupt-driven, we mask "colored" interrupts based on the \ac{QoS}
assessment, providing fine-grain control to mitigate interference on critical
workloads without entirely suspending non-critical workloads. We propose the
so-called IRQ coloring technique. We implement and evaluate the IRQ Coloring on
a reference high-performance multicore platform, i.e., Xilinx ZCU102. Results
demonstrate negligible performance overhead, i.e., <1% for a 100 microseconds
period, and reasonable throughput guarantees for medium-critical workloads. We
argue that the IRQ coloring technique presents predictability and intermediate
guarantees advantages compared to state-of-art mechanisms
