  Existing high-performance computing (HPC) interconnection architectures are
based on high-radix switches, which limits the injection/local performance and
introduces latency/energy/cost overhead. The new wafer-scale packaging and
high-speed wireline technologies provide high-density, low-latency, and
high-bandwidth connectivity, thus promising to support direct-connected
high-radix interconnection architecture.
  In this paper, we propose a wafer-based interconnection architecture called
Switch-Less-Dragonfly-on-Wafers. By utilizing distributed high-bandwidth
networks-on-chip-on-wafer, costly high-radix switches of the Dragonfly topology
are eliminated while increasing the injection/local throughput and maintaining
the global throughput. Based on the proposed architecture, we also introduce
baseline and improved deadlock-free minimal/non-minimal routing algorithms with
only one additional virtual channel. Extensive evaluations show that the
Switch-Less-Dragonfly-on-Wafers outperforms the traditional switch-based
Dragonfly in both cost and performance. Similar approaches can be applied to
other switch-based direct topologies, thus promising to power future
large-scale supercomputers.
