  We outline the challenges associated with the development and construction of
large focal plane arrays for use both on the ground and in space. Using lessons
learned from existing JPL-led and ASU/JPL partnership efforts to develop
technology for, and design such arrays and imagers for large focal planes, we
enumerate here the remaining problems that need to be solved to make such a
venture viable. Technologies we consider vital for further development include:
(1) architectures, processes, circuits, and readout solutions for production
and integration of four-side buttable, low-cost, high-fidelity,
high-performance, and high-reliability CCD and CMOS imagers; (2) modular,
four-side buttable packaging of CCD/CMOS imagers; (3) techniques and hardware
to test and characterize the large number of chips required to produce the
hundreds of flight-grade detectors needed for large focal-plane missions being
conceived at this time; (4) ground based testbed needs, such as a large format
camera mounted on a ground-based telescope, to field test the detectors and the
focal plane technology solutions; and (5) validation of critical sub-components
of the design on a balloon mission to ensure their flight-readiness. This paper
outlines the steps required to provide a mature solution to the astronomical
community with a minimal investment, building on years of planning and
investments already completed at JPL.
