  Process-related and stress-induced changes in threshold voltage are major
variability concerns in ultra-scaled CMOS transistors. The device designers
consider this variability as an irreducible part of the design problem and use
different circuit level optimization schemes to handle these variations. In
this paper, we demonstrate how an increase in the negative steepness of the
universal mobility relationship improves both the process-related (e.g., oxide
thickness fluctuation, gate work-function fluctuation), as well as
stress-induced or reliability-related (e.g., Bias Temperature Instability or
BTI) parametric variation in CMOS technology. Therefore, we calibrate the
universal mobility parameters to reflect the measured variation of negative
steepness in uniaxially strained CMOS transistor. This allows us to study the
extent of (process-related and stress-induced parametric) variation resilience
in uniaxial strain technology by increasing the negative steepness of the
mobility characteristics. Thus, we show that variability analysis in strained
CMOS technology must consider the presence of self-compensation between
mobility variation and threshold voltage variation, which leads to considerable
amount of variation resilience. Finally, we use detailed circuit simulation to
stress the importance of accurate mobility variation modeling in SPICE analysis
and explain why the variability concerns in strained technology may be less
severe than those in unstrained technology.
