  While standard cell layouts are drawn with minimum design rules for maximum
benefit of design area shrinkage, the complicated design rules begin to cause
difficulties with signal routes accessing the pins in standard cell layouts.
Multiple design iterations are required to resolve routing issues, thus
increasing the runtime and the overall chip area. To optimize the chip
performance, power and area (PPA) and improve the routability, it is necessary
to consider the pin accessibility during standard cell development phase so
that each cell is designed to maximize the number of feasible pin-access
solutions available to the router. As part of the Synopsys IC Compiler Library
Preparation Reference Methodology, the Synopsys Pin Access Checker (PAC)
reports DRC violations associated with the standard cell. Based on Synopsys
PAC's methodology, we demonstrate several methods to improve the probability of
detecting pin accessibility issues, such as reducing the number of cells
required for each Synopsys 'testcell', increasing the complexity of the pin
connectivity assignment and recommending the router constraints.
