  We present a deep, fully convolutional neural network that learns to route a
circuit layout net with appropriate choice of metal tracks and wire class
combinations. Inputs to the network are the encoded layouts containing spatial
location of pins to be routed. After 15 fully convolutional stages followed by
a score comparator, the network outputs 8 layout layers (corresponding to 4
route layers, 3 via layers and an identity-mapped pin layer) which are then
decoded to obtain the routed layouts. We formulate this as a binary
segmentation problem on a per-pixel per-layer basis, where the network is
trained to correctly classify pixels in each layout layer to be 'on' or 'off'.
To demonstrate learnability of layout design rules, we train the network on a
dataset of 50,000 train and 10,000 validation samples that we generate based on
certain pre-defined layout constraints. Precision, recall and $F_1$ score
metrics are used to track the training progress. Our network achieves
$F_1\approx97\%$ on the train set and $F_1\approx92\%$ on the validation set.
We use PyTorch for implementing our model. Code is made publicly available at
https://github.com/sjain-stanford/deep-route .
