  In this paper, we propose a control synthesis method for signal temporal
logic (STL) specifications with neural networks (NNs). Most of the previous
works consider training a controller for only a given STL specification. These
approaches, however, require retraining the NN controller if a new
specification arises and needs to be satisfied, which results in large
consumption of memory and inefficient training. To tackle this problem, we
propose to construct NN controllers by introducing encoder-decoder structured
NNs with an attention mechanism. The encoder takes an STL formula as input and
encodes it into an appropriate vector, and the decoder outputs control signals
that will meet the given specification. As the encoder, we consider three NN
structures: sequential, tree-structured, and graph-structured NNs. All the
model parameters are trained in an end-to-end manner to maximize the expected
robustness that is known to be a quantitative semantics of STL formulae. We
compare the control performances attained by the above NN structures through a
numerical experiment of the path planning problem, showing the efficacy of the
proposed approach.
