  The everlasting demand for higher computing power for deep neural networks
(DNNs) drives the development of parallel computing architectures. 3D
integration, in which chips are integrated and connected vertically, can
further increase performance because it introduces another level of spatial
parallelism. Therefore, we analyze dataflows, performance, area, power and
temperature of such 3D-DNN-accelerators. Monolithic and TSV-based stacked
3D-ICs are compared against 2D-ICs. We identify workload properties and
architectural parameters for efficient 3D-ICs and achieve up to 9.14x speedup
of 3D vs. 2D. We discuss area-performance trade-offs. We demonstrate
applicability as the 3D-IC draws similar power as 2D-ICs and is not thermal
limited.
