  Studying the electrical and structural properties of the interface of the
gate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, with
important implications for understanding and optimizing the performances of
metal-oxide-semiconductor field effect transistor (MOSFETs). In this paper,
near interface oxide traps (NIOTs) in lateral 4H-SiC MOSFETs were investigated
combining transient gate capacitance measurements (C-t) and state of the art
scanning transmission electron microscopy in electron energy loss spectroscopy
(STEM-EELS) with sub-nm resolution. The C-t measurements as a function of
temperature indicated that the effective NIOTs discharge time is temperature
independent and electrons from NIOTs are emitted toward the semiconductor
via-tunnelling. The NIOTs discharge time was modelled taking into account also
the interface state density in a tunnelling relaxation model and it allowed to
locate traps within a tunnelling distance up to 1.3nm from the SiO2/4H-SiC
interface. On the other hand, sub-nm resolution STEM-EELS revealed the presence
of a Non-Abrupt (NA) SiO2/4H-SiC interface. The NA interface shows the
re-arrangement of the carbon atoms in a sub-stoichiometric SiOx matrix. A mixed
sp2/sp3 carbon hybridization in the NA interface region suggests that the
interfacial carbon atoms have lost their tetrahedral SiC coordination.
