  In current computer architectures, data movement (from die to network) is by
far the most energy consuming part of an algorithm (10pJ/word on-die to
10,000pJ/word on the network). To increase memory locality at the hardware
level and reduce energy consumption related to data movement, future exascale
computers tend to use more and more cores on each compute nodes ("fat nodes")
that will have a reduced clock speed to allow for efficient cooling. To
compensate for frequency decrease, machine vendors are making use of long SIMD
instruction registers that are able to process multiple data with one
arithmetic operator in one clock cycle. SIMD register length is expected to
double every four years. As a consequence, Particle-In-Cell (PIC) codes will
have to achieve good vectorization to fully take advantage of these upcoming
architectures. In this paper, we present a new algorithm that allows for
efficient and portable SIMD vectorization of current/charge deposition routines
that are, along with the field gathering routines, among the most time
consuming parts of the PIC algorithm. Our new algorithm uses a particular data
structure that takes into account memory alignement constraints and avoids
gather/scatter instructions that can significantly affect vectorization
performances on current CPUs. The new algorithm was successfully implemented in
the 3D skeleton PIC code PICSAR and tested on Haswell Xeon processors (AVX2-256
bits wide data registers). Results show a factor of $\times 2$ to $\times 2.5$
speed-up in double precision for particle shape factor of order $1$ to $3$. The
new algorithm can be applied as is on future KNL (Knights Landing)
architectures that will include AVX-512 instruction sets with 512 bits register
lengths (8 doubles/16 singles).
