  The Si/SiO$_2$ interface is populated by isolated trap states which modify
its electronic properties. These traps are of critical interest for the
development of semiconductor-based quantum sensors and computers, as well as
nanoelectronic devices. Here, we study the electric susceptibility of the
Si/SiO$_2$ interface with nm spatial resolution using frequency-modulated
atomic force microscopy to measure a patterned dopant delta-layer buried 2 nm
beneath the silicon native oxide interface. We show that surface charge
organization timescales, which range from 1-150 ns, increase significantly
around interfacial states. We conclude that dielectric loss under time-varying
gate biases at MHz and sub-MHz frequencies in metal-insulator-semiconductor
capacitor device architectures is highly spatially heterogeneous over nm length
scales.
  Supplemental GIFs can be found at
https://doi.org/10.6084/m9.figshare.25546687
