  The ability to collect statistics about the execution of a program within a
CPU is of the utmost importance across all fields of computing since it allows
characterizing the timing performance of a program. This capability is even
more relevant in safety-critical software systems, where it is mandatory to
analyze software timing requirements to ensure the correct operation of the
programs. Moreover, in order to properly evaluate and verify the
extra-functional properties of these systems, besides timing performance, there
are many other statistics available on a CPU, such as those associated with
resource utilization. In this paper, we showcase a Performance Measurement
Unit, also known as Hardware Performance Monitor, integrated into a RISC-V
On-Board Computer designed for space applications by our research group. The
monitoring technique features a novel approach whereby the events triggered are
not counted immediately but instead are propagated through the pipeline so that
their annotation is synchronized with the executed instruction. Additionally,
we demonstrate the use of this PMU in a process to characterize the execution
model of the processor. Finally, as an example of the statistics provided by
the PMU, the results obtained running the CoreMark and Dhrystone benchmarks on
the RISC-V OBC are shown.
