  Emergent nanoscale non-volatile memory technologies with high integration
density offer a promising solution to overcome the scalability limitations of
CMOS-based neural networks architectures, by efficiently exhibiting the key
principle of neural computation. Despite the potential improvements in
computational costs, designing high-performance on-chip communication networks
that support flexible, large-fanout connectivity remains as daunting task. In
this paper, we elaborate on the communication requirements of large-scale
neuromorphic designs, and point out the differences with the conventional
network-on-chip architectures. We present existing approaches for on-chip
neuromorphic routing networks, and discuss how new memory and integration
technologies may help to alleviate the communication issues in constructing
next-generation intelligent computing machines.
