  Ring Learning With Error (RLWE) algorithm is used in Post Quantum
Cryptography (PQC) and Homomorphic Encryption (HE) algorithm. The existing
classical crypto algorithms may be broken in quantum computers. The adversaries
can store all encrypted data. While the quantum computer will be available,
these encrypted data can be exposed by the quantum computer. Therefore, the PQC
algorithms are an essential solution in recent applications. On the other hand,
the HE allows operations on encrypted data which is appropriate for getting
services from third parties without revealing confidential plain-texts. The
FPGA based PQC and HE hardware accelerators like RLWE is much cost-effective
than processor based platform and Application Specific Integrated Circuit
(ASIC). FPGA based hardware accelerators still consume more power compare to
ASIC based design. Near Threshold Computation (NTC) may be a convenient
solution for FPGA based RLWE implementation. In this paper, we have implemented
RLWE hardware accelerator which has 14 subcomponents. This paper creates
clusters based on the critical path of all 14 subcomponents. Each cluster is
implemented in an FPGA partition which has the same biasing voltage
$V_{ccint}$. The clusters that have higher critical paths use higher Vccint to
avoid timing failure. The clusters have lower critical paths use lower biasing
voltage Vccint. This voltage scaled, partitioned RLWE can save ~6% and ~11%
power in Vivado and VTR platform respectively. The resource usage and
throughput of the implemented RLWE hardware accelerator is comparatively better
than existing literature.
