  In this work, a rationalized algorithm for calculating the quotient of two
quaternions is presented which reduces the number of underlying real
multiplications. Hardware for fast multiplication is much more expensive than
hardware for fast addition. Therefore, reducing the number of multiplications
in VLSI processor design is usually a desirable task. The performing of a
quaternion division using the naive method takes 16 multiplications, 15
additions, 4 squarings and 4 divisions of real numbers while the proposed
algorithm can compute the same result in only 8 multiplications (or multipliers
in hardware implementation case), 31 additions, 4 squaring and 4 division of
real numbers.
