  An automatic clock synchronizing method implemented in field programmable
gate array (FPGA) is proposed in this paper. It is developed for the clock
system which will be applied in the end-cap time of flight (ETOF) upgrade of
the Beijing Spectrometer (BESIII). In this design, an FPGA is used to
automatically monitor the synchronization circuit and deal with signals coming
from external clock synchronization circuit. By testing different delay time of
the detection signal and analyzing state signals returned, the synchronization
windows will be found automatically in FPGA. The new clock system not only
retains low clock jitter which is less than 20ps root mean square (RMS), but
also demonstrates automatic synchronization to the beam bunches. So far, the
clock auto-synchronizing function has been working successfully under a series
of tests. It will greatly simplify the system initialization and maintenance in
the future.
