  The complexity of modern integrated circuits (ICs) necessitates collaboration
between multiple distrusting parties, including thirdparty intellectual
property (3PIP) vendors, design houses, CAD/EDA tool vendors, and foundries,
which jeopardizes confidentiality and integrity of each party's IP. IP
protection standards and the existing techniques proposed by researchers are ad
hoc and vulnerable to numerous structural, functional, and/or side-channel
attacks. Our framework, Garbled EDA, proposes an alternative direction through
formulating the problem in a secure multi-party computation setting, where the
privacy of IPs, CAD tools, and process design kits (PDKs) is maintained. As a
proof-of-concept, Garbled EDA is evaluated in the context of simulation, where
multiple IP description formats (Verilog, C, S) are supported. Our results
demonstrate a reasonable logical-resource cost and negligible memory overhead.
To further reduce the overhead, we present another efficient implementation
methodology, feasible when the resource utilization is a bottleneck, but the
communication between two parties is not restricted. Interestingly, this
implementation is private and secure even in the presence of malicious
adversaries attempting to, e.g., gain access to PDKs or in-house IPs of the CAD
tool providers.
