  Spin-valley properties in two-dimensional (2D) semiconducting transition
metal dichalcogenides (TMDC) has attracted significant interest due to the
possible applications in quantum computing. Spin-valley properties can be
exploited in TMDC quantum dot (QD) with well-resolved energy levels. This
requires smaller QDs, especially in material systems with heavy carrier
effective mass e.g. TMDCs and silicon. Device architectures employed for TMDC
QDs so far have difficulty achieving smaller QDs. Therefore, an alternative
approach in the device architecture is needed. Here, we propose a multilayer
device architecture to achieve a gate-defined QD in TMDC with a relatively
large energy splitting on the QD. We provide a range of device dimensions and
dielectric thicknesses and its correlation with the QD energy splitting. The
device architecture is modeled realistically. Moreover, we show that all the
device parameters used in modeling are experimentally achievable. These studies
lay the foundation for future work toward spin-valley qubits in TMDCs. The
successful implementation of these device architectures will drive the
technological development of 2D materials-based quantum technologies.
