  Edge-AI computing requires high energy efficiency, low power consumption, and
relatively high flexibility and compact area, challenging the AI-chip design.
This work presents a 0.96 pJ/SOP heterogeneous neuromorphic system-on-chip
(SoC) with fullerene-like interconnection topology for edge-AI computing. The
neuromorphic core integrates different technologies to augment computing energy
efficiency, including sparse computing, partial membrane potential updates, and
non-uniform weight quantization. Multiple neuromorphic cores and multi-mode
routers form a fullerene-like network-on-chip (NoC). The average degree of
communication nodes exceeds traditional topologies by 32%, with a minimal
degree variance of 0.93, allowing advanced decentralized on-chip communication.
Additionally, the NoC can be scaled up through extended off-chip high-level
router nodes. A RISC-V CPU and a neuromorphic processor are tightly coupled and
fabricated within a 5.42 mm^2 die area under 55 nm CMOS technology. The chip
has a low power density of 0.52 mW/mm^2, reducing 67.5% compared to related
works, and achieves a high neuron density of 30.23 K/mm^2. Eventually, the chip
is demonstrated to be effective on different datasets and achieves 0.96 pJ/SOP
energy efficiency.
