  Multiplication is a basic arithmetic operation that is encountered in almost
all general-purpose microprocessing and digital signal processing applications,
and multiplication is physically realized using a multiplier. This paper
discusses the physical implementation of indicating asynchronous multipliers,
which are inherently elastic and are robust to timing, process, and parametric
variations, and are modular. We consider the physical implementation of many
weak-indication asynchronous multipliers using a 32/28-nm CMOS technology by
adopting the array multiplier architecture. The multipliers are synthesized in
a semi-custom ASIC-design style. The 4-phase return-to-zero (RTZ) and the
4-phase return-to-one (RTO) handshake protocols are considered for the data
communication. The multipliers are realized using strong-indication or
weak-indication full adders. Strong-indication 2-input AND function is used to
generate the partial products in the case of both RTZ and RTO handshaking. The
full adders considered are derived from different indicating asynchronous logic
design methods. Among the multipliers considered, a weak-indication
asynchronous multiplier utilizing the biased weak-indication full adder is
found to be efficient in terms of the cycle time and the power-cycle time
product with respect to both RTZ and RTO handshaking. Also, the 4-phase RTO
handshake protocol is found to be preferable than the 4-phase RTZ handshake
protocol for achieving enhanced optimizations in the design metrics.
