  As high-performance computing (HPC) moves into the exascale era, computer
scientists and engineers must find innovative ways of transferring and
processing unprecedented amounts of data. As the scale and complexity of the
applications running on these machines increases, the cost of their
interactions and data exchanges (in terms of latency, energy, runtime, etc.)
can increase exponentially. In order to address I/O coordination and
communication issues, computing vendors are developing an intermediate layer
between compute nodes and the parallel file system composed of different types
of memory (NVRAM, DRAM, SSD). These large scale memory appliances are being
called 'burst buffers.' In this paper, we envision advanced memory at various
levels of HPC hardware and derive potential use cases for how to take advantage
of it. We then present the challenges and issues that arise when utilizing
burst buffers in next-generation supercomputers and map the challenges to the
use cases. Lastly, we discuss the emerging state-of-the-art burst buffer
solutions that are expected to become available by the end of the year in new
HPC systems and which use cases these implementations may satisfy.
