  The Pad Front End Board (pFEB) and the Strip Front End Board (sFEB) are
developed for the ATLAS Phase-I sTGC Trigger Upgrade. The pFEB is used to to
gather and analyze pads trigger, and the sFEB is developed to accept the pad
trigger to define the regions-of-interest for strips readout. The performance
of p/sFEBs must be confirmed before they are mounted on the sTGC detector. We
will present the scanning test system prototype which is designed according to
the test requirements of the p/sFEB. In this test system prototype, a
simulation signal board is developed to generate different types of signal to
the p/sFEB. PC software and FPGA XADC cooperate to achieve the scan test of
analog parameter.
