  The paper describes the design of high performance MIPS Cryptography
processor based on triple data encryption standard. The organization of
pipeline stages in such a way that pipeline can be clocked at high frequency.
Encryption and Decryption blocks of triple data encryption standard (T-DES)
crypto system and dependency among themselves are explained in detail with the
help of block diagram. In order to increase the processor functionality and
performance, especially for security applications we include three new 32-bit
instructions LKLW, LKUW and CRYPT. The design has been synthesized at 40nm
process technology targeting using Xilinx Virtex-6 device. The overall MIPS
Crypto processor works at 209MHz.
