  In this work, we present a class of new designs for reversible binary and BCD
adder circuits. The proposed designs are primarily optimized for the number of
ancilla inputs and the number of garbage outputs and are designed for possible
best values for the quantum cost and delay. First, we propose two new designs
for the reversible ripple carry adder: (i) one with no input carry $c_0$ and no
ancilla input bits, and (ii) one with input carry $c_0$ and no ancilla input
bits. The proposed reversible ripple carry adder designs with no ancilla input
bits have less quantum cost and logic depth (delay) compared to their existing
counterparts in the literature. In these designs, the quantum cost and delay
are reduced by deriving designs based on the reversible Peres gate and the TR
gate. Next, four new designs for the reversible BCD adder are presented based
on the following two approaches: (i) the addition is performed in binary mode
and correction is applied to convert to BCD when required through detection and
correction, and (ii) the addition is performed in binary mode and the result is
always converted using a binary to BCD converter. The proposed reversible
binary and BCD adders can be applied in a wide variety of digital signal
processing applications and constitute important design components of
reversible computing.
