  An ever increasing number of computer vision and image/video processing
challenges are being approached using deep convolutional neural networks,
obtaining state-of-the-art results in object recognition and detection,
semantic segmentation, action recognition, optical flow and superresolution.
Hardware acceleration of these algorithms is essential to adopt these
improvements in embedded and mobile computer vision systems. We present a new
architecture, design and implementation as well as the first reported silicon
measurements of such an accelerator, outperforming previous work in terms of
power-, area- and I/O-efficiency. The manufactured device provides up to 196
GOp/s on 3.09 mm^2 of silicon in UMC 65nm technology and can achieve a power
efficiency of 803 GOp/s/W. The massively reduced bandwidth requirements make it
the first architecture scalable to TOp/s performance.
