  Although next generation (>28 Gbps) SerDes standards have been contemplated
for several years, it has not been clear whether PCB structures supporting 56
Gbps NRZ will be feasible and practical. In this paper, we assess a number of
specific PCB design strategies (related to pin-field breakouts, via stubs, and
fiber weave skew) both through simulation and through measurement of a wide
range of structures on a PCB test vehicle. We demonstrate that conventional
approaches in many cases will not be sufficient, but that modest
(manufacturable) design changes can enable low-skew 56 Gbps NRZ channels having
acceptable insertion and return loss.
