  In recent years, there has been a notable surge in attention towards hardware
security, driven by the increasing complexity and integration of processors,
SoCs, and third-party IPs aimed at delivering advanced solutions. However, this
complexity also introduces vulnerabilities and bugs into hardware systems,
necessitating early detection during the IC design cycle to uphold system
integrity and mitigate re-engineering costs. While the Design Verification (DV)
community employs dynamic and formal verification strategies, they encounter
challenges such as scalability for intricate designs and significant human
intervention, leading to prolonged verification durations. As an alternative
approach, hardware fuzzing, inspired by software testing methodologies, has
gained prominence for its efficacy in identifying bugs within complex hardware
designs. Despite the introduction of various hardware fuzzing techniques,
obstacles such as inefficient conversion of hardware modules into software
models impede their effectiveness. This Systematization of Knowledge (SoK)
initiative delves into the fundamental principles of existing hardware fuzzing,
methodologies, and their applicability across diverse hardware designs.
Additionally, it evaluates factors such as the utilization of golden reference
models (GRMs), coverage metrics, and toolchains to gauge their potential for
broader adoption, akin to traditional formal verification methods. Furthermore,
this work examines the reliability of existing hardware fuzzing techniques in
identifying vulnerabilities and identifies research gaps for future
advancements in design verification techniques.
