  Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are
described in this paper. GDI technique allows reducing power consumption,
propagation delay and low PDP (power delay product) whereas Pass Transistor
Logic (PTL) reduces the count of transistors used to make different logic
gates, by eliminating redundant transistors. Performance comparison with
various Hybrid Adder is been presented. In this paper, we propose two new
designs based on GDI & PTL techniques, which is found to be much more power
efficient in comparison with existing design technique. Only 10 transistors are
used to implement the SUM & CARRY function for both the designs. The SUM and
CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is
implemented and then using XOR as input SUM as well as CARRY cell is
implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed
using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell
is constructed using PTL technique and the CARRY cell is designed using GDI
technique. The advantages of both the designs are discussed. The significance
of these designs is substantiated by the simulation results obtained from
Cadence Virtuoso 180nm environment.
