  When modern FPGA architecture becomes increasingly complicated, modern FPGA
placement is a mixed optimization problem with multiple objectives, including
wirelength, routability, timing closure, and clock feasibility. Typical FPGA
devices nowadays consist of heterogeneous SLICEs like SLICEL and SLICEM. The
resources of a SLICE can be configured to {LUT, FF, distributed RAM, SHIFT,
CARRY}. Besides such heterogeneity, advanced FPGA architectures also bring
complicated constraints like timing, clock routing, carry chain alignment, etc.
The above heterogeneity and constraints impose increasing challenges to FPGA
placement algorithms.
  In this work, we propose a multi-electrostatic FPGA placer considering the
aforementioned SLICEL-SLICEM heterogeneity under timing, clock routing and
carry chain alignment constraints. We first propose an effective SLICEL-SLICEM
heterogeneity model with a novel electrostatic-based density formulation. We
also design a dynamically adjusted preconditioning and carry chain alignment
technique to stabilize the optimization convergence. We then propose a
timing-driven net weighting scheme to incorporate timing optimization. Finally,
we put forward a nested Lagrangian relaxation-based placement framework to
incorporate the optimization objectives of wirelength, routability, timing, and
clock feasibility. Experimental results on both academic and industrial
benchmarks demonstrate that our placer outperforms the state-of-the-art placers
in quality and efficiency.
