  Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful
synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP).
Here, the TSTDP is capable of reproducing the outcomes from a variety of
biological experiments, while the PSTDP rule fails to reproduce them.
Additionally, it has been shown that the behaviour inherent to the spike
rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also
emerge from the TSTDP rule. This paper proposes an analog implementation of the
TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 um
CMOS process and has been simulated using design kits for Synopsys and Cadence
tools. Simulation results demonstrate how well the proposed circuit can alter
synaptic weights according to the timing difference amongst a set of different
patterns of spikes. Furthermore, the circuit is shown to give rise to a
BCM-like learning rule, which is a rate-based rule. To mimic implementation
environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed
circuit. The presented MC simulation analysis and the simulation result from
fine-tuned circuits show that, it is possible to mitigate the effect of process
variations in the proof of concept circuit, however, a practical variation
aware design technique is required to promise a high circuit performance in a
large scale neural network. We believe that the proposed design can play a
significant role in future VLSI implementations of both spike timing and rate
based neuromorphic learning systems.
