  FinFETs have replaced the conventional bulk CMOS transistors in the sub-20nm
technology. One of the key issues to consider is, the vulnerability of FinFET
based circuits to multiple node charge collection due to neutron-induced
strikes. In this paper, we perform a device simulation based characterization
study on representative layouts of 14nm bulk FinFETs in order to study the
extent to which multiple transistors are affected. We find that multiple
transistors do get affected and the impact can last up to five transistors away
(~200nm). We show that the potential of source/drain regions in the
neighborhood of the strike is a significant contributing factor. In the case of
multi-fin FinFETs, the charge collected per fin is seen to reduce as the number
of fins increase. Thus, smaller FinFETs are susceptible to high amounts of
charge collection.
