  Recently, RRAM-based Binary Neural Network (BNN) hardware has been gaining
interests as it requires 1-bit sense-amp only and eliminates the need for
high-resolution ADC and DAC. However, RRAM-based BNN hardware still requires
high-resolution ADC for partial sum calculation to implement large-scale neural
network using multiple memory arrays. We propose a neural network-hardware
co-design approach to split input to fit each split network on a RRAM array so
that the reconstructed BNNs calculate 1-bit output neuron in each array. As a
result, ADC can be completely eliminated from the design even for large-scale
neural network. Simulation results show that the proposed network
reconstruction and retraining recovers the inference accuracy of the original
BNN. The accuracy loss of the proposed scheme in the CIFAR-10 testcase was less
than 1.1% compared to the original network. The code for training and running
proposed BNN models is available at:
https://github.com/YulhwaKim/RRAMScalable_BNN.
