  The extensive use of digital controllers demands a growing effort to prevent
design errors that appear due to finite-word length (FWL) effects. However,
there is still a gap, regarding verification tools and methodologies to check
implementation aspects of control systems. Thus, the present paper describes an
approach, which employs bounded model checking (BMC) techniques, to verify
fixed-point digital controllers represented by state-space equations. The
experimental results demonstrate the sensitivity of such systems to FWL effects
and the effectiveness of the proposed approach to detect them. To the best of
my knowledge, this is the first contribution tackling formal verification
through BMC of fixed-point state-space digital controllers.
