  The use of high-level languages for designing hardware is gaining popularity
since they increase design productivity by providing higher abstractions.
However, one drawback of such abstraction level has been the difficulty of
relating the low-level implementation problems back to the original high-level
design, which is paramount for architectural optimization. In this work
(developed between April 2013 and April 2014), we propose a methodology to
analyze the effects of technology over the architecture, and to generate
architectural-level area, delay and power metrics. Such feedback allows the
designer to quickly gauge the impact of architectural decisions on the quality
of generated hardware and opens the door to automatic architectural analysis.
We demonstrate the use of our technique on three FPGA platforms using two
designs: a Reed-Solomon error correction decoder and a 32-bit pipelined
processor implementation.
