  In view of the tremendous computing power jump of modern RISC processors the
interest in parallel computing seems to be thinning out. Why use a complicated
system of parallel processors, if the problem can be solved by a single
powerful micro-chip? It is a general law, however, that exponential growth will
always end by some kind of a saturation, and then parallelism will again become
a hot topic. We try to prepare ourselves for this eventuality. The MPPC project
started in 1990 in the heydeys of parallelism and produced four ASTRA machines
(presented at CHEP'92) with 4k processors (which are expandable to 16k) based
on `yesterday's chip-technology' (chip presented at CHEP'91). These machines
now provide excellent test-beds for algorithmic developments in a complete,
real environment. We are developing for example fast-pattern recognition
algorithms which could be used in high-energy physics experiments at the LHC
(planned to be operational after 2004 at CERN) for triggering and data
reduction. The basic feature of our ASP (Associative String Processor) approach
is to use extremely simple (thus very cheap) processor elements but in huge
quantities (up to millions of processors) connected together by a very simple
string-like communication chain. In this paper we present powerful algorithms
based on this architecture indicating the performance perspectives if the
hardware (i.e. chip fabrication) quality reaches `present or even future
technology levels'.
