  To mitigate the impact of noise and interference on multi-level-cell (MLC)
flash memory with the use of low-density parity-check (LDPC) codes, we propose
a dynamic write-voltage design scheme considering the asymmetric property of
raw bit error rate (RBER), which can obtain the optimal write voltage by
minimizing a cost function. In order to further improve the decoding
performance of flash memory, we put forward a low-complexity entropy-based
read-voltage optimization scheme, which derives the read voltages by searching
for the optimal entropy value via a log-likelihood ratio (LLR)-aware cost
function. Simulation results demonstrate the superiority of our proposed
dynamic write-voltage design scheme and read-voltage optimization scheme with
respect to the existing counterparts.
