  This paper explains how to develop Verilog hardware description language
(HDL) optimized flow graph compiled simulators. It is claimed that the methods
and algorithms described here can be applied in the development of flow graph
compilers for other complex computer languages. The method uses the von Neumann
computer architecture (MRAM model) as the best abstract model of computation
and uses comparison and selection of alternative machine code sequences to
utilize modern processor low level parallelism. By using the anti formalist
method described here, the fastest available full IEEE 1364 2005 Verilog HDL
standard simulators has been developed. The compiler only required 95,000 lines
of C code and two developers. This paper explains how such a compiled simulator
validates the anti-formalism computer science methodology best expressed by
Peter Naur's datalogy and provides specific guidelines for applying the method.
Development history from a slow interpreter into a fast flow graph based
machine code compiled simulator is described. The failure of initial efforts
that tried to convert a full 1364 compliant interpreter into interpreted
execution of possibly auto generated virtual machines is discussed. The
argument that fast Verilog simulation requires detail removing abstraction is
shown to be incorrect. Reasons parallel GPU Verilog simulation has not
succeeded are given.
