  The design and measurement results of ultra-low power, fast 10-bit Successive
Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65
nm CMOS technology are presented. Eight prototype ADCs were designed using two
different switching schemes of capacitive Digital-to-Analog Converters (DACs),
based on MIM or MOM capacitors, and controlled by standard or low-power SAR
logic. The layout of each ADC prototype is drawn in 60 um pitch to make it
ready for multi-channel implementation. A series of measurements have been made
confirming that all prototypes are fully functional, and six of them achieve
very good quantitative performance. Five out of eight ADCs show both integral
(INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic
measurements performed at 0.1 Nyquist input frequency, the effective number of
bits (ENOB) between 8.9-9.3 was obtained for different ADC prototypes. Standard
ADC versions work up to 80-90 MSps with ENOB between 8.9-9.2 bits at the
highest sampling rate, while the low-power versions work up to above 50 MSps
with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the
sample rate and at 40 MSps it is around 400 uW for the low-power ADCs and just
over 500 uW for the standard ADCs. At 80 MSps the standard ADCs consume about 1
mW.
