  The lack of open-source memory compilers in academia typically causes
significant delays in research and design implementations. This paper presents
an open-source memory compiler that is directly integrated within the Cadence
Virtuoso environment using physical verification tools provided by Mentor
Graphics (Calibre). It facilitates the entire memory generation process from
netlist generation to layout implementation, and physical implementation
verification. To the best of our knowledge, this is the first open-source
memory compiler that has been developed specifically to automate Resistive
Random Access Memory (RRAM) generation. RRAM holds the promise of achieving
high speed, high density and non-volatility. A novel RRAM architecture,
additionally is proposed, and a number of generated RRAM arrays are evaluated
to identify their worst case control line parasitics and worst case settling
time across the memristors of their cells. The total capacitance of lines SEL,
N and P is 5.83 fF/cell, 3.31 fF/cell and 2.48 fF/cell respectively, while the
total calculated resistance for SEL is 1.28 Ohm/cell and 0.14 Ohm/cell for both
N and P lines.
