  Memory designs require timing margins to compensate for aging and fabrication
process variations. With technology downscaling, aging mechanisms became more
apparent, and larger margins are considered necessary. This, in return, means a
larger area requirement and lower performance for the memory. Bias Temperature
Instability (BTI) is one of the main contributors to aging, which slows down
transistors and ultimately causes permanent faults. In this paper, first, we
propose a low-cost aging mitigation scheme, which can be applied to existing
hardware to mitigate aging on memory address decoder logic. We mitigate the BTI
effect on critical transistors by applying a rejuvenation workload to the
memory. Such an auxiliary workload is executed periodically to rejuvenate
transistors that are located on critical paths of the address decoder. Second,
we analyze workloads' efficiency to optimize the mitigation scheme.
Experimental results performed with realistic benchmarks demonstrate
several-times lifetime extension with a negligible execution overhead.
