  Deep Neural Networks have flourished at an unprecedented pace in recent
years. They have achieved outstanding accuracy in fields such as computer
vision, natural language processing, medicine or economics. Specifically,
Convolutional Neural Networks (CNN) are particularly suited to object
recognition or identification tasks. This, however, comes at a high
computational cost, prompting the use of specialized GPU architectures or even
ASICs to achieve high speeds and energy efficiency. ASIC accelerators
streamline the execution of certain dataflows amenable to CNN computation that
imply the constant movement of large amounts of data, thereby turning on-chip
communication into a critical function within the accelerator. This paper
studies the communication flows within CNN inference accelerators of edge
devices, with the aim to justify current and future decisions in the design of
the on-chip networks that interconnect their processing elements. Leveraging
this analysis, we then qualitatively discuss the potential impact of
introducing the novel paradigm of wireless on-chip network in this context.
