  Applications of Binary Neural Networks (BNNs) are promising for embedded
systems with hard constraints on computing power. Contrary to conventional
neural networks with the floating-point datatype, BNNs use binarized weights
and activations which additionally reduces memory requirements. Memristors,
emerging non-volatile memory devices, show great potential as the target
implementation platform for BNNs by integrating storage and compute units. The
energy and performance improvements are mainly due to 1) accelerating
matrix-matrix multiplication as the main kernel for BNNs, 2) diminishing memory
bottleneck in von-Neumann architectures, 3) and bringing massive
parallelization. However, the efficiency of this hardware highly depends on how
the network is mapped and executed on these devices. In this paper, we propose
an efficient implementation of XNOR-based BNN to maximize parallelization while
using a simple sensing scheme to generate activation values. Besides, a new
mapping is introduced to minimize the overhead of data communication between
convolution layers mapped to different memristor crossbars. This comes with
extensive analytical and simulation-based analysis to evaluate the implication
of different design choices considering the accuracy of the network. The
results show that our approach achieves up to $10\times$ energy-saving and
$100\times$ improvement in latency compared to the state-of-the-art in-memory
hardware design.
