  SystemC-based Virtual Prototypes (VPs) at the Electronic System Level (ESL)
are increasingly adopted by the semiconductor industry. The main reason is that
VPs are much earlier available, and their simulation is orders of magnitude
faster in comparison to the hardware models at lower levels of abstraction
(e.g. RTL). This leads designers to use VPs as reference models for early
design verification. Hence, the correctness of VPs is of utmost importance as
undetected errors may propagate to less abstract levels in the design process,
increasing the fixing cost and effort. In this paper, we introduce a
comprehensive simulation-based verification approach to automatically validate
the simulation behavior of a given SystemC-based VP against both the TLM-2.0
rules and its specifications, i.e. functional and timing behavior of
communications in the VP.
