  Triangle counting (TC) is a fundamental problem in graph analysis and has
found numerous applications, which motivates many TC acceleration solutions in
the traditional computing platforms like GPU and FPGA. However, these
approaches suffer from the bandwidth bottleneck because TC calculation involves
a large amount of data transfers. In this paper, we propose to overcome this
challenge by designing a TC accelerator utilizing the emerging
processing-in-MRAM (PIM) architecture. The true innovation behind our approach
is a novel method to perform TC with bitwise logic operations (such as
\texttt{AND}), instead of the traditional approaches such as matrix
computations. This enables the efficient in-memory implementations of TC
computation, which we demonstrate in this paper with computational
Spin-Transfer Torque Magnetic RAM (STT-MRAM) arrays. Furthermore, we develop
customized graph slicing and mapping techniques to speed up the computation and
reduce the energy consumption. We use a device-to-architecture co-simulation
framework to validate our proposed TC accelerator. The results show that our
data mapping strategy could reduce $99.99\%$ of the computation and $72\%$ of
the memory \texttt{WRITE} operations. Compared with the existing GPU or FPGA
accelerators, our in-memory accelerator achieves speedups of $9\times$ and
$23.4\times$, respectively, and a $20.6\times$ energy efficiency improvement
over the FPGA accelerator.
