  In this work we evaluate the potential of FPGAs for accelerating HPC
workloads as a more power-efficient alternative to GPUs. Using High-Level
Synthesis and a large set of optimization techniques, we show that FPGAs can
achieve better performance than CPUs, and better power efficiency than both
CPUs and GPUs for typical HPC workloads. Furthermore, we show that for the
specific case of stencil computation, the unique architectural advantages of
FPGAs allow them to surpass high-end CPU, Xeon Phi and GPU devices. Unlike
previous work, our FPGA-based stencil accelerator combines spatial blocking
with temporal blocking to achieve high performance without restricting input
size. With support for high-order stencils, we achieve the highest single-FPGA
performance for 2D and 3D stencil computation of any order, to this day.
