  The deep learning accelerator is one of the methods to accelerate deep
learning network computations, which is mainly based on convolutional neural
network acceleration. To address the fact that concurrent convolutional neural
network accelerators are not solely open-source and the exclusiveness of
platforms, FusionAccel, a scalable convolutional neural network accelerator
hardware architecture with supporting software is proposed. It can adapt to
different network structures and can be reconstructed before compilation and
reconfigured at runtime. This paper realizes this RTL convolutional neural
network accelerator design and functional verifications on a Xilinx Spartan-6
FPGA. The result is identical to that of Caffe-CPU. Since the entire project is
based on RTL, it can be migrated to ASIC after replacing some FPGA-specific
IPs.
