  Network-on-Chip (NoC) has become a popular choice for connecting a large
number of processing cores in chip multiprocessor design. In a conventional NoC
design, most of the area in the router is occupied by the buffers and the
crossbar switch. These two components also consume the majority of the router's
power. Much of the research in NoC has been based on the conventional router
microarchitecture. We propose a novel router microarchitecture that treats the
router itself as a small network of the ring topology. It eliminates the large
crossbar switch in the conventional design. In addition, network latency is
much reduced. Simulation and circuit synthesis show that the proposed
microarchitecture can reduce the latency, area and power by 53%, 34% and 27%,
respectively, compared to the conventional design.
