  We have developed a quantum annealing processor, based on an array of tunably
coupled rf-SQUID flux qubits, fabricated in a superconducting integrated
circuit process [1]. Implementing this type of processor at a scale of 512
qubits and 1472 programmable inter-qubit couplers and operating at ~ 20 mK has
required attention to a number of considerations that one may ignore at the
smaller scale of a few dozen or so devices. Here we discuss some of these
considerations, and the delicate balance necessary for the construction of a
practical processor that respects the demanding physical requirements imposed
by a quantum algorithm. In particular we will review some of the design
trade-offs at play in the floor-planning of the physical layout, driven by the
desire to have an algorithmically useful set of inter-qubit couplers, and the
simultaneous need to embed programmable control circuitry into the processor
fabric. In this context we have developed a new ultra-low power embedded
superconducting digital-to-analog flux converters (DACs) used to program the
processor with zero static power dissipation, optimized to achieve maximum flux
storage density per unit area. The 512 single-stage, 3520 two-stage, and 512
three-stage flux-DACs are controlled with an XYZ addressing scheme requiring 56
wires. Our estimate of on-chip dissipated energy for worst-case reprogramming
of the whole processor is ~ 65 fJ. Several chips based on this architecture
have been fabricated and operated successfully at our facility, as well as two
outside facilities (see for example [2]).
