  We report a method of fabricating self-aligned, top-gated graphene
field-effect transistors (GFETs) employing polyethyleneimine spin-on-doped
source/drain access regions, resulting in a 2X reduction of access resistance
and a 2.5X improvement in device electrical characteristics, over undoped
devices. The GFETs on Si/SiO$_2$ substrates have high carrier mobilities of up
to 6,300 cm$^2$/Vs. Self-aligned spin-on-doping is applicable to GFETs on
arbitrary substrates, as demonstrated by a 3X enhancement in performance for
GFETs on insulating quartz substrates, which are better suited for radio
frequency applications.
