  We present Versa, an energy-efficient processor with 36 systolic ARM
Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits
algorithm-specific characteristics in order to optimize bandwidth, access
latency, and data reuse. Measured on a set of kernels with diverse data access,
control, and synchronization characteristics, reconfiguration between different
Versa modes yields median energy-efficiency improvements of 11.6x and 37.2x
over mobile CPU and GPU baselines, respectively.
