  - This paper describes a pipeline analog-to-digital converter is implemented
for high speed camera. In the pipeline ADC design, prime factor is designing
operational amplifier with high gain so ADC have been high speed. The other
advantage of pipeline is simple on concept, easy to implement in layout and
have flexibility to increase speed. We made design and simulation using Mentor
Graphics Software with 0.6 \mu m CMOS technology with a total power dissipation
of 75.47 mW. Circuit techniques used include a precise comparator, operational
amplifier and clock management. A switched capacitor is used to sample and
multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The
design operates at 5 V dc. The ADC achieves a SNDR of 44.86 dB. keywords:
pipeline, switched capacitor, clock management
