  Modern communication and computer systems require rapid (Gbps), efficient and
large bandwidth data transfers. Agressive scaling of digital integrated systems
allow buses and communication controller circuits to be integrated with the
microprocessor on the same chip. The Peripheral Component Interconnect Express
(PCIe) protocol handles all communcation between the central processing unit
(CPU) and hardware devices. PCIe buses require efficient clock data recovery
circuits (CDR) to recover clock signals embedded in data during transmission.
This paper describes the theoretical modeling and simulation of a phase-locked
loop (PLL) used in a CDR circuit. A simple PLL architecture for a 5 GHz CDR
circuit is proposed and elaborated in this work. Simulations were carried out
using a Hardware Description Language, Verilog- AMS. The effect of jitter on
the proposed design is also simulated and evaluated in this work. It was found
that the proposed design is robust against both input and VCO jitter.
