  We present a novel approach to pre-silicon verification of processor designs.
The purpose of pre-silicon verification is to find logic bugs in a design at an
early stage and thus avoid time- and cost-intensive post-silicon debugging. Our
approach relies on symbolic quick error detection (Symbolic QED, or SQED). SQED
is targeted at finding logic bugs in a symbolic representation of a design by
combining bounded model checking (BMC) with QED tests. QED tests are powerful
in generating short sequences of instructions (traces) that trigger bugs. We
extend an existing SQED approach with symbolic starting states. This way, we
enable the BMC tool to select starting states arbitrarily when generating a
trace. To avoid false positives, (e.g., traces starting in unreachable states
that may not be-have in accordance with the processor instruction-set
architecture), we define constraints to restrict the set of possible starting
states. We demonstrate that these constraints, togeth-er with reasonable
assumptions about the system behavior, allow us to avoid false positives. Using
our approach, we discovered previously unknown bugs in open-source RISC-V
processor cores that existing methods cannot detect. Moreover, our novel
approach out-performs existing ones in the detection of bugs having long traces
and in the detection of hardware Trojans, i.e., unauthorized modifications of a
design.
