  Rapid design space exploration in early design stage is critical to
algorithm-architecture co-design for accelerators. In this work, a pre-RTL
cycle-accurate accelerator simulator based on SystemC transaction-level
modeling (TLM), AccTLMSim, is proposed for convolutional neural network (CNN)
accelerators. The accelerator simulator keeps track of each bus transaction
between accelerator and DRAM, taking into account the communication bandwidth.
The simulation results are validated against the implementation results on the
Xilinx Zynq. Using the proposed simulator, it is shown that the communication
bandwidth is severely affected by DRAM latency and bus protocol overhead. In
addition, the loop tiling is optimized to maximize the performance under the
constraint of on-chip SRAM size. Furthermore, a new performance estimation
model is proposed to speed up the design space exploration. Thanks to the
proposed simulator and performance estimation model, it is possible to explore
a design space of millions of architectural options within a few tens of
minutes.
