  In this paper, we propose a new hybrid temporal computing (HTC) framework
that leverages both pulse rate and temporal data encoding to design ultra-low
energy hardware accelerators. Our approach is inspired by the recently proposed
temporal computing, or race logic, which encodes data values as single delays,
leading to significantly lower energy consumption due to minimized signal
switching. However, race logic is limited in its applications due to inherent
restrictions. The new HTC framework overcomes these limitations by encoding
signals in both temporal and pulse rate formats for multiplication and in
temporal format for propagation. This approach maintains reduced switch energy
while being general enough to implement a wide range of arithmetic operations.
We demonstrate how HTC multiplication is performed for both unipolar and
bipolar data encoding and present the basic designs for multipliers, adders,
and MAC units. Additionally, we implement two hardware accelerators: a Finite
Impulse Response (FIR) filter and a Discrete Cosine Transform (DCT)/iDCT engine
for image compression and DSP applications. Experimental results show that the
HTC MAC has a significantly smaller power and area footprint compared to the
Unary MAC design and is orders of magnitude faster. Compared to the CBSC MAC,
the HTC MAC reduces power consumption by $45.2\%$ and area footprint by
$50.13\%$. For the FIR design, the HTC design significantly outperforms the
Unary design on all metrics. Compared to the CBSC design, the HTC-based FIR
filter reduces power consumption by $36.61\%$ and area cost by $45.85\%$. The
HTC-based DCT filter retains the quality of the original image with a decent
PSNR, while consuming $23.34\%$ less power and occupying $18.20\%$ less area
than the CBSC MAC-based DCT filter.
