  Using a tight-binding mode-space NEGF technique, we explore the essential
physics, design and performance potential of the III-V core-shell (CS) nanowire
(NW) heterojunction TFET. The CS TFET line-tunneling current increases
significantly with the core diameter $d_{C}$ and outperforms the best III-V
axial point-tunneling NW heterojunction TFET $I_{ON}$ by up to 6x for $d_{C}$ =
6.6 nm. Reaching such a high level of current at low supply voltage, however,
requires and involves specific and sometime unanticipated optimizations and
physics that are thoroughly investigated here. In spite of the commonly
accepted view, we also show and explain the weak gate-length dependency
observed for the line-tunneling current in a III-V TFET. We further investigate
the effect of electron-phonon scattering and discrete-dopant impurity band
tails on optimized CS NW TFETs. Including those non-idealities, the CS-TFET
inverter performance significantly outperforms that of the axial TFETs. The
low-power (LP) VDD = 0.35V CS-inverter delay is comparable to that of the
high-performance (HP) Si CMOS using VDD = 0.55V, which shows promise for a LP
TFET technology with HP speed.
