  The use of third-party IP cores in implementing applications in FPGAs has
given rise to the threat of malicious alterations through the insertion of
hardware Trojans. To address this threat, it is important to predict the way
hardware Trojans are built and to identify their weaknesses. This paper
describes a logic family for implementing robust hardware Trojans, which can
evade the two major detection methods, namely unused-circuit identification and
side-channel analysis. This robustness is achieved by encoding information in
frequency rather than amplitude so that the Trojan trigger circuitry's state
will never stay constant during 'normal' operation. In addition, the power
consumption of Trojan circuits built using the proposed logic family can be
concealed with minimal design effort and supplementary hardware resources.
Defense measures against hardware Trojans with frequency modulation are
described.
