  Rapid single-flux quantum (RSFQ), a leading cryogenic superconductive
electronics (SCE) technology, offers extremely low power dissipation and high
speed. However, implementing RSFQ systems at VLSI complexity faces challenges,
such as substantial area overhead from gate-level pipelining and path
balancing, exacerbated by RSFQ's limited layout density. T1 flip-flop (T1-FF)
is an RSFQ logic cell operating as a pulse counter. Using T1-FF the full adder
function can be realized with only 40% of the area required by the conventional
realization. This cell however imposes complex constraints on input signal
timing, complicating its use. Multiphase clocking has been recently proposed to
alleviate gate-level pipelining overhead. The fanin signals can be efficiently
controlled using multiphase clocking. We present the novel two-stage SFQ
technology mapping methodology supporting the T1-FF. Compatible parts of the
SFQ network are first replaced by the efficient T1-FFs. Multiphase retiming is
next applied to assign clock phases to each logic gate and insert DFFs to
satisfy the input timing. Using our flow, the area of the SFQ networks is
reduced, on average, by 6% with up to 25% reduction in optimizing the 128-bit
adder.
