  Reliability has taken centre stage in the development of high-performance
computing processors. A Surge of interest is noticeable in recent times in
formulating fault and failure models, understanding failure mechanism and
strategizing fault mitigation methods for improving the reliability of the
system. The article presents a congregation of concepts illustrated one after
the other for a better understanding of damages caused by radiation, relevant
fault models, and effects of faults. We examine the state of art fault
mitigation techniques at the logical layer for digital CMOS based design and
SRAM based FPGA. CMOS SRAM structure is the same for both digital CMOS and
FPGA. Understanding of resilient SRAM based FPGA is necessary for developing
resilient prototypes and it facilitates a faster integration of digital CMOS
designs. At the micro-architectural and architectural layer, error detection
and recovery methods are discussed for bus-based multi-core systems. The
Through silicon via based 3D Network on chip is the prospective solution for
integrating many cores on single die. A suitable interconnection approach for
petascale computing on many-core systems. The article presents an elaborate
discussion on fault models, failure mechanisms, resilient 3D routers, defect
tolerance methods for the TSV based 3D NOC many-core systems. Core redundancy,
self-diagnosis and distributed diagnosis at the hardware level are examined for
many-core systems. The article presents a gamut of fault tolerance solutions
from logic level to processor core level in a multi-core and many-core
scenario.
