  NoCs have become a widespread paradigm in the system-on-chip design world,
not only for multi-purpose SoCs, but also for application-specific ICs. The
common approach in the NoC design world is to separate the design of the
interconnection from the design of the processing elements: this is well suited
for a large number of developments, but the need for joint application and NoC
design is not uncommon, especially in the application specific case. The
correlation between processing and communication tasks can be strong, and
separate or trace-based simulations fall often short of the desired precision.
In this work, the OMNET++ based JANoCS simulator is presented: concurrent
simulation of processing and communication allow cycle-accurate evaluation of
the system. Two cases of study are presented, showing both the need for joint
simulations and the effectiveness of JANoCS.
