  RISC-V is a RISC based open and loyalty free instruction set architecture
which has been developed since 2010, and can be used for cost-effective soft
processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is
defined as RV32I, which is sufficient to support the operating system
environment and suits for embedded systems. In this paper, we propose an
optimized RV32I soft processor named RVCoreP adopting five-stage pipelining.
The processor applies three effective optimization methods to improve the
operating frequency. These methods are instruction fetch unit optimization
including pipelined branch prediction mechanism, ALU optimization, and data
alignment and sign-extension optimization for data memory output. We implement
RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an
actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle),
operating frequency, hardware resource utilization, and processor performance.
From the evaluation results, we show that RVCoreP achieves 30.0% performance
improvement compared with VexRiscv, which is a high-performance and open source
RV32I processor selected from some related works.
