  A hierarchical approach to the construction of compound distributions for
process-induced faults in IC manufacture is proposed. Within this framework,
the negative binomial distribution is treated as level-1 models. The
hierarchical approach to fault distribution offers an integrated picture of how
fault density varies from region to region within a wafer, from wafer to wafer
within a batch, and so on. A theory of compound-distribution hierarchies is
developed by means of generating functions. A study of correlations, which
naturally appears in microelectronics due to the batch character of IC
manufacture, is proposed. Taking these correlations into account is of
significant importance for developing procedures for statistical quality
control in IC manufacture. With respect to applications, hierarchies of yield
means and yield probability-density functions are considered.
