  In this paper, we propose a Junctionless (JL)/Accumulation Mode (AM)
transistor with an access transistor (JL in series with JL/AM transistor) based
capacitorless Dynamic Random Access Memory (1TDRAM) cell. The JL transistor
overcomes the problem of ultrasharp p-n junction associated with conventional
Metal-Oxide-Semiconductor (MOS) in nanoscale regime. The access transistor (AT)
is utilized to reduces the leakage, and thus, improves the Retention Time (RT)
and Sense Margin (SM) of the proposed capacitorless DRAM cell. Thus, the
proposed DRAM cell achieved a maximum SM of ~4.6 {\mu}A/{\mu}m with RT of ~6.5
s for a gate length (Lg) of 100nm. Further, this topology shows better gate
length scalability with a fixed gate length of AT and achieves RT of ~100 ms
and ~10 ms for a scaled gate length of 10 nm at 27 {\deg}C and 85 {\deg}C,
respectively.
