  The implementation of a quaternary 1-digit adder composed of a 2-bit binary
adder, quaternary to binary decoders and binary to quaternary encoders is
compared with several recent implementations of quaternary adders. This simple
implementation outperforms all other implementations using only one power
supply. It is equivalent to the best other implementation using three power
supplies. The best quaternary adder using a 2-bit binary adder, the interface
circuits between quaternary and binary levels are just overhead compared to the
binary adder. This result shows that the quaternary approach for adders use
more transistors, more chip area and more power dissipation than the
corresponding binary ones.
