  Neuromorphic computing has the potential to further the success of
software-based artificial neural networks (ANNs) by designing hardware from a
different perspective. Current research in neuromorphic hardware targets
dramatic improvements to ANN performance by increasing energy efficiency, speed
of operation, and even seeks to extend the utility of ANNs by natively adding
functionality such as spiking operation. One promising neuromorphic hardware
platform is based on superconductive electronics, which has the potential to
incorporate all of these advantages at the device level in addition to offering
the potential of near lossless communications both within the neuromorphic
circuits as well as between disparate superconductive chips. Here we explore
one of the fundamental brain-inspired architecture components, the fan-in and
fan-out as realized in superconductive circuits based on Josephson junctions.
From our calculations and WRSPICE simulations we find that the fan-out should
be limited only by junction count and circuit size limitations, and we
demonstrate results in simulation at a level of 1-to-10,000, similar to that of
the human brain. We find that fan-in has more limitations, but a fan-in level
on the order of a few 100-to-1 should be achievable based on current
technology. We discuss our findings and the critical parameters that set the
limits on fan-in and fan-out in the context of superconductive neuromorphic
circuits.
