  We show that the quantum parity gate on $n > 3$ qubits cannot be cleanly
simulated by a quantum circuit with two layers of arbitrary C-SIGN gates of any
arity and arbitrary 1-qubit unitary gates, regardless of the number of allowed
ancilla qubits. This is the best known and first nontrivial separation between
the parity gate and circuits of this form. The same bounds also apply to the
quantum fanout gate. Our results are incomparable with those of Fang et al.
[3], which apply to any constant depth but require a sublinear number of
ancilla qubits on the simulating circuit.
