  The ever-increasing computational and storage requirements of modern
applications and the slowdown of technology scaling pose major challenges to
designing and implementing efficient computer architectures. In this paper, we
leverage the architectural balance principle to alleviate the bandwidth
bottleneck at the L1 data memory boundary of a tightly-coupled cluster of
processing elements (PEs). We thus explore coupling each PE with an L0 memory,
namely a private register file implemented as Standard Cell Memory (SCM).
Architecturally, the SCM is the Vector Register File (VRF) of Spatz, a compact
64-bit floating-point-capable vector processor based on RISC-V's Vector
Extension Zve64d. Unlike typical vector processors, whose VRF are hundreds of
KiB large, we prove that Spatz can achieve peak energy efficiency with a VRF of
only 2 KiB. An implementation of the Spatz-based cluster in GlobalFoundries'
12LPP process with eight double-precision Floating Point Units (FPUs) achieves
an FPU utilization just 3.4% lower than the ideal upper bound on a
double-precision, floating-point matrix multiplication. The cluster reaches 7.7
FMA/cycle, corresponding to 15.7 GFLOPS-DP and 95.7 GFLOPS-DP/W at 1 GHz and
nominal operating conditions (TT, 0.80V, 25^oC) with more than 55% of the power
spent on the FPUs. Furthermore, the optimally-balanced Spatz-based cluster
reaches a 95.0% FPU utilization (7.6 FMA/cycle), 15.2 GFLOPS-DP, and 99.3
GFLOPS-DP/W (61% of the power spent in the FPU) on a 2D workload with a 7x7
kernel, resulting in an outstanding area/energy efficiency of 171
GFLOPS-DP/W/mm^2. At equi-area, our computing cluster built upon compact vector
processors reaches a 30% higher energy efficiency than a cluster with the same
FPU count built upon scalar cores specialized for stream-based floating-point
computation.
