  The ubiquitous use of sensing and signal processing is increasing
exponentially with the advance of the Internet of Everything (IoE). In this
context, the design of every time more power efficient sensor nodes is a must.
Within these nodes, one of the most power-hungry components are the
analog-to-digital converters (ADC). These components are used everywhere to
translate real-world analog signals into computer intelligible digital signals.
One of the promising architecture for the sensing of physiological signals is
the level crossing ADC due to the sparse characteristics of those signals. One
of the challenges to improve the power efficiency of this type of ADC lies in
the use of continuous comparators to keep track of the input signal within the
voltage references. The aim of this work is to investigate the impact of using
continuous comparator which can be turned off without incurring error to the
conversion of the level crossing ADC. New boundaries will be set for the
correct behavior of the level crossing ADC together with the conditions for
power saving with the proposed architecture. A 1V 5-bits level crossing ADC was
implemented using the TSMC 0.18um process and fabricated for laboratory
measurements. The ADC consumes 12.2uW during tracking state and with the
proposed technique, the reduction of the average power can go from 4.2% to
45.5% depending on the activity and the type of the input signal.
