  The foreseen Phase 2 pixel upgrades at the LHC have very challenging
requirements for the design of hybrid pixel readout chips. A versatile pixel
simulation platform is as an essential development tool for the design,
verification and optimization of both the system architecture and the pixel
chip building blocks (Intellectual Properties, IPs). This work is focused on
the implemented simulation and verification environment named VEPIX53, built
using the SystemVerilog language and the Universal Verification Methodology
(UVM) class library in the framework of the RD53 Collaboration. The environment
supports pixel chips at different levels of description: its reusable
components feature the generation of different classes of parameterized input
hits to the pixel matrix, monitoring of pixel chip inputs and outputs,
conformity checks between predicted and actual outputs and collection of
statistics on system performance. The environment has been tested performing a
study of shared architectures of the trigger latency buffering section of pixel
chips. A fully shared architecture and a distributed one have been described at
behavioral level and simulated; the resulting memory occupancy statistics and
hit loss rates have subsequently been compared.
