  It has been widely acknowledged that Very Long Baseline Interferometry (VLBI)
in the submillimeter wavelengths can make imaging observations of super massive
black holes possible. The Sub-Millimeter Array (SMA) along with the James Clerk
Maxwell Telescope (JCMT) and Caltech Submillimeter Observatory (CSO) on the
Mauna Kea summit in Hawaii can together provide a large collecting area as one
or more stations for VLBI observations aimed at studying an event horizon. To
work as a VLBI station with full collecting area the SMA (or a combination SMA,
JCMT, CSO antennas) would need a processor to enable phased array operation.
This masters project focusses on building such a processor. Back end processing
for high bandwidth radio telescopes has traditionally been done using custom
designed application specific integrated circuits (ASIC). Recent advances in
Field Programmable Gate Array (FPGA) technology have made FPGAs both powerful
and economically viable for radio astronomy back ends. We have attempted to
take advantage of these advances and built a proof-of-concept 500 MHz phased
array processor for the SMA using FPGAs. The phased array processing is done in
the time domain using high speed sampling and digital delay lines. The design
is capable of spooling the phased sum to a Mark 5b VLBI data recorder. It is
based on hardware built by the Berkeley Wireless Research Center and the
Berkeley Space Science Laboratory. We digitize signals after the 1st SMA
downconvertor using 1024 MHz sampling and have demonstrated the capability to
sum signals from 8 antennas through programmable digital delay lines up to a
precision of (approx) 1/10 the sampling rate i.e. 0.1 ns. To calibrate
geometric, atmospheric and instrument delays for accurate phasing, a single
baseline 512 MHz 32 channel FX correlator has also been designed to fit on a
single FPGA chip.
