  The k-means algorithm is one of the most common clustering algorithms and
widely used in data mining and pattern recognition. The increasing
computational requirement of big data applications makes hardware acceleration
for the k-means algorithm necessary. In this paper, a simplified Map-Reduce
architecture is proposed to implement the k-means algorithm on an FPGA.
Algorithmic segmentation, data path elaboration and automatic control are
applied to optimize the architecture for high performance. In addition, high
level synthesis technique is utilized to reduce development cycles and
complexity. For a single iteration in the k-means algorithm, a throughput of
28.74 Gbps is achieved. The performance shows at least 3.93x speedup compared
with four representative existing FPGA-based implementations and can satisfy
the demand of big data applications.
