  CMOS-transistors circuits have been used as a conventional approach for
designing an analog multiplier in modern era of industrial electronics.
However, previous studies have shown, that based on the working region of
transistors, such as saturation or weak inversion regions, the circuit may face
issues with output ranges and accuracy. One possible solution to that problem
could be choosing CMOS-memristors as a basis for the circuit. Although
memristor research is still a growing and promising field, one could argue that
its implementation could bring many benefits such as increased circuit density
and superior computation speeds, etc. Additionally, the era of Moore's Law of
downscaling the size of transistors is to eventually come to an end. No one
knows whether the end of a scaling paradigm is to happen within the next five
or twenty years. Hence, the research on this particular subject is quite
important. This paper proposes an analog multiplier design with CMOS and
memristive components. Mainly, the aim of the paper is to compare the power
consumption and overall characteristic of the multiplier such as the accuracy
and the output range to that of the conventional multiplier. The designed
circuit is expected to be suitable for low power applications, and it is built
using 18um CMOS technology. The circuit simulations will be conducted using
SPICE software. Finally, the effects of channel modulation and temperature on
the multiplier performance will be discussed.
