  A switched-capacitor matrix multiplier is presented for approximate computing
and machine learning applications. The multiply-and-accumulate operations
perform discrete-time charge-domain signal processing using passive switches
and 300 aF unit capacitors. The computation is digitized with a 6 b
asynchronous successive approximation register analog-to-digital converter. The
analyses of incomplete charge accumulation and thermal noise are discussed. The
design was fabricated in 40 nm CMOS, and experimental measurements of
multiplication are illustrated using matched filtering and image convolutions
to analyze noise and offset. Two applications are highlighted: 1)
energy-efficient feature extraction layer performing both compression and
classification in a neural network for an analog front end and 2) analog
acceleration for solving optimization problems that are traditionally performed
in the digital domain. The chip obtains measured efficiencies of 8.7 TOPS/W at
1 GHz for the first application and 7.7 TOPS/W at 2.5 GHz for the second
application.
