  One of the major barriers that CMOS devices face at nanometer scale is
increasing parameter variation due to manufacturing imperfections. Process
variations severely inhibit the reliable operation of circuits, as the
operational frequency at the nominal process corner is insufficient to suppress
timing violations across the entire variability spectrum. To avoid
variability-induced timing errors, previous efforts impose pessimistic and
performance-degrading timing guardbands atop the operating frequency. In this
work, we employ approximate computing principles and propose a circuit-agnostic
automated framework for generating variability-aware approximate circuits that
eliminate process-induced timing guardbands. Variability effects are accurately
portrayed with the creation of variation-aware standard cell libraries, fully
compatible with standard EDA tools. The underlying transistors are fully
calibrated against industrial measurements from Intel 14nm FinFET in which both
electrical characteristics of transistors and variability effects are
accurately captured. In this work, we explore the design space of approximate
variability-aware designs to automatically generate circuits of reduced
variability and increased performance without the need for timing guardbands.
Experimental results show that by introducing negligible functional error of
merely $5.3\times 10^{-3}$, our variability-aware approximate circuits can be
reliably operated under process variations without sacrificing the application
performance.
