  DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system
performance by interfering with memory accesses. As DRAM chip density increases
with technology node scaling, refresh operations also increase because: 1) the
number of DRAM rows in a chip increases; and 2) DRAM cells need additional
refresh operations to mitigate bit failures caused by RowHammer, a failure
mechanism that becomes worse with technology node scaling. Thus, it is critical
to enable refresh operations at low performance overhead. To this end, we
propose a new operation, Hidden Row Activation (HiRA), and the HiRA Memory
Controller (HiRA-MC).
  HiRA hides a refresh operation's latency by refreshing a row concurrently
with accessing or refreshing another row within the same bank. Unlike prior
works, HiRA achieves this parallelism without any modifications to
off-the-shelf DRAM chips. To do so, it leverages the new observation that two
rows in the same bank can be activated without data loss if the rows are
connected to different charge restoration circuitry. We experimentally
demonstrate on 56% real off-the-shelf DRAM chips that HiRA can reliably
parallelize a DRAM row's refresh operation with refresh or activation of any of
the 32% of the rows within the same bank. By doing so, HiRA reduces the overall
latency of two refresh operations by 51.4%.
  HiRA-MC modifies the memory request scheduler to perform HiRA when a refresh
operation can be performed concurrently with a memory access or another
refresh. Our system-level evaluations show that HiRA-MC increases system
performance by 12.6% and 3.73x as it reduces the performance degradation due to
periodic refreshes and refreshes for RowHammer protection (preventive
refreshes), respectively, for future DRAM chips with increased density and
RowHammer vulnerability.
