  Transistor random mismatch continuously poses challenges for analog/RF
circuit design for achieving high accuracy and high yield as the process
technology advances. Existing statistical element selection (SES) design method
can improve transistor matching property, but it falls short of being a general
calibration method due to its limited calibration range. In this dissertation,
we propose a high resolution digital calibration method, called extended
statistical element selection (ESES). As compared to the SES method, the ESES
method not only provides wider calibration range, but also it results in higher
calibration yield with same calibration resolution target. Two types of ESES
based calibration application in analog/RF circuits are also proposed. One is
current source calibration and the other is phase/delay calibration. To verify
this proposed digital calibration method in circuit implementation, we
designed, fabricated and tested a wideband harmonic rejection receiver design.
The receiver utilizes ESES-based gain and phase error calibration for improving
harmonic rejection ratios. With the high calibration resolution provided by the
ESES method, after calibration, we achieved best-in-class harmonic rejection
ratios. To extend the application of the proposed method, we further designed a
current-steering D/A data converter (CS-DAC). The CS-DAC utilizes ESES-based
amplitude and timing error calibration for improving linearity performance.
Simulation results showed that we can achieve more than one order of magnitude
linearity improvement after performing ESES-based calibration in the CS-DAC.
