  Presently with technology node scaling, an accurate prediction model at early
design stages can significantly reduce the design cycle. Especially during
logic synthesis, predicting cell congestion due to improper logic combination
can reduce the burden of subsequent physical implementations. There have been
attempts using Graph Neural Network (GNN) techniques to tackle congestion
prediction during the logic synthesis stage. However, they require informative
cell features to achieve reasonable performance since the core idea of GNNs is
built on the message passing framework, which would be impractical at the early
logic synthesis stage. To address this limitation, we propose a framework that
can directly learn embeddings for the given netlist to enhance the quality of
our node features. Popular random-walk based embedding methods such as
Node2vec, LINE, and DeepWalk suffer from the issue of cross-graph alignment and
poor generalization to unseen netlist graphs, yielding inferior performance and
costing significant runtime. In our framework, we introduce a superior
alternative to obtain node embeddings that can generalize across netlist graphs
using matrix factorization methods. We propose an efficient mini-batch training
method at the sub-graph level that can guarantee parallel training and satisfy
the memory restriction for large-scale netlists. We present results utilizing
open-source EDA tools such as DREAMPLACE and OPENROAD frameworks on a variety
of openly available circuits. By combining the learned embedding on top of the
netlist with the GNNs, our method improves prediction performance, generalizes
to new circuit lines, and is efficient in training, potentially saving over $90
\%$ of runtime.
