  In this paper, the acceleration of algorithms using a design of a field
programmable gate array (FPGA) as a prototype of a static dataflow architecture
is discussed. The static dataflow architecture using operators interconnected
by parallel buses was implemented. Accelerating algorithms using a dataflow
graph in a reconfigurable system shows the potential for high computation
rates. The results of benchmarks implemented using the static dataflow
architecture are reported at the end of this paper.
