  Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to
edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL
modeling compared to slow simulations. However, realistic test stimuli are
challenging to generate in hardware for diverse applications. In other words,
both a fast and flexible design framework is required. The most promising
solution is hybrid emulation, in which parts of the design are simulated in
software, and the other parts are emulated in hardware. This paper proposes a
novel hybrid emulation framework called EmuNoC. We introduce a
clock-synchronization method and software-only packet generation that improves
the emulation speed by 36.3x to 79.3x over state-of-the-art frameworks while
retaining the flexibility of a pure-software interface for stimuli simulation.
We also increased the area efficiency to model up to an NoC with 169 routers on
a single FPGA, while previous frameworks only achieved 64 routers.
