  Typical semiconductor chips include thousands of mostly small memories. As
memories contribute an estimated 25% to 40% to the overall power, performance,
and area (PPA) of a chip, memories must be designed carefully to meet the
system's requirements. Memory arrays are highly uniform and can be described by
approximately 10 parameters depending mostly on the complexity of the
periphery. Thus, to improve PPA utilization, memories are typically generated
by memory compilers. A key task in the design flow of a chip is to find optimal
memory compiler parametrizations which on the one hand fulfill system
requirements while on the other hand optimize PPA. Although most compiler
vendors also provide optimizers for this task, these are often slow or
inaccurate. To enable efficient optimization in spite of long compiler run
times, we propose training fully connected feed-forward neural networks to
predict PPA outputs given a memory compiler parametrization. Using an
exhaustive search-based optimizer framework which obtains neural network
predictions, PPA-optimal parametrizations are found within seconds after chip
designers have specified their requirements. Average model prediction errors of
less than 3%, a decision reliability of over 99% and productive usage of the
optimizer for successful, large volume chip design projects illustrate the
effectiveness of the approach.
