  This paper proposes a new logic optimization paradigm based on circuit
simulation, which reduces the need for Boolean computations such as SAT-solving
or constructing BDDs. The paper develops a Boolean resubstitution framework to
demonstrate the effectiveness of the proposed approach. Methods to generate
highly expressive simulation patterns are developed, and the generated patterns
are used in resubstitution for efficient filtering of potential resubstitution
candidates to reduce the need for SAT validation. Experimental results show
that improvements in circuit size reduction were achieved by up to 74%,
compared to a state-of-the-art resubstitution algorithm.
