  Analog to Digital Converters (ADCs) are a major contributor to the power
consumption of multiple-input multiple-output (MIMO) receivers with large
antenna arrays operating in the millimeter wave carrier frequencies. This is
especially the case in large bandwidth communication systems, due to the sudden
drop in energy-efficiency of ADCs as the sampling rate is increased above
100MHz. Two mitigating energy-efficient approaches which have received
significant recent interest are i) to reduce the number of ADCs via analog and
hybrid beamforming architectures, and ii) to reduce the resolution of the ADCs
which in turn decreases power consumption. However, decreasing the number and
resolution of ADCs leads to performance loss -- in terms of achievable rates --
due to increased quantization error. In this work, we study the application of
practically implementable nonlinear analog operators such as envelope detectors
and polynomial operators, prior to sampling and quantization at the ADCs, as a
way to mitigate the aforementioned rate-loss. A receiver architecture
consisting of linear analog combiners, nonlinear analog operators, and few-bit
ADCs is designed. The fundamental information theoretic performance limits of
the resulting communication system, in terms of achievable rates, are
investigated under various assumptions on the set of implementable analog
operators. Extensive numerical evaluations and simulations of the communication
system are provided to compare the set of achievable rates under different
architecture designs and parameters. Circuit simulations and measurement
results, based on both 22 nm FDSOI CMOS technology and 65 nm Bulk CMOS
transistor technologies, are provided to justify the power efficiency of the
proposed receiver architecture deploying envelope detectors and polynomial
operators.
