  Placement is an essential task in modern chip design, aiming at placing
millions of circuit modules on a 2D chip canvas. Unlike the human-centric
solution, which requires months of intense effort by hardware engineers to
produce a layout to minimize delay and energy consumption, deep reinforcement
learning has become an emerging autonomous tool. However, the learning-centric
method is still in its early stage, impeded by a massive design space of size
ten to the order of a few thousand. This work presents MaskPlace to
automatically generate a valid chip layout design within a few hours, whose
performance can be superior or comparable to recent advanced approaches. It has
several appealing benefits that prior arts do not have. Firstly, MaskPlace
recasts placement as a problem of learning pixel-level visual representation to
comprehensively describe millions of modules on a chip, enabling placement in a
high-resolution canvas and a large action space. It outperforms recent methods
that represent a chip as a hypergraph. Secondly, it enables training the policy
network by an intuitive reward function with dense reward, rather than a
complicated reward function with sparse reward from previous methods. Thirdly,
extensive experiments on many public benchmarks show that MaskPlace outperforms
existing RL approaches in all key performance metrics, including wirelength,
congestion, and density. For example, it achieves 60%-90% wirelength reduction
and guarantees zero overlaps. We believe MaskPlace can improve AI-assisted chip
layout design. The deliverables are released at
https://laiyao1.github.io/maskplace.
