  The design and synthesis of masked cryptographic hardware implementations
that are secure against power side-channel attacks (PSCAs) in the presence of
glitches is a challenging task. High-Level Synthesis (HLS) is a promising
technique for generating masked hardware directly from masked software,
offering opportunities for design space exploration. However, conventional HLS
tools make modifications that alter the guarantee against PSCA security via
masking, resulting in an insecure RTL. Moreover, existing HLS tools can't place
registers at designated places and balance parallel paths in a cryptographic
design which is needed to stop glitch propagation. This paper introduces a
domain-specific HLS approach tailored to obtain a PSCA secure masked hardware
implementation directly from a masked software implementation. It places the
registers at specific locations required by the glitch-robust masking gadgets,
resulting in a secure RTL. Moreover, our tool automatically balances parallel
paths and facilitates a reduction in latency while preserving the PSCA security
guaranteed by masking. Experimental results with the PRESENT Cipher's S-box and
AES Canright's S-box masked with four state-of-the-art gadgets, show that
MaskedHLS produces RTLs with 73.9% decrease in registers and 45.7% decrease in
latency on an average} compared to manual register insertions. The PSCA
security of the MaskedHLS generated RTLs is also shown with TVLA test.
