  Recent expansions in multimedia devices gather enormous amounts of real-time
images for processing and inference. The images are first compressed using
compression schemes, like JPEG, to reduce storage costs and power for
transmitting the captured data. Due to inherent error resilience and
imperceptibility in images, JPEG can be approximated to reduce the required
computation power and area. This work demonstrates the first end-to-end
approximation computing-based optimization of JPEG hardware using i) an
approximate division realized using bit-shift operators to reduce the
complexity of the quantization block, ii) loop perforation, and iii) precision
scaling on top of a multiplier-less fast DCT architecture to achieve an
extremely energy-efficient JPEG compression unit which will be a perfect fit
for power/bandwidth-limited scenario. Furthermore, a gradient descent-based
heuristic composed of two conventional approximation strategies, i.e.,
Precision Scaling and Loop Perforation, is implemented for tuning the degree of
approximation to trade off energy consumption with the quality degradation of
the decoded image. The entire RTL design is coded in Verilog HDL, synthesized,
mapped to TSMC 65nm CMOS technology, and simulated using Cadence Spectre
Simulator under 25$^{\circ}$\textbf{C}, TT corner. The approximate division
approach achieved around $\textbf{28\%}$ reduction in the active design area.
The heuristic-based approximation technique combined with accelerator
optimization achieves a significant energy reduction of $\textbf{36\%}$ for a
minimal image quality degradation of $\textbf{2\%}$ SAD. Simulation results
also show that the proposed architecture consumes 15uW at the DCT and
quantization stages to compress a colored 480p image at 6fps.
