  There is a recent interest in neural network (NN)-based communication
algorithms which have shown to achieve (beyond) state-of-the-art performance
for a variety of problems or lead to reduced implementation complexity.
However, most work on this topic is simulation based and implementation on
specialized hardware for fast inference, such as field-programmable gate arrays
(FPGAs), is widely ignored. In particular for practical uses, NN weights should
be quantized and inference carried out by a fixed-point instead of
floating-point system, widely used in consumer class computers and graphics
processing units (GPUs). Moving to such representations enables higher
inference rates and complexity reductions, at the cost of precision loss. We
demonstrate that it is possible to implement NN-based algorithms in fixed-point
arithmetic with quantized weights at negligible performance loss and with
hardware complexity compatible with practical systems, such as FPGAs and
application-specific integrated circuits (ASICs).
