  A simulation methodology for ultra-scaled InAs quantum well field effect
transistors (QWFETs) is presented and used to provide design guidelines and a
path to improve device performance. A multiscale modeling approach is adopted,
where strain is computed in an atomistic valence-force-field method, an
atomistic sp3d5s* tight-binding model is used to compute channel effective
masses, and a 2-D real-space effective mass based ballistic quantum transport
model is employed to simulate three terminal current-voltage characteristics
including gate leakage. The simulation methodology is first benchmarked against
experimental I-V data obtained from devices with gate lengths ranging from 30
to 50 nm. A good quantitative match is obtained. The calibrated simulation
methodology is subsequently applied to optimize the design of a 20 nm gate
length device. Two critical parameters have been identified to control the gate
leakage magnitude of the QWFETs, (i) the geometry of the gate contact (curved
or square) and (ii) the gate metal work function. In addition to pushing the
threshold voltage towards an enhancement mode operation, a higher gate metal
work function can help suppress the gate leakage and allow for much aggressive
insulator scaling.
