  The Network-on-Chips is a promising candidate for addressing communication
bottlenecks in many-core processors and neural network processors. In this
work, we consider the generalized fault-tolerance topology generation problem,
where the link or switch failures can happen, for application-specific
network-on-chips (ASNoC). With a user-defined number, K, we propose an integer
linear programming (ILP) based method to generate ASNoC topologies, which can
tolerate at most K faults in switches or links. Given the communication
requirements between cores and their floorplan, we first propose a
convex-cost-flow based method to solve a core mapping problem for building
connections between the cores and switches. Second, an ILP based method is
proposed to allocate K+1 switch-disjoint routing paths for every communication
flow between the cores. Finally, to reduce switch sizes, we propose sharing the
switch ports for the connections between the cores and switches and formulate
the port sharing problem as a clique-partitioning problem Additionally, we
propose an ILP-based method to simultaneously solve the core mapping and
routing path allocation problems when considering physical link failures only.
Experimental results show that the power consumptions of fault-tolerance
topologies increase almost linearly with K because of the routing path
redundancy. When both switch faults and link faults are considered, port
sharing can reduce the average power consumption of fault-tolerance topologies
with K = 1, K = 2 and K = 3 by 18.08%, 28.88%, and 34.20%, respectively. When
considering only the physical link faults, the experimental results show that
compared to the FTTG algorithm, the proposed method reduces power consumption
and hop count by 10.58% and 6.25%, respectively; compared to the DBG based
method, the proposed method reduces power consumption and hop count by 21.72%
and 9.35%, respectively.
