  We propose a three-stage load balancing packet switch and its configuration
scheme. The input- and central-stage switches are bufferless crossbars, and the
output-stage switches are buffered crossbars. We call this switch ThRee-stage
Clos-network swItch with queues at the middle stage and DEtermiNisTic
scheduling (TRIDENT), and the switch is cell based. The proposed configuration
scheme uses predetermined and periodic interconnection patterns in the input
and central modules to load-balance and route traffic, therefore; it has low
configuration complexity. The operation of the switch includes a mechanism
applied at input and output modules to forward cells in sequence. TRIDENT
achieves 100% throughput under uniform and nonuniform admissible traffic with
independent and identical distributions (i.i.d.). The switch achieves this high
performance using a low-complexity architecture while performing in-sequence
forwarding and no central-stage expansion or memory speedup. Our discussion
includes throughput analysis, where we describe the operations the
configuration mechanism performs on the traffic traversing the switch, and
proof of in-sequence forwarding. We present a simulation analysis as a
practical demonstration of the switch performance under uniform and nonuniform
i.i.d. traffic.
