  Logic Obfuscation is a well renowned design-for-trust solution to protect an
Integrated Circuit (IC) from unauthorized use and illegal overproduction by
including key-gates to lock the design. This is particularly necessary for ICs
manufactured at untrusted third-party foundries getting exposed to security
threats. In the past, several logic obfuscation methodologies have been
proposed that are vulnerable to attacks such as the Boolean Satisfiability
Attack. Many of these techniques are implemented at the gate level that may
involve expensive re-synthesis cycles. In this paper, we present an
interconnect obfuscation scheme at the Register-Transfer Level (RTL) using
Switch Boxes (SBs) constructed of Polymorphic Transistors. A polymorphic SB can
be designed using the same transistor count as its
Complementary-Metal-Oxide-Semiconductor based counterpart, thereby no increased
area in comparison, but serving as an advantage in having more key-bit
combinations for an attacker to correctly identify and unlock each polymorphic
SB. Security-aware high-level synthesis algorithms have also been presented to
increase RTL interconnects to Functional Units impacting multiple outputs such
that when a polymorphic SB is strategically inserted, those outputs would be
corrupted upon incorrect key-bit identification. Finally, we run the SMT
(Satisfiability Modulo Theories)-based RTL Logic Attack on the obfuscated
design to examine its robustness.
