  In this paper, SiO2 layers deposited on 4H-SiC and subjected to different
post deposition annealing (PDA) in NO and N2O were studied to identify the key
factors influencing the channel mobility and threshold voltage stability in
4H-SiC MOSFETs. In particular, PDA in NO gave a higher channel mobility (55
cm2V-1s-1) than PDA in N2O (20 cm2V-1s-1), and the subthreshold behavior of the
devices confirmed a lower total amount of interface states for the NO case.
This latter could be also deduced from the behavior of the capacitance-voltage
characteristics of 4H-SiC MOSFETs measured in gate controlled diode
configuration. On the other hand, cyclic gate bias stress measurements allowed
to separate the contributions of interface states (Nit) both on the upper and
bottom parts of the 4H-SiC band gap and near interface oxide traps (NIOTs) in
the two oxides. In particular, it was found that NO annealing reduced the total
density of charges trapped at the interface states down to 3 x 1011 cm- 2 and
those trapped inside the oxide down to 1 x 1011 cm-2. Electron energy loss
spectroscopy demonstrated that the reduction of these traps in the NO annealed
sample is due to the lower amounts of sub-stoichiometric silicon oxide (~ 1nm)
and carbon-related defects (< 1nm) at the interface, respectively. This
correlation represents a further step in the comprehension of the physics of
the SiO2/4H-SiC interface explaining the mobility and threshold voltage
behavior of 4H-SiC MOSFETs.
