  A variety of computing platform like Field Programmable Gate Array (FPGA),
Graphics Processing Unit (GPU) and multicore Central Processing Unit (CPU) in
data centers are suitable for acceleration of data-intensive workloads.
Especially, FPGA platforms in data centers are gaining popularity for
high-performance computations due to their high speed, reconfigurable nature
and cost effectiveness. Such heterogeneous, highly parallel computational
architectures in data centers, combined with high-speed communication
technologies like 5G, are becoming increasingly suitable for real-time
applications. However, flexibility, cost-effectiveness, high computational
capabilities, and energy efficiency remain challenging issues in FPGA based
data centers. In this context an energy efficient scheduling solution is
required to maximize the resource profitability of FPGA. This paper introduces
a power-aware scheduling methodology aimed at accommodating periodic hardware
tasks within the available FPGAs of a data center at their potentially maximum
speed. This proposed methodology guarantees the execution of these tasks us ing
the maximum number of parallel computation units possible to implement in the
FPGAs, with minimum power consumption. The proposed scheduling methodology is
implemented in a data center with multiple Alveo-50 Xilinx-AMD FPGAs and Vitis
2023 tool. The evidence from the implementation shows the proposed scheduling
methodology is efficient compared to existing solutions.
