  Multi-core architectures feature an intricate hierarchy of cache memories,
with multiple levels and sizes. To adequately decompose an application
according to the traits of a particular memory hierarchy is a cumbersome task
that may be rewarded with significant performance gains. The current
state-of-the-art in memory-hierarchy-aware parallel computing delegates this
endeavour on the programmer, demanding from him deep knowledge of both parallel
programming and computer architecture. In this paper we propose the shifting of
these memory-hierarchy-related concerns to the run-time system, which then
takes on the responsibility of distributing the computation's data across the
target memory hierarchy. We evaluate our approach from a performance
perspective, comparing it against the common cache-neglectful data
decomposition strategy.
