  This paper presents the process optimization of a single-electron nanoflash
electron memory. Self-aligned single dot memory structures have been fabricated
using a wet anisotropic oxidation of a silicon nanowire. One of the main issue
was to clarify the process conditions for the dot formation. Based on the
process modeling, the influence of various parameters (oxidation temperature,
nanowire shape) has been investigated. The necessity of a sharp compromise
between these different parameters to ensure the presence of the memory dot has
been established. In order to propose an aggressive memory cell, the
downscaling of the device has been carefully studied. Scaling rules show that
the size of the original device could be reduced by a factor of 2. This point
has been previously confirmed by the realization of single-electron memory
devices.
