  This communication deals with a theoretical study of the hot spot onset (HSO)
in cellular bipolar power transistors. This well-known phenomenon consists of a
current crowding within few cells occurring for high power conditions, which
significantly decreases the forward safe operating area (FSOA) of the device.
The study was performed on a virtual sample by means of a fast, fully
analytical electro-thermal simulator operating in the steady state regime and
under the condition of imposed input base current. The purpose was to study the
dependence of the phenomenon on several thermal and geometrical factors and to
test suitable countermeasures able to impinge this phenomenon at higher biases
or to completely eliminate it. The power threshold of HSO and its localization
within the silicon die were observed as a function of the electrical bias
conditions as for instance the collector voltage, the equivalent thermal
resistance of the assembling structure underlying the silicon die, the value of
the ballasting resistances purposely added in the emitter metal
interconnections and the thickness of the copper heat spreader placed on the
die top just to the aim of making more uniform the temperature of the silicon
surface.
