  The true-differential superconductor on-chip amplifier has complementary
outputs that float with respect to chip ground. This improves signal integrity
and compatibility with the receiving semiconductor stage. Both
source-terminated and non-source-terminated designs producing 4mV demonstrated
rejection of a large common mode interference in the package. Measured margins
are $\pm$8.5% on the output bias, and $\pm$28% on AC clock amplitude. Waveforms
and eye diagrams are taken at 2.9-10Gb/s. Direct measurement of bit-error rates
are better than the resolution limit of 1e-12 at 2.9Gb/s, and better than 1e-9
at 10Gb/s.
