  The increasing transistor scale integration poses, among others, the
thermal-aware floorplanning problem; consisting of how to place the hardware
components in order to reduce overheating by dissipation. Due to the huge
amount of feasible floorplans, most of the solutions found in the literature
include an evolutionary algorithm for, either partially or completely, carrying
out the task of floorplanning. Evolutionary algorithms usually have a
bottleneck in the fitness evaluation. In the problem of thermal-aware
floorplanning, the layout evaluation by the thermal model takes 99.5\% of the
computational time for the best floorplanning algorithm proposed so far.The
contribution of this paper is to present a parallelization of this evaluation
phase in a master$-$worker model to achieve a dramatic speed-up of the
thermal-aware floorplanning process. Exhaustive experimentation was done over
three dimensional integrated circuits, with 48 and 128 cores, outperforming
previous published works.
