  Field-programmable gate arrays (FPGAs) provide an opportunity to co-design
applications with hardware accelerators, yet they remain difficult to program.
High-level synthesis (HLS) tools promise to raise the level of abstraction by
compiling C or C++ to accelerator designs. Repurposing legacy software
languages, however, requires complex heuristics to map imperative code onto
hardware structures. We find that the black-box heuristics in HLS can be
unpredictable: changing parameters in the program that should improve
performance can counterintuitively yield slower and larger designs. This paper
proposes a type system that restricts HLS to programs that can predictably
compile to hardware accelerators. The key idea is to model consumable hardware
resources with a time-sensitive affine type system that prevents simultaneous
uses of the same hardware structure. We implement the type system in Dahlia, a
language that compiles to HLS C++, and show that it can reduce the size of HLS
parameter spaces while accepting Pareto-optimal designs.
