  FPGAs have become a popular choice for deploying deep learning architectures
(DLA). There are many researchers that have explored the deployment and mapping
of DLA on FPGA. However, there has been a growing need to do design-time
hardware-software co-verification of these deployments. To the best of our
knowledge this is the first work that proposes a 2-Level 3-Way (2L-3W)
hardware-software co-verification methodology and provides a step-by-step guide
for the successful mapping, deployment and verification of DLA on FPGA boards.
The 2-Level verification is to make sure the implementation in each stage
(software and hardware) are following the desired behavior. The 3-Way
co-verification provides a cross-paradigm (software, design and hardware)
layer-by-layer parameter check to assure the correct implementation and mapping
of the DLA onto FPGA boards. The proposed 2L-3W co-verification methodology has
been evaluated over several test cases. In each case, the prediction and
layer-by-layer output of the DLA deployed on PYNQ FPGA board (hardware)
alongside with the intermediate design results of the layer-by-layer output of
the DLA implemented on Vivado HLS and the prediction and layer-by-layer output
of the software level (Caffe deep learning framework) are compared to obtain a
layer-by-layer similarity score. The comparison is achieved using a completely
automated Python script. The comparison provides a layer-by-layer similarity
score that informs us the degree of success of the DLA mapping to the FPGA or
help identify in design time the layer to be debugged in the case of
unsuccessful mapping. We demonstrated our technique on LeNet DLA and Caffe
inspired Cifar-10 DLA and the co-verification results yielded layer-by-layer
similarity scores of 99\% accuracy.
