  The allreduce operation is one of the most commonly used communication
routines in distributed applications. To improve its bandwidth and to reduce
network traffic, this operation can be accelerated by offloading it to network
switches, that aggregate the data received from the hosts, and send them back
the aggregated result. However, existing solutions provide limited
customization opportunities and might provide suboptimal performance when
dealing with custom operators and data types, with sparse data, or when
reproducibility of the aggregation is a concern. To deal with these problems,
in this work we design a flexible programmable switch by using as a building
block PsPIN, a RISC-V architecture implementing the sPIN programming model. We
then design, model, and analyze different algorithms for executing the
aggregation on this architecture, showing performance improvements compared to
state-of-the-art approaches.
