  As the process technologies scale into deep submicron region, crosstalk delay
is becoming increasingly severe, especially for global on-chip buses. To cope
with this problem, accurate delay models of coupled interconnects are needed.
In particular, delay models based on analytical approaches are desirable,
because they not only are largely transparent to technology, but also
explicitly establish the connections between delays of coupled interconnects
and transition patterns, thereby enabling crosstalk alleviating techniques such
as crosstalk avoidance codes (CACs). Unfortunately, existing analytical delay
models, such as the widely cited model in [1], have limited accuracy and do not
account for loading capacitance. In this paper, we propose analytical delay
models for coupled interconnects that address these disadvantages. By
accounting for more wires and eschewing the Elmore delay, our delay models
achieve better accuracy than the model in [1].
