  Compute-in-memory (CiM) is a promising approach to improving the computing
speed and energy efficiency in dataintensive applications. Beyond existing CiM
techniques of bitwise logic-in-memory operations and dot product operations,
this paper extends the CiM paradigm with FAST, a new shift-based inmemory
computation technique to handle high-concurrency operations on multiple rows in
an SRAM. Such high-concurrency operations are widely seen in both conventional
applications (e.g. the table update in a database), and emerging applications
(e.g. the parallel weight update in neural network accelerators), in which low
latency and low energy consumption are critical. The proposed shift-based CiM
architecture is enabled by integrating the shifter function into each SRAM
cell, and by creating a datapath that exploits the high-parallelism of shifting
operations in multiple rows in the array. A 128-row 16-column shiftable SRAM in
65nm CMOS is designed to evaluate the proposed architecture. Postlayout SPICE
simulations show average improvements of 4.4x energy efficiency and 96.0x speed
over a conventional fully-digital memory-computing-separated scheme, when
performing the 8-bit weight update task in a VGG-7 framework.
