  In this paper, the program control unit of an embedded RISC processor is
enhanced with a novel zero-overhead loop controller (ZOLC) supporting arbitrary
loop structures with multiple-entry/exit nodes. The ZOLC has been incorporated
to an open RISC processor core to evaluate the performance of the proposed unit
for alternative configurations of the selected processor. It is proven that
speed improvements of 8.4% to 48.2% are feasible for the used benchmarks.
