  Fifth-generation (5G) cellular systems will build on massive multi-user (MU)
multiple-input multiple-output (MIMO) technology to attain high spectral
efficiency. However, having hundreds of antennas and radio-frequency (RF)
chains at the base station (BS) entails prohibitively high hardware costs and
power consumption. This paper proposes a novel nonlinear precoding algorithm
for the massive MU-MIMO downlink in which each RF chain contains an 8-phase
(3-bit) constant-modulus transmitter, enabling the use of low-cost and
power-efficient analog hardware. We present a high-throughput VLSI architecture
and show implementation results on a Xilinx Virtex-7 FPGA. Compared to a
recently-reported nonlinear precoder for BS designs that use two 1-bit
digital-to-analog converters per RF chain, our design enables up to 3.75 dB
transmit power reduction at no more than a 2.7x increase in FPGA resources.
