  Deep neural network (DNN) accelerators employing crossbar arrays capable of
in-memory computing (IMC) are highly promising for neural computing platforms.
However, in deeply scaled technologies, interconnect resistance severely
impairs IMC robustness, leading to a drop in the system accuracy. To address
this problem, we propose SWANN - a technique based on shuffling weights in
crossbar arrays which alleviates the detrimental effect of wire resistance on
IMC. For 8T-SRAM-based 128x128 crossbar arrays in 7nm technology, SWANN
enhances the accuracy from 47.78% to 83.5% for ResNet-20/CIFAR-10. We also show
that SWANN can be used synergistically with Partial-Word-LineActivation,
further boosting the accuracy. Moreover, we evaluate the implications of SWANN
for compact ferroelectric-transistorbased crossbar arrays. SWANN incurs minimal
hardware overhead, with less than a 1% increase in energy consumption.
Additionally, the latency and area overheads of SWANN are ~1% and ~16%,
respectively when 1 ADC is utilized per crossbar array.
