  Recently, a parallel decoding framework of $G_N$-coset codes was proposed.
High throughput is achieved by decoding the independent component polar codes
in parallel. Various algorithms can be employed to decode these component
codes, enabling a flexible throughput-performance tradeoff. In this work, we
adopt SC as the component decoders to achieve the highest-throughput end of the
tradeoff. The benefits over soft-output component decoders are reduced
complexity and simpler (binary) interconnections among component decoders. To
reduce performance degradation, we integrate an error detector and a
log-likelihood ratio (LLR) generator into each component decoder. The LLR
generator, specifically the damping factors therein, is designed by a genetic
algorithm. This low-complexity design can achieve an area efficiency of
$533Gbps/mm^2$ under 7nm technology.
