  This work presents a producer-consumer link between two independent clock
domains. The link allows for metastability-free, low-latency, high-throughput
communication by slight adjustments to the clock frequencies of the producer
and consumer domains steered by a controller circuit. Any such controller
cannot deterministically avoid, detect, nor resolve metastability. Typically,
this is addressed by synchronizers, incurring a larger dead time in the control
loop. We follow the approach of Friedrichs et al. (TC 2018) who proposed
metastability-containing circuits. The result is a simple control circuit that
may become metastable, yet deterministically avoids buffer underrun or
overflow. More specifically, the controller output may become metastable, but
this may only affect oscillator speeds within specific bounds. In contrast,
communication is guaranteed to remain metastability-free. We formally prove
correctness of the producer-consumer link and a possible implementation that
has only small overhead. With SPICE simulations of the proposed implementation
we further substantiate our claims. The simulation uses 65nm process running at
roughly 2GHz.
