  Software defined radio is a widely accepted paradigm for design of
reconfigurable modems. The continuing march of Moore's law makes real-time
signal processing on general purpose processors feasible for a large set of
waveforms. Data rates in the low Mbps can be processed on low-power ARM
processors, and much higher data rates can be supported on large x86
processors. The advantages of all-software development (vs. FPGA/DSP/GPU) are
compelling: much wider pool of talent, lower development time and cost, and
easier maintenance and porting. However, very high-rate systems (above 100
Mbps) are still firmly in the domain of custom and semi-custom hardware (mostly
FPGAs). In this paper we describe an architecture and testbed for an SDR that
can be easily scaled to support over 3 GHz of bandwidth and data rate up to 10
Gbps. The paper covers a novel technique to parallelize typically serial
algorithms for phase and symbol tracking, followed by a discussion of data
distribution for a massively parallel architecture. We provide a brief
description of a mixed-signal front end and conclude with measurement results.
To the best of the author's knowledge, the system described in this paper is an
order of magnitude faster than any prior published result.
