  While standard cell layouts are drawn with minimum design rules to maximize
the benefit of design area shrinkage, the complicated design rules have caused
difficulties with signal routes accessing the pins in standard cell layouts. As
a result, it has become a great challenge for physical layout designers to
design a standard cell layout that is optimized for area, power, timing, signal
integrity, and printability. Multiple design iterations are required to
consider pin accessibility during standard cells layout to increase the number
of feasible solutions available to the router. In this work, we will
demonstrate several improvements with the Synopsys PAC methodology, such as
reducing the number of cells required for each Synopsys 'testcell' with the
same cell abutment condition, increasing the complexity of the pin connection
for better pin accessibility evaluation. We also recommend additional
constraints to improve the probability of detecting pin accessibility issues.
We also integrate other physical verification methods to access the design rule
compliance and the printability of standard cells. We hope that the easy to use
utility enables layout engineers to perform the verification, simplifying the
verification methodology.
