  This paper presents CERMET, an energy-efficient hardware architecture
designed for hardware-constrained cryptosystems. CERMET employs a base
cryptosystem in conjunction with network coding to provide both
information-theoretic and computational security while reducing energy
consumption per bit. This paper introduces the hardware architecture for the
system and explores various optimizations to enhance its performance. The
universality of the approach is demonstrated by designing the architecture to
accommodate both asymmetric and symmetric cryptosystems. The analysis reveals
that the benefits of this proposed approach are multifold, reducing energy per
bit and area without compromising security or throughput. The optimized
hardware architectures can achieve below 1 pJ/bit operations for AES-256.
Furthermore, for a public key cryptosystem based on Elliptic Curve Cryptography
(ECC), a remarkable 14.6X reduction in energy per bit and a 9.3X reduction in
area are observed, bringing it to less than 1 nJ/bit.
