  Interest in many-core architectures applied to real time selections is
growing in High Energy Physics (HEP) experiments. In this paper we describe
performance measurements of many-core devices when applied to a typical HEP
online task: the selection of events based on the trajectories of charged
particles. We use as benchmark a scaled-up version of the algorithm used at CDF
experiment at Tevatron for online track reconstruction - the SVT algorithm - as
a realistic test-case for low-latency trigger systems using new computing
architectures for LHC experiment. We examine the complexity/performance
trade-off in porting existing serial algorithms to many-core devices. We
measure performance of different architectures (Intel Xeon Phi and AMD GPUs, in
addition to NVidia GPUs) and different software environments (OpenCL, in
addition to NVidia CUDA). Measurements of both data processing and data
transfer latency are shown, considering different I/O strategies to/from the
many-core devices.
