  In recent years, CCD-in-CMOS TDI image sensors are becoming increasingly
popular for many small satellite missions to assure a fast and affordable
access to space for Low Earth Observation. Our monolithic CCD-in-CMOS TDI
imager features a specifically developed technology which combines the benefits
of a classical CCD TDI with the advantages of CMOS System-On-a-Chip (SoC)
design. Like CCD, this detector is also controlled by a large number of clock
voltages. Optimizing these voltages allows to increase the performance of the
detector by improving multiple characteristic parameters, such as full well
capacity (FWC), dark current, linearity, dark signal non-uniformity (DSNU) and
charge transfer efficiency (CTE). Traditionally, it has been the standard
practice to adjust the CCD voltages by trial and error methods to get a better
image. Because of the large parameter space, such subjective procedures may
yield far from the optimum performance. This paper reports a design of
experiments (DOE) technique applied on the clock voltages to improve the
multiple performance parameters of the detector. This method utilizes the
Taguchi's orthogonal arrays of experiments to reduce the number of experiments
with different voltage combinations. Finally, optimal combination of clock
voltages is obtained by converting the multiple performance parameters of the
detector into a single Grey relational grade. In this process, the sequences of
obtaining parameter values are categorized according to the performance
characteristics. The condition Higher-the-better is used for parameters like
FWC and CTE whereas condition Lower-the-better is applied for parameters, such
as dark current, linearity error and DSNU.
