  Lattice reduction (LR) is a preprocessing technique for multiple-input
multiple-output (MIMO) symbol detection to achieve better bit error-rate (BER)
performance. In this paper, we propose a customized homogeneous multiprocessor
for LR. The processor cores are based on transport triggered architecture
(TTA). We propose some modification of the popular LR algorithm,
Lenstra-Lenstra-Lovasz (LLL) for high throughput. The TTA cores are programmed
with high level language. Each TTA core consists of several special function
units to accelerate the program code. The multiprocessor takes 187 cycles to
reduce a single matrix for LR. The architecture is synthesized on 90 nm
technology and takes 405 kgates at 210 MHz.
