  This work compares and analyzes static approximate adders which are suitable
for FPGA and ASIC type implementations. We consider many static approximate
adders and evaluate their performance with respect to a digital image
processing application using standard figures of merit such as peak signal to
noise ratio and structural similarity index metric. We provide the error
metrics of approximate adders, and the design metrics of accurate and
approximate adders corresponding to FPGA and ASIC type implementations. For the
FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type
implementation, we considered a 32-28 nm CMOS standard digital cell library.
While the inferences from this work could serve as a useful reference to
determine an optimum static approximate adder for a practical application, in
particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be
preferable.
