  Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and
5V) are presented in this paper. Several PMOS and NMOS transistors with
different width to length ratios(W/L) were extensively characterized under
various bias conditions at temperatures ranging from 300K down to 4.2K. We
extracted their fundamental physical parameters and developed a compact model
based on BSIM3V3. In addition to their I-V characteristics, threshold
voltage(Vth) values, on/off current ratio, transconductance of the MOS
transistors, and resistors on chips are measured at temperatures from 300K down
to 4.2K. A simple subcircuit was built to correct the kink effect. This work
provides experimental evidence for implementation of cryogenic CMOS technology,
a valid industrial tape-out process model, and romotes the application of
integrated circuits in cryogenic environments, including quantum measurement
and control systems for quantum chips at very low temperatures.
