  As the demand for high-performance microprocessors increases, the circuit
complexity and the rate of data transfer increases resulting in higher power
consumption. We propose a clocking architecture that uses a series LC resonance
and inductor matching technique to address this bottleneck. By employing pulsed
resonance, the switching power dissipated is recycled back. The inductor
matching technique aids in reducing the skew, increasing the robustness of the
clock network. This new resonant architecture saves over 43% power and 91% skew
clocking a range of 1--5 GHz, compared to a conventional primary-secondary
flip-flop-based CMOS architecture.
