  The surface detector (SD) array of the Pierre Auger Observatory containing at
present 1680 water Cherenkov detectors spread over an area of 3000 km^2 started
to operate since 2004. The currently used Front-End Boards are equipped with
no-more produced ACEX and obsolete Cyclone FPGA (40 MSps/15-bit of dynamic
range).
  Huge progress in electronics and new challenges from physics impose a
significant upgrade of the SD electronics either to improve a quality of
measurements (much higher sampling and much wider dynamic range) or pick-up
from a background extremely rare events (new FPGA algorithms based on
sophisticated approaches like e.g. spectral triggers or neural networks). Much
higher SD sensitivity is necessary to confirm or reject hypotheses critical for
a modern astrophysics.
  The paper presents the Front-End Board (FEB) with the biggest Cyclone V E
FPGA 5CEFA9F31I7N, supporting 8 channels sampled with max. 250 MSps @ 14-bit
resolution. Considered sampling for the SD is 120 MSps, however, the FEB has
been developed with external anti-aliasing filters to keep a maximal
flexibility. Six channels are targeted to the SD, two the rest for other
experiments like: Auger Engineering Radio Array and additional muon counters.
  The FEB is an intermediate design pluged-in the actually used Unified Board
communicating with micro-controller at 40 MHz, however providing even 250 MSPs
sampling with 20-bit dynamic range, equipped in a virtual NIOS processor and
supporting 256 MB of SDRAM as well as with an implemented spectral trigger
based on the Discrete Cosine Transform for a detection of very inclined "old"
showers. The FEB can also support a neural network developing for a detection
of "young" showers, potentially generated by neutrinos.
