  This study simulated negative-capacitance double gate FinFETs with channel
lengths ranging from 25nm to 100nm using TCAD. The results show that negative
capacitance significantly reduces subthreshold swing as well as drain induced
barrier lowering effects. The improvement is found to be significantly more
prominent for short channel devices than long ones, which demonstrates the
tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A
compact analytical formulation is developed to quantify sub-threshold swing
improvement for short channel devices.
