  Micro-Raman spectroscopy was employed to study the near-surface stress
distributions and origins in Si around through silicon vias (TSVs) at both room
temperature and elevated temperatures for Cu-filled and CNT-filled TSV samples.
From the observations, we proved that the stresses near TSVs are mainly from
two sources: 1) pre-existing stress before via filling, and 2) coefficients of
thermal expansion (CTE) mismatch-induced stress. CTE-mismatch-induced stress is
shown to dominate the compressive regime of the near-surface stress
distribution around Cu-filled TSV structures, while pre-existing stress
dominates the full range of the stress distribution in the CNT-filled TSV
structures. Once the pre-existing stress is minimized, the total stress around
CNT-filled TSVs can be minimized accordingly. Therefore, compared to Cu-filled
TSVs, CNT-filled TSVs hold the potential to circumvent the hassle of
stress-aware circuit layout and to solve the stress-related reliability issues.
