  Neuromorphic vision processor is an electronic implementation of vision
algorithm processor on semiconductor. To image the world, a low-power CMOS
image sensor array is required in the vision processor. The image sensor array
is typically formed through photo diodes and analog to digital converter (ADC).
To achieve low power acquisition, a low-power mid-resolution ADC is necessary.
In this paper, a 1.8V, 8-bit, 166MS/s pipelined ADC was proposed in a 0.18 um
CMOS technology. The ADC used operational amplifier sharing architecture to
reduce power consumption and achieved maximum DNL of 0.24 LSB, maximum INL of
0.35 LSB, at a power consumption of 38.9mW. When input frequency is 10.4MHz, it
achieved an SNDR 45.9dB, SFDR 50dB, and an ENOB of 7.33 bit.
