  This article describes a custom VHDL firmware implementation of a
two-dimensional cluster-finder architecture for reconstructing hit positions in
the new vertex pixel detector (VELO) that is part of the LHCb Upgrade. This
firmware has been deployed to the existing FPGA cards that perform the readout
of the VELO, as a further enhancement of the DAQ system, and will run in real
time during physics data taking, reconstructing VELO hits coordinates
on-the-fly at the LHC collision rate. This pre-processing allows the first
level of the software trigger to accept a 11% higher rate of events, as the
ready-made hits coordinates accelerate the track reconstruction and consumes
significantly less electrical power. It additionally allows the raw pixel data
to be dropped at the readout level, thus saving approximately 14% of the DAQ
bandwidth. Detailed simulation studies have shown that the use of this
real-time cluster finding does not introduce any appreciable degradation in the
tracking performance in comparison to a full-fledged software implementation.
This work is part of a wider effort aimed at boosting the real-time processing
capability of HEP experiments by delegating intensive tasks to dedicated
computing accelerators deployed at the earliest stages of the data acquisition
chain.
