  We ported the firmware of the ARTIQ experiment control infrastructure to an
embedded system based on a commercial Xilinx Zynq-7000 system-on-chip. It
contains high-performance hardwired CPU cores integrated with FPGA fabric. As
with previous ARTIQ systems, the FPGA fabric is responsible for timing all I/O
signals to and from peripherals, thereby retaining the exquisite precision
required by most quantum physics experiments. A significant amount of latency
is incurred by the hardwired interface between the CPU core and FPGA fabric of
the Zynq-7000 chip; creative use of the CPU's cache-coherent accelerator ports
and the CPU's event flag allowed us to reduce this latency and achieve better
I/O performance than previous ARTIQ systems. The performance of the hardwired
CPU core, in particular when floating-point computation is involved, greatly
exceeds that of previous ARTIQ systems based on a softcore CPU. This makes it
interesting to execute intensive computations on the embedded system, with a
low-latency path to the experiment. We extended the ARTIQ compiler so that many
mathematical functions and matrix operations can be programmed by the user,
using the familiar NumPy syntax.
