  Overlays have shown significant promise for field-programmable gate-arrays
(FPGAs) as they allow for fast development cycles and remove many of the
challenges of the traditional FPGA hardware design flow. However, this often
comes with a significant performance burden resulting in very little adoption
of overlays for practical applications. In this paper, we tailor an overlay to
a specific application domain, and we show how we maintain its full
programmability without paying for the performance overhead traditionally
associated with overlays. Specifically, we introduce an overlay targeted for
deep neural network inference with only ~1% overhead to support the control and
reprogramming logic using a lightweight very-long instruction word (VLIW)
network. Additionally, we implement a sophisticated domain specific graph
compiler that compiles deep learning languages such as Caffe or Tensorflow to
easily target our overlay. We show how our graph compiler performs
architecture-driven software optimizations to significantly boost performance
of both convolutional and recurrent neural networks (CNNs/RNNs) - we
demonstrate a 3x improvement on ResNet-101 and a 12x improvement for long
short-term memory (LSTM) cells, compared to naive implementations. Finally, we
describe how we can tailor our hardware overlay, and use our graph compiler to
achieve ~900 fps on GoogLeNet on an Intel Arria 10 1150 - the fastest ever
reported on comparable FPGAs.
