  Reliability is a fundamental requirement in any microprocessor to guarantee
correct execution over its lifetime. The design rules related to reliability
depend on the process technology being used and the expected operating
conditions of the device. To meet reliability requirements, advanced process
technologies (28 nm and below) impose highly challenging design rules. Such
design-for-reliability rules have become a major burden on the flow of VLSI
implementation because of the severe physical constraints they impose.
  This paper focuses on electromigration (EM), which is one of the major
critical factors affecting semiconductor reliability. EM is the aging process
of on-die wires and vias and is induced by excessive current flow that can
damage wires and may also significantly impact the integrated-circuit clock
frequency. EM exerts a comprehensive global effect on devices because it
impacts wires that may reside inside the standard or custom logical cells,
between logical cells, inside memory elements, and within wires that
interconnect functional blocks.
  The design-implementation flow (synthesis and place-and-route) currently
detects violations of EM-reliability rules and attempts to solve them. In
contrast, this paper proposes a new approach to enhance these flows by using
EM-aware architecture. Our results show that the proposed solution can relax EM
design efforts in microprocessors and more than double microprocessor lifetime.
This work demonstrates this proposed approach for modern microprocessors,
although the principals and ideas can be adapted to other cases as well.
