  In this paper, we design a polar decoding platform for diverse application
scenarios that require low-cost and low-power communications. Specifically,
prevalent polar decoders such as successive cancellation (SC), SC-list (SCL)
and Fano decoders are all supported under the same architecture. Unlike
high-throughput or low-latency decoders that promote parallelism, this
architecture promotes serialization by repeatedly calling a ``sub-process''
that is executed by a core module. The resulting serial SCL-8 decoder is only 3
times as big as an SC decoder. Cost and power are minimized through resource
sharing and adaptive decoding techniques, etc. We carried out performance
simulation and hardware implementation to evaluate the actual chip area and
energy consumption.
