  LDPC code is a powerful error correcting code and has been applied to many
advanced communication systems. The prosperity of software radio has motivated
us to investigate the implementation of LDPC decoders on processors. In this
paper, we estimate and compare complexity and power consumption of LDPC
decoding algorithms running on general purpose processors. Using the estimation
results, we show two power control schemes for software radio: SNR-based
algorithm diversity and joint transmit power and receiver energy management.
Overall, this paper discusses general concerns about using processors as the
software radio platform for the implementation of LDPC decoders.
