  Processors using the open RISC-V ISA are finding increasing adoption in the
embedded world. Many embedded use cases have real-time constraints and require
flexible, predictable, and fast reactive handling of incoming events. However,
RISC- V processors are still lagging in this area compared to more mature
proprietary architectures, such as ARM Cortex-M and TriCore, which have been
tuned for years. The default interrupt controller standardized by RISC-V, the
Core Local Interruptor (CLINT), lacks configurability in prioritization and
preemption of interrupts. The RISC-V Core Local Interrupt Controller (CLIC)
specification addresses this concern by enabling pre-emptible, low-latency
vectored interrupts while also envisioning optional extensions to improve
interrupt latency. In this work, we implement a CLIC for the CV32E40P, an
industrially supported open-source 32-bit MCU-class RISC-V core, and enhance it
with fastirq: a custom extension that provides interrupt latency as low as 6
cycles. We call CV32RT our enhanced core. To the best of our knowledge, CV32RT
is the first fully open-source RV32 core with competitive interrupt-handling
features compared to the Arm Cortex-M series and TriCore. The proposed
extensions are also demonstrated to improve task context switching in real-time
operating systems.
