  Parallel and monolithic 3D integration directions offer pathways to realize
3D integrated circuits (ICs) but still lead to layer-by-layer implementations,
each functional layer being composed in 2D first. This mindset causes
challenging connectivity, routing and layer alignment between layers when
connected in 3D, with a routing access that can be even worse than 2D CMOS,
which fundamentally limits their potential. To fully exploit the opportunities
in the third dimension, we propose Skybridge-3D-CMOS (S3DC), a fine-grained 3D
integration approach that is directly composed in 3D, utilizing the vertical
dimension vs. using a layer-by-layer assembly mindset. S3DC uses a novel wafer
fabric creation with direct 3D design and connectivity in the vertical
dimension. It builds on a uniform vertical nanowire template that is processed
as a single wafer; it incorporates specifically architected structures for
realizing devices, circuits, and heat management directly in 3D. Novel 3D
interconnect concepts, including within the silicon layers, enable
significantly improved routing flexibility in all three dimensions and a
high-density 3D design paradigm overall. Intrinsic components for fabric-level
3D heat management are introduced. Extensive bottom-up simulations and
experiments have been presented to validate the key fabric-enabling concepts.
Evaluation results indicate up to 40x density and 10x performance-per-watt
benefits against conventional 16-nm CMOS for the circuits studied; benefits are
also at least an order of magnitude beyond what was shown to be possible with
other 3D directions.
