  We present the first rigorous security, performance, energy, and cost
analyses of the state-of-the-art on-DRAM-die read disturbance mitigation
method, Per Row Activation Counting (PRAC), described in JEDEC DDR5
specification's April 2024 update. Unlike prior state-of-the-art that advises
the memory controller to periodically issue refresh management (RFM) commands,
which provides the DRAM chip with time to perform refreshes, PRAC introduces a
new back-off signal. PRAC's back-off signal propagates from the DRAM chip to
the memory controller and forces the memory controller to 1) stop serving
requests and 2) issue RFM commands. As a result, RFM commands are issued when
needed as opposed to periodically, reducing RFM's overheads. We analyze PRAC in
four steps. First, we define an adversarial access pattern that represents the
worst-case for PRAC's security. Second, we investigate PRAC's configurations
and security implications. Our analyses show that PRAC can be configured for
secure operation as long as no bitflip occurs before accessing a memory
location 10 times. Third, we evaluate the performance impact of PRAC and
compare it against prior works using Ramulator 2.0. Our analysis shows that
while PRAC incurs less than 13% performance overhead for today's DRAM chips,
its performance overheads can reach up to 94% for future DRAM chips that are
more vulnerable to read disturbance bitflips. Fourth, we define an availability
adversarial access pattern that exacerbates PRAC's performance overhead to
perform a memory performance attack, demonstrating that such an adversarial
pattern can hog up to 94% of DRAM throughput and degrade system throughput by
up to 95%. We discuss PRAC's implications on future systems and foreshadow
future research directions. To aid future research, we open-source our
implementations and scripts at https://github.com/CMU-SAFARI/ramulator2.
