  In this work a rationalized algorithm for Dirac numbers multiplication is
presented. This algorithm has a low computational complexity feature and is
well suited to FPGA implementation. The computation of two Dirac numbers
product using the na\"ive method takes 256 real multiplications and 240 real
additions, while the proposed algorithm can compute the same result in only 88
real multiplications and 256 real additions. During synthesis of the discussed
algorithm we use the fact that Dirac numbers product may be represented as
vector-matrix product. The matrix participating in the product has unique
structural properties that allow performing its advantageous decomposition.
Namely this decomposition leads to significant reducing of the computational
complexity.
