  In three dimensional integrated circuits (3D-ICs), through silicon via (TSV)
is a critical technique in providing vertical connections. However, the yield
and reliability is one of the key obstacles to adopt the TSV based 3D-ICs
technology in industry. Various fault-tolerance structures using spare TSVs to
repair faulty functional TSVs have been proposed in literature for yield and
reliability enhancement, but a valid structure cannot always be found due to
the lack of effective generation methods for fault-tolerance structures. In
this paper, we focus on the problem of adaptive fault-tolerance structure
generation. Given the relations between functional TSVs and spare TSVs, we
first calculate the maximum number of tolerant faults in each TSV group. Then
we propose an integer linear programming (ILP) based model to construct
adaptive fault-tolerance struc- ture with minimal multiplexer delay overhead
and hardware cost. We further develop a speed-up technique through efficient
min-cost-max-flow (MCMF) model. All the proposed method- ologies are embedded
in a top-down TSV planning framework to form functional TSV groups and generate
adaptive fault- tolerance structures. Experimental results show that, compared
with state-of-the-art, the number of spare TSVs used for fault tolerance can be
effectively reduced.
