  Today's data centers consist of thousands of network-connected hosts, each
with CPUs and accelerators such as GPUs and FPGAs. These hosts also contain
network interface cards (NICs), operating at speeds of 100Gb/s or higher, that
are used to communicate with each other. We propose RecoNIC, an FPGA-based
RDMA-enabled SmartNIC platform that is designed for compute acceleration while
minimizing the overhead associated with data copies (in CPU-centric accelerator
systems) by bringing network data as close to computation as possible. Since
RDMA is the defacto transport-layer protocol for improved communication in data
center workloads, RecoNIC includes an RDMA offload engine for high throughput
and low latency data transfers. Developers have the flexibility to design their
accelerators using RTL, HLS or Vitis Networking P4 within the RecoNIC's
programmable compute blocks. These compute blocks can access host memory as
well as memory in remote peers through the RDMA offload engine. Furthermore,
the RDMA offload engine is shared by both the host and compute blocks, which
makes RecoNIC a very flexible platform. Lastly, we have open-sourced RecoNIC
for the research community to enable experimentation with RDMA-based
applications and use-cases.
