  Multipliers are widely-used arithmetic operators in digital signal processing
and machine learning circuits. Due to their relatively high complexity, they
can have high latency and be a significant source of power consumption. One
strategy to alleviate these limitations is to use approximate computing. This
paper thus introduces an original FPGA-based approximate multiplier
specifically optimized for machine learning computations. It utilizes
dynamically reconfigurable lookup table (LUT) primitives in AMD-Xilinx
technology to realize the core part of the computations. The paper provides an
in-depth analysis of the hardware architecture, implementation outcomes, and
accuracy evaluations of the multiplier proposed in INT8 precision.
Implementation results on an AMD-Xilinx Kintex Ultrascale+ FPGA demonstrate
remarkable savings of 64% and 67% in LUT utilization for signed multiplication
and multiply-and-accumulation configurations, respectively, when compared to
the standard Xilinx multiplier core. Accuracy measurements on four popular deep
learning (DL) benchmarks indicate a minimal average accuracy decrease of less
than 0.29% during post-training deployment, with the maximum reduction staying
less than 0.33%. The source code of this work is available on GitHub.
