  We present ESP4ML, an open-source system-level design flow to build and
program SoC architectures for embedded applications that require the hardware
acceleration of machine learning and signal processing algorithms. We realized
ESP4ML by combining two established open-source projects (ESP and HLS4ML) into
a new, fully-automated design flow. For the SoC integration of accelerators
generated by HLS4ML, we designed a set of new parameterized interface circuits
synthesizable with high-level synthesis. For accelerator configuration and
management, we developed an embedded software runtime system on top of Linux.
With this HW/SW layer, we addressed the challenge of dynamically shaping the
data traffic on a network-on-chip to activate and support the reconfigurable
pipelines of accelerators that are needed by the application workloads
currently running on the SoC. We demonstrate our vertically-integrated
contributions with the FPGA-based implementations of complete SoC instances
booting Linux and executing computer-vision applications that process images
taken from the Google Street View database.
