  This paper presents the new approach in implementation of analog-to-digital
converter (ADC) that is based on Hopfield neural-network architecture. Hopfield
neural ADC (NADC) is a type of recurrent neural network that is effective in
solving simple optimization problems, such as analog-to-digital conversion. The
main idea behind the proposed design is to use multiple 2-bit Hopfield NADCs
operating as quantizers in parallel, where analog input signal to each
successive 2-bit Hopfield ADC block is passed through a voltage level shifter.
This is followed by a neural network encoder to remove the quantization errors.
In traditional Hopfield NADC based designs, increasing the number of bits could
require proper scaling of the network parameters, in particular digital output
operating region. Furthermore, the resolution improvement of traditional
Hopfield NADC creates digital error that increases with the increasing number
of bits. The proposed design is scalable in number of bits and number of
quantization levels, and can maintain the magnitude of digital output code
within a manageable operating voltage range.
