  Today, most X-ray pixel detectors used at light sources transmit raw pixel
data off the detector ASIC. With the availability of more advanced ASIC
technology nodes for scientific application, more digital functionality from
the computing domains (e.g., compression) can be integrated directly into a
detector ASIC to increase data velocity. In this paper, we describe a
lightweight, user-configurable detector ASIC digital architecture with on-chip
compression which can be implemented in \SI{130}{\nm} technologies in a
reasonable area on the ASIC periphery. In addition, we present a design to
efficiently handle the variable data from the stream of parallel compressors.
The architecture includes user-selectable lossy and lossless compression
blocks. The impact of lossy compression algorithms is evaluated on simulated
and experimental X-ray ptychography datasets. This architecture is a practical
approach to increase pixel detector frame rates towards the continuous
\SI{1}{\MHz} regime for not only coherent imaging techniques such as
ptychography, but also for other diffraction techniques at X-ray light sources.
