  We study the impact of different interlayers and ferroelectric materials on
charge trapping during the endurance fatigue of Si FeFET with
TiN/HfxZr1-xO2/interlayer/Si (MFIS) gate stack. We have fabricated FeFET
devices with different interlayers (SiO2 or SiON) and HfxZr1-xO2 materials
(x=0.75, 0.6, 0.5), and directly extracted the charge trapping during endurance
fatigue. We find that: 1) The introduction of the N element in the interlayer
suppresses charge trapping and defect generation, and improves the endurance
characteristics. 2) As the spontaneous polarization (Ps) of the HfxZr1-xO2
decreases from 25.9 {\mu}C/cm2 (Hf0.5Zr0.5O2) to 20.3 {\mu}C/cm2
(Hf0.6Zr0.4O2), the charge trapping behavior decreases, resulting in the slow
degradation rate of memory window (MW) during program/erase cycling; in
addition, when the Ps further decreases to 8.1 {\mu}C/cm2 (Hf0.75Zr0.25O2), the
initial MW nearly disappears (only ~0.02 V). Thus, the reduction of Ps could
improve endurance characteristics. On the contract, it can also reduce the MW.
Our work helps design the MFIS gate stack to improve endurance characteristics.
