  In this paper, the field programmable gate array (FPGA) implementation of a
fetal heart rate (FHR) monitoring system is presented. The system comprises of
a preprocessing unit to remove various types of noise, followed by a fetal
electrocardiogram (FECG) extraction unit and an FHR detection unit. In order to
improve the precision and accuracy of the arithmetic operations, a floating
point unit is developed. A least mean squares algorithm based adaptive filter
(LMS-AF) is used for the purpose of FECG extraction. Two different
architectures, namely series and parallel, are proposed for the LMS-AF, with
the series architecture targeting lower utilization of hardware resources, and
the parallel architecture enabling less convergence time and lower power
consumption. The results show that it effectively detects the R peaks in the
extracted FECG with a sensitivity of 95.74% to 100% and a specificity of 100%.
The parallel architecture shows upto 85.88% reduction in the convergence time
for non-invasive FECG database while the series architecture shows 27.41%
reduction in the number of flip flops used when compared with the existing FPGA
implementations of various FECG extraction methods. It also shows an increase
of 2 to 7.51% in accuracy when compared to previous works.
