  The rise of hardware accelerators with custom instructions necessitates
custom compiler backends supporting these accelerators. This study provides
detailed analyses of LLVM and its RISC-V backend, supplemented with case
studies providing end-to-end overview of the mentioned transformations.
  We discuss that instruction design should consider both hardware and software
design space. The necessary compiler modifications may mean that the
instruction is not well designed and need to be reconsidered. We discuss that
RISC-V standard extensions provide exemplary instructions that can guide
instruction designers.
  In this study, the process of adding a custom instruction to compiler is
split into two parts as Assembler support and pattern matching support. Without
pattern matching support, conventional software requires manual entries of
inline Assembly for the accelerator which is not scalable. While it is trivial
to add Assembler support regardless of the instruction semantics, pattern
matching support is on the contrary. Pattern matching support and choosing the
right stage for the modification, requires the knowledge of the internal
transformations in the compiler. This study delves deep into pattern matching
and presents multiple ways to approach the problem of pattern matching support.
It is discussed that depending on the pattern's complexity, higher level
transformations, e.g. IR level, can be more maintainable compared to
Instruction Selection phase.
