  Partial Reconfiguration (PR) is a technique that allows reconfiguring the
FPGA chip at runtime. However, current design support tools require manual
floorplanning of the partial modules. Several approaches have been proposed in
this field, but only a few of them consider all aspects of PR, like the shape
and the aspect ratio of the reconfigurable region. Most of them are defined for
old FPGA architectures and have a high computational time. This paper
introduces an efficient automatic floorplanning algorithm, which takes into
account the heterogeneous architectures of modern FPGA families, as well as PR
constraints, introducing the aspect ratio constraint to optimize routing. The
algorithm generates possible placements of the partial modules, then applies a
recursive pseudo-bipartitioning heuristic search to find the best floorplan.
The experiments showed that the algorithm's performance is significantly better
than the one of other algorithms in this field.
