  Modern SoC-FPGA that consists of FPGA with embedded ARM cores is being
popularized as an embedded vision system platform. However, the design approach
of SoC-FPGA applications still follows traditional hardware-software separate
workflow, which becomes the barrier of rapid product design and iteration on
SoC-FPGA. High-Level Synthesis (HLS) and OpenCL-based system-level design
approaches provide programmers the possibility to design SoC-FGPA at
system-level with an unified development environment for both hardware and
software. To evaluate the feasibility of high-level design approach especially
for embedded vision applications, Vivado HLS and Altera SDK for OpenCL,
representative and most popular commercial tools in market, are selected as
evaluation design tools, disparity map calculation as targeting application. In
this paper, hardware accelerators of disparity map calculation are designed
with both tools and implemented on Zedboard and SoCKit development board,
respectively. Comparisons between design tools are made in aspects of
supporting directives, accelerator design process, and generated hardware
performance. The results show that both tools can generate efficient hardware
for disparity map calculation application with much less developing time.
Moreover, we can also state that, more directives (e.g., interface type, array
reshape, resource type specification) are supported, but more hardware
knowledge is required, in Vivado HLS. In contrast, Altera SDK for OpenCL is
relatively easier for software programmers who is new to hardware, but with the
price of more resources usage on FPGA for similar hardware accelerator
generation.
