  Ultra Deep-Sub-Micron CMOS chips have to function correctly and reliably, not
only during their early post-fabrication life, but also for their entire life
span. In this paper, we present an architectural-level in-field repair
technique. The key idea is to trade area for reliability by adding repair
features to the system while keeping the power and the performance overheads as
low as possible. In the case of permanent faults, spare blocks will replace the
faulty blocks on the fly. Meanwhile by shutting down the main logic blocks,
partial threshold voltage recovery can be achieved which will alleviate the
ageing-related delays and timing issues. The technique can avoid fatal
shut-downs in the system and will decrease the down-time, hence the
availability of such a system will be preserved. We have implemented the
proposed idea on a pipelined processor core using a conventional ASIC design
flow. The simulation results show that by tolerating about 70% area overhead
and less than 18% power overhead we can dramatically increase the reliability
and decrease the downtime of the processor.
