  Ensuring predictability in modern real-time Systems-on-Chip (SoCs) is an
increasingly critical concern for many application domains such as automotive,
robotics, and industrial automation. An effective approach involves the
modeling and development of hardware components, such as interconnects and
shared memory resources, to evaluate or enforce their deterministic behavior.
Unfortunately, these IPs are often closed-source, and these studies are limited
to the single modules that must later be integrated with third-party IPs in
more complex SoCs, hindering the precision and scope of modeling and
compromising the overall predictability. With the coming-of-age of open-source
instruction set architectures (RISC-V) and hardware, major opportunities for
changing this status quo are emerging. This study introduces an innovative
methodology for modeling and analyzing State-of-the-Art (SoA) open-source SoCs
for low-power cyber-physical systems. Our approach models and analyzes the
entire set of open-source IPs within these SoCs and then provides a
comprehensive analysis of the entire architecture. We validate this methodology
on a sample heterogenous low-power RISC-V architecture through RTL simulation
and FPGA implementation, minimizing pessimism in bounding the service time of
transactions crossing the architecture between 28% and 1%, which is
considerably lower when compared to similar SoA works.
