  Emerging research in edge devices and micro-controller units (MCU) enables
on-device computation of Deep Learning Training and Inferencing tasks. More
recently, contemporary trends focus on making the Deep Neural Net (DNN) Models
runnable on battery-less intermittent devices. One of the approaches is to
shrink the DNN models by enabling weight sharing, pruning, and conducted Neural
Architecture Search (NAS) with optimized search space to target specific edge
devices \cite{Cai2019OnceFA} \cite{Lin2020MCUNetTD} \cite{Lin2021MCUNetV2MP}
\cite{Lin2022OnDeviceTU}. Another approach analyzes the intermittent execution
and designs the corresponding system by performing NAS that is aware of
intermittent execution cycles and resource constraints \cite{iNAS}
\cite{HW-NAS} \cite{iLearn}.
  However, the optimized NAS was only considering consecutive execution with no
power loss, and intermittent execution designs only focused on balancing data
reuse and costs related to intermittent inference and often with low accuracy.
We proposed Accelerated Intermittent Deep Inference to harness the power of
optimized inferencing DNN models specifically targeting SRAM under 256KB and
make it schedulable and runnable within intermittent power. Our main
contribution is: (1) Schedule tasks performed by on-device inferencing into
intermittent execution cycles and optimize for latency; (2) Develop a system
that can satisfy the end-to-end latency while achieving a much higher accuracy
compared to baseline \cite{iNAS} \cite{HW-NAS}
