  FDTD codes, such as Sophie developed at CEA/DAM, no longer take advantage of
the processor's increased computing power, especially recently with the raising
multicore technology. This is rooted in the fact that low order numerical
schemes need an important memory bandwidth to bring and store the computed
fields. The aim of this article is to present a programming method at the
software's architecture level that improves the memory access pattern in order
to reuse data in cache instead of constantly accessing RAM memory. We will
exhibit a more than two computing time improvement in practical applications.
The target audience of this article is made of computing scientists and of
electrical engineers that develop simulation codes with no specific knowledge
in computer science or electronics.
