  We report the first experimental demonstration of recently proposed
energy-efficient single flux quantum logic, eSFQ. This logic can represent the
next generation of RSFQ logic eliminating dominant static power dissipation
associated with a dc bias current distribution and providing over two orders of
magnitude efficiency improvement over conventional RSFQ logic. We further
demonstrate that the introduction of passive phase shifters allows the
reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit
operation. Two types of demonstration eSFQ circuits, shift registers and
demultiplexers (deserializers), were implemented using the standard HYPRES 4.5
kA/cm2 fabrication process. In this paper, we present eSFQ circuit design and
demonstrate the viability and performance metrics of eSFQ circuits through
simulations and experimental testing.
