  While non-volatile memories (NVMs) provide several desirable characteristics
like better density and comparable energy efficiency than DRAM, DRAM-like
performance, and disk-like durability, the limited endurance NVMs manifest
remains a challenge with these memories. Indeed, the endurance constraints of
NVMs can prevent solutions that are commonly employed for other mainstream
memories like DRAM from being carried over as-is to NVMs. Specifically, in this
work we observe that, Oblivious RAM (ORAM) primitive, the state-ofart solution
to tackle memory bus side channel vulnerability, while widely studied for
DRAMs, is particularly challenging to implement as-is for NVMs as it severely
affects endurance of NVMs. This is so, as the inherent nature of ORAM primitive
causes an order of magnitude increase in write traffic and furthermore, causes
some regions of memory to be written far more often than others. This
non-uniform write traffic as manifested by ORAM primitive stands to severely
affect the lifetime of non-volatile memories (1% of baseline without ORAM) to
even make it impractical to address this security vulnerability
