  We present a study based on numerical simulations and comparative analysis of
recent experimental data concerning the operation and design of FeFETs. Our
results show that a proper consideration of charge trapping in the
ferroelectric-dielectric stack is indispensable to reconcile simulations with
experiments, and to attain the desired hysteretic behavior of the
current-voltage characteristics. Then we analyze a few design options for
polysilicon channel FeFETs and, in particular, we study the influence of the
channel thickness and doping concentration on the memory window, and on the
ratio between the polarization dependent, high and low resistance state.
