  Manycore SoC architectures based on on-chip shared memory are preferred for
flexible and programmable solutions in many application domains. However, the
development of many ported memory is becoming increasingly challenging as we
approach the end of Moore's Law while systems requirements demand larger shared
memory and more access ports. Memory can no longer be designed simply to
minimize single transaction access time, but must take into account the
functionality on the SoC. In this paper we examine a common large memory usage
in SoC, where the memory is used as storage for large buffers that are then
moved for time scheduled processing. We merge two aspects of many ported memory
design, combinatorial analysis of interconnect, and geometric analysis of
critical paths, extending both to show that in this case the SoC performance
benefits significantly from a hierarchical, distributed and staged architecture
with lower-radix switches and fractal randomization of memory bank addressing,
along with judicious and geometry aware application of speed up. The results
presented show the new architecture supports 20% higher throughput with 20%
lower latency and 30% less interconnection area at approximately the same power
consumption. We demonstrate the flexibility and scalability of this
architecture on silicon from a physical design perspective by taking the design
through layout. The architecture enables a much easier implementation flow that
works well with physically irregular port access and memory dominant layout,
which is a common issue in real designs.
