  The architecture of a new class of computers, optimized for lattice QCD
calculations, is described. An individual node is based on a single integrated
circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit
IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor
communications and additional control and diagnostic circuitry. The machine's
name, QCDOC, derives from ``QCD On a Chip''.
