  Increasing complexity of modern multi-processor system on chip (MPSoC) and
the decreasing feature size have introduced new challenges. System designers
have to consider now aspects which were not part of the design process in past
times. Resource-aware Computing is one of such emerging design concerns which
can help to improve performance, dependability and resource utilization of
overall system. Resource-aware execution takes into account the resource status
when executing tasks on MPSoCs. Exploration of resource-aware computing at
early design stages of complex systems is mandatory and appropriate
methodologies to do this in an efficient manner are thus required. In this
paper, we present a modular approach which provides modeling and simulation
support for investigation of resource-aware execution in MPSoCs. The proposed
methodology enables rapid exploration of the design space by modeling and
simulating the resource-awareness in a separate layer while widely reusing the
legacy system model in the other layer. Our experiments illustrate the benefits
of our approach for the exploration of resource-aware execution on MPSoCs.
