  Ternary neural networks (TNNs) offer a superior accuracy-energy trade-off
compared to binary neural networks. However, until now, they have required
specialized accelerators to realize their efficiency potential, which has
hindered widespread adoption. To address this, we present xTern, a lightweight
extension of the RISC-V instruction set architecture (ISA) targeted at
accelerating TNN inference on general-purpose cores. To complement the ISA
extension, we developed a set of optimized kernels leveraging xTern, achieving
67% higher throughput than their 2-bit equivalents. Power consumption is only
marginally increased by 5.2%, resulting in an energy efficiency improvement by
57.1%. We demonstrate that the proposed xTern extension, integrated into an
octa-core compute cluster, incurs a minimal silicon area overhead of 0.9% with
no impact on timing. In end-to-end benchmarks, we demonstrate that xTern
enables the deployment of TNNs achieving up to 1.6 percentage points higher
CIFAR-10 classification accuracy than 2-bit networks at equal inference
latency. Our results show that xTern enables RISC-V-based ultra-low-power edge
AI platforms to benefit from the efficiency potential of TNNs.
