  This paper introduces a novel optimization framework for deep neural network
(DNN) hardware accelerators, enabling the rapid development of customized and
automated design flows. More specifically, our approach aims to automate the
selection and configuration of low-level optimization techniques, encompassing
DNN and FPGA low-level optimizations. We introduce novel optimization and
transformation tasks for building design-flow architectures, which are highly
customizable and flexible, thereby enhancing the performance and efficiency of
DNN accelerators. Our results demonstrate considerable reductions of up to 92\%
in DSP usage and 89\% in LUT usage for two networks, while maintaining accuracy
and eliminating the need for human effort or domain expertise. In comparison to
state-of-the-art approaches, our design achieves higher accuracy and utilizes
three times fewer DSP resources, underscoring the advantages of our proposed
framework.
