  We investigate iterative low-resolution message-passing algorithms for
quasi-cyclic LDPC codes with horizontal and vertical layered schedules. Coarse
quantization and layered scheduling are highly relevant for hardware
implementations to reduce the bit width of messages and the number of decoding
iterations. As a novelty, this paper compares the two scheduling variants in
combination with mutual information maximizing compression operations in
variable and check nodes. We evaluate the complexity and error rate performance
for various configurations. Dedicated hardware architectures for regular
quasi-cyclic LDPC decoders are derived on a conceptual level. The
hardware-resource estimates confirm that most of the complexity lies within the
routing network operations. Our simulations reveal similar error rate
performance for both layered schedules but a slightly lower average iteration
count for the horizontal decoder.
