  In this paper a low power multiplier is proposed. The proposed multiplier
utilizes Broken-Array Multiplier approximation method on the conventional
modified Booth multiplier. This method reduces the total power consumption of
multiplier up to 58% at the cost of a small decrease in output accuracy. The
proposed multiplier is compared with other approximate multipliers in terms of
power consumption and accuracy. Furthermore, to have a better evaluation of the
proposed multiplier efficiency, it has been used in designing a 30-tap low-pass
FIR filter and the power consumption and accuracy are compared with that of a
filter with conventional booth multipliers. The simulation results show a 17.1%
power reduction at the cost of only 0.4dB decrease in the output SNR.
