  The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth
pixel layer inside the present Pixel Detector to recover from eventual failures
in the current pixel system, especially the b-layer. Additionally the IBL will
ensure excellent tracking, vertexing and b-tagging performance during the LHC
phase I and add robustness in tracking with high luminosity pile-up. The
expected peak luminosity for IBL is 2 to 3centerdot1034 cm-2s-1 and IBL is
designed for an integrated luminosity of 700 fb-1. This corresponds to an
expected fluence of 5centerdot1015 1 MeV neqcm-2 and a total ionizing dose of
250 MRad. In order to cope with these requirements, two new module concepts are
under investigation, both based on a new front end IC, called FE-I4. This IC
was designed as readout chip for future ATLAS Pixel Detectors and its first
application will be the IBL. The planar pixel sensor (PPS) based module concept
benefits from its well understood design, which is kept as similar as possible
to the design of the current ATLAS Pixel Detector sensor. The second approach
of the new three dimensional (3D) silicon sensor technology benefits from the
shorter charge carrier drift distance to the electrodes, which completely
penetrate the sensor bulk. Prototype modules of both sensor concepts have been
build and tested in laboratory and test beam environment before and after
irradiation. Both concepts show very high performance even after irradiation to
5centerdot1015 1 MeV neqcm-2 and meet the IBL specifications in terms of hit
efficiency being larger than 97%. Lowest operational threshold studies have
been effected and prove independent of the used sensor concept the excellent
performance of FE-I4 based module concepts in terms of noise hit occupancy at
low thresholds.
