  Compiler writers typically focus primarily on the performance of the
generated program binaries when selecting the passes and the order in which
they are applied in the standard optimization levels, such as GCC -O3. In some
domains, such as embedded systems and High-Performance Computing (HPC), it
might be sometimes acceptable to slowdown computations if the energy consumed
can be significantly decreased. Embedded systems often rely on a battery and
besides energy also have power dissipation limitations, while HPC centers have
a growing concern with electricity and cooling costs. Relying on power policies
to apply frequency/voltage scaling and/or change the CPU to idle states (e.g.,
alternate between power levels in bursts) as the main method to reduce energy
leaves potential for improvement using other orthogonal approaches. In this
work we evaluate the impact of compiler pass sequences specialization (also
known as compiler phase ordering) as a means to reduce the energy consumed by a
set of programs/functions when comparing with the use of the standard compiler
phase orders provided by, e.g., -OX flags. We use our phase selection and
ordering framework to explore the design space in the context of a Clang+LLVM
compiler targeting a multicore ARM processor in an ODROID board and a dual x86
desktop representative of a node in a Supercomputing center. Our experiments
with a set of representative kernels show that there we can reduce energy
consumption by up to 24% and that some of these improvements can only be
partially explained by improvements to execution time. The experiments show
cases where applications that run faster consume more energy. Additionally, we
make an effort to characterize the compiler sequence exploration space in terms
of their impact on performance and energy.
