  This paper investigates the impact of memory orientation on the bias pattern
of SRAM-based PUFs. We designed and fabricated a 65nm CMOS chip that contains
eleven SRAM macros that exercise different memory- and chip-level parameters.
At the memory level, several parameters passed to the SRAM compiler are
considered, including the number of addresses, the number of words, the aspect
ratio, and the chosen bitcell. Chip-level decisions are considered during the
floorplan, including the location and rotation of each SRAM macro in the
testchip. In this study, we conduct a comprehensive analysis of different
memory orientations and their effect on the biasing direction. Physical
measurements performed on 50 fabricated chips revealed that specific memory
orientations, namely R270 and MY90, exhibit a distinct negative biasing
direction compared to other orientations. Importantly, this biasing direction
remains consistent regardless of memory type, column mux ratio, memory size, or
the utilization of SRAMs with different bitcells. Overall, this study
highlights the significance of careful physical implementation and memory
orientation selection in designing SRAM-based PUFs. Our findings can guide
designers in the selection of SRAM memories with properties that make for
better PUFs that potentially require less error correction effort to compensate
for instability.
