  DRAM-based main memory and its associated components increasingly account for
a significant portion of application performance bottlenecks and power budget
demands inside the computing ecosystem. To alleviate the problems of storage
density and power constraints associated with DRAM, system architects are
investigating alternative non-volatile memory technologies such as Phase Change
Memory (PCM) to either replace or be used alongside DRAM memory. While such
alternative memory types offer many promises to overcome the DRAM-related
issues, they present a significant security threat to the users due to
persistence of memory data even after power down.
  In this paper, we investigate smart mechanisms to obscure the data left in
non-volatile memory after power down. In particular, we analyze the effect of
using a single encryption algorithm versus differentiated encryption based on
the security needs of the application phases. We also explore the effect of
encryption on a hybrid main memory that has a DRAM buffer cache plus PCM main
memory. Our mechanism takes into account the limited write endurance problem
associated with several non-volatile memory technologies including PCM, and
avoids any additional writes beyond those originally issued by the
applications. We evaluate using Gem5 simulator and SPEC 2006 applications, and
show the performance and power overheads of our proposed design.
