  Developing mixed-signal analog-digital neuromorphic circuits in advanced
scaled processes poses significant design challenges. We present compact and
energy efficient sub-threshold analog synapse and neuron circuits, optimized
for a 28 nm FD-SOI process, to implement massively parallel large-scale
neuromorphic computing systems. We describe the techniques used for maximizing
density with mixed-mode analog/digital synaptic weight configurations, and the
methods adopted for minimizing the effect of channel leakage current, in order
to implement efficient analog computation based on pA-nA small currents. We
present circuit simulation results, based on a new chip that has been recently
taped out, to demonstrate how the circuits can be useful for both low-frequency
operation in systems that need to interact with the environment in real-time,
and for high-frequency operation for fast data processing in different types of
spiking neural network architectures.
