  We present a hardware-based implementation of Linear Program (LP) decoding
for binary linear codes. LP decoding frames error-correction as an optimization
problem. In contrast, variants of Belief Propagation (BP) decoding frame
error-correction as a problem of graphical inference. LP decoding has several
advantages over BP-based methods, including convergence guarantees and better
error-rate performance in high-reliability channels. The latter makes LP
decoding attractive for optical transport and storage applications. However, LP
decoding, when implemented with general solvers, does not scale to large
blocklengths and is not suitable for a parallelized implementation in hardware.
It has been recently shown that the Alternating Direction Method of Multipliers
(ADMM) can be applied to decompose the LP decoding problem. The result is a
message-passing algorithm with a structure very similar to BP. We present new
intuition for this decoding algorithm as well as for its major computational
primitive: projection onto the parity polytope. Furthermore, we present results
for a fixed-point Verilog implementation of ADMM-LP decoding. This
implementation targets a Field-Programmable Gate Array (FPGA) platform to
evaluate error-rate performance and estimate resource usage. We show that Frame
Error Rate (FER) performance well within 0.5dB of double-precision
implementations is possible with 10-bit messages. Finally, we outline a number
of research opportunities that should be explored en-route to the realization
of an Application Specific Integrated Circuit (ASIC) implementation capable of
gigabit per second throughput.
