  The use of asynchronous design approaches to construct digital signal
processing (DSP) systems is a rapidly growing research area driven by a wide
range of emerging energy constrained applications such as wireless sensor
network, portable medical devices and brain implants. The asynchronous design
techniques allow the construction of systems which are samples driven, which
means they only dissipate dynamic energy when there processing data and idle
otherwise. This inherent advantage of asynchronous design over conventional
synchronous circuits allows them to be energy efficient. However the
implementation flow of asynchronous systems is still difficult due to its lack
of compatibility with industry-standard synchronous design tools and modelling
languages. This paper devises a novel asynchronous design for a finite impulse
response (FIR) filter, an essential building block of DSP systems, which is
synthesizable and suitable for implementation using conventional synchronous
systems design flow and tools. The proposed design is based on a modified
version of the micropipline architecture and it is constructed using four phase
bundled data protocol. A hardware prototype of the proposed filter has been
developed on an FPGA, and systematically verified. The results prove correct
functionality of the novel design and a superior performance compared to a
synchronous FIR implementation. The findings of this work will allow a wider
adoption of asynchronous circuits by DSP designers to harness their energy and
performance benefits.
