  Consider an arbitrary network of communicating modules on a chip, each
requiring a local signal telling it when to execute a computational step. There
are three common solutions to generating such a local clock signal: (i) by
deriving it from a single, central clock source, (ii) by local, free-running
oscillators, or (iii) by handshaking between neighboring modules. Conceptually,
each of these solutions is the result of a perceived dichotomy in which
(sub)systems are either clocked or fully asynchronous, suggesting that the
designer's choice is limited to deciding where to draw the line between
synchronous and asynchronous design. In contrast, we take the view that the
better question to ask is how synchronous the system can and should be. Based
on a distributed clock synchronization algorithm, we present a novel design
providing modules with local clocks whose frequency bounds are almost as good
as those of corresponding free-running oscillators, yet neighboring modules are
guaranteed to have a phase offset substantially smaller than one clock cycle.
Concretely, parameters obtained from a 15nm ASIC implementation running at 2GHz
yield mathematical worst-case bounds of 30ps on phase offset for a 32x32 node
grid network.
