  Silicon quantum devices are maturing from academic single- and two-qubit
devices to industrially-fabricated dense quantum-dot (QD) arrays, increasing
operational complexity and the need for better pulsed-gate and readout
techniques. We perform gate-voltage pulsing and gate-based reflectometry
measurements on a dense 2$\times$2 array of silicon quantum dots fabricated in
a 300-mm-wafer foundry. Utilizing the strong capacitive couplings within the
array, it is sufficient to monitor only one gate electrode via high-frequency
reflectometry to establish single-electron occupation in each of the four dots
and to detect single-electron movements with high bandwidth. A global top-gate
electrode adjusts the overall tunneling times, while linear combinations of
side-gate voltages yield detailed charge stability diagrams. To test for spin
physics and Pauli spin blockade at finite magnetic fields, we implement
symmetric gate-voltage pulses that directly reveal bidirectional interdot
charge relaxation as a function of the detuning between two dots. Charge
sensing within the array can be established without the involvement of adjacent
electron reservoirs, important for scaling such split-gate devices towards
longer 2$\times$N arrays. Our techniques may find use in the scaling of few-dot
spin-qubit devices to large-scale quantum processors.
