  Switched capacitor arrays (SCA) ASICs are becoming more and more popular for
the readout of detector signals, since the sampling frequency of typically
several gigasamples per second allows excellent pile-up rejection and time
measurements. They suffer however from the fact that their sampling bins are
not equidistant in time, given by limitations of the chip process. In the past,
this limited time measurements of optimal signals to standard deviations
({\sigma}) of about 4-25 ps in accuracy for the split pulse test, depending on
the specific chip. This paper introduces a novel time calibration, which
determines the true sampling speed of an SCA. Additionally, for two
independently running SCA chips, the achieved time resolution improved to less
than 3 ps ({\sigma}) independently from the delay for the split pulse test,
when simply applying a linear interpolation. When using a more advanced
analyzing technique for the split pulse test with a single SCA, this limit is
pushed below 1 ps ({\sigma}) for delays up to 8 ns. Various test measurements
with different boards based on the DRS4 ASIC indicate that the new calibration
is stable over time but not over larger temperature variations.
