  Current-induced domain wall motion (CIDWM) is regarded as a promising way
towards achieving emerging high-density, high-speed and low-power non-volatile
devices. Racetrack memory is an attractive spintronic memory based on this
phenomenon, which can store and transfer a series of data along a magnetic
nanowire. However, storage capacity issue is always one of the most serious
bottlenecks hindering its application for practical systems. This paper focuses
on the potential of racetrack memory towards large capacity. The investigations
covering from device level to system level have been carried out. Various
alternative mechanisms to improve the capacity of racetrack memory have been
proposed and elucidated, e.g. magnetic field assistance, chiral DW motion and
voltage-controlled flexible DW pinning. All of them can increase nanowire
length, allowing enhanced feasibility of large-capacity racetrack memory. By
using SPICE compatible racetrack memory electrical model and commercial CMOS 28
nm design kit, mixed simulations are performed to validate their
functionalities and analyze their performance. System level evaluations
demonstrate the impact of capacity improvement on overall system. Compared with
traditional SRAM based cache, racetrack memory based cache shows its advantages
in terms of execution time and energy consumption.
