  This paper describes a novel design of a threshold logic gate (a binary
perceptron) and its implementation as a standard cell. This new cell structure,
referred to as flash threshold logic (FTL), uses floating gate (flash)
transistors to realize the weights associated with a threshold function. The
threshold voltages of the flash transistors serve as a proxy for the weights.
An FTL cell can be equivalently viewed as a multi-input, edge-triggered
flipflop which computes a threshold function on a clock edge. Consequently, it
can be used in the automatic synthesis of ASICs. The use of flash transistors
in the FTL cell allows programming of the weights after fabrication, thereby
preventing discovery of its function by a foundry or by reverse engineering.
This paper focuses on the design and characteristics of the FTL cell. We
present a novel method for programming the weights of an FTL cell for a
specified threshold function using a modified perceptron learning algorithm.
The algorithm is further extended to select weights to maximize the robustness
of the design in the presence of process variations. The FTL circuit was
designed in 40nm technology and simulations with layout-extracted parasitics
included, demonstrate significant improvements in the area (79.7%), power
(61.1%), and performance (42.5%) when compared to the equivalent
implementations of the same function in conventional static CMOS design. Weight
selection targeting robustness is demonstrated using Monte Carlo simulations.
The paper also shows how FTL cells can be used for fixing timing errors after
fabrication.
