  The Digital Annealer is a CMOS hardware designed by Fujitsu Laboratories for
high-speed solving of Quadratic Unconstrained Binary Optimization (QUBO)
problems that could be difficult to solve by means of existing general-purpose
computers. In this paper, we present a mathematical description of the
first-generation Digital Annealer's Algorithm from the Markov chain theory
perspective, establish a relationship between its stationary distribution with
the Gibbs-Boltzmann distribution, and provide a necessary and sufficient
condition on its cooling schedule that ensures asymptotic convergence to the
ground states.
