  This paper addresses the question: Can spintronic circuits based on Magnetic
Tunnel Junction (MTJ) transducers outperform their state-of-the-art CMOS
counterparts? To this end, we use the EPFL combinational benchmark sets,
synthesize them in 7 nm CMOS and in MTJ-based spintronic technologies, and
compare the two implementation methods in terms of Energy-Delay-Product (EDP).
To fully utilize the technologies potential, CMOS and spintronic
implementations are built upon standard Boolean and Majority Gates,
respectively. For the spintronic circuits, we assumed that domain conversion
(electric/magnetic to magnetic/electric) is performed by means of MTJs and the
computation is accomplished by domain wall based majority gates, and considered
two EDP estimation scenarios: (i) Uniform Benchmarking, which ignores the
circuit's internal structure and only includes domain transducers power and
delay contributions into the calculations, and (ii) Majority-Inverter-Graph
Benchmarking, which also embeds the circuit structure, the associated critical
path delay and energy consumption by DW propagation. Our results indicate that
for the uniform case, the spintronic route is better suited for the
implementation of complex circuits with few inputs and outputs. On the other
hand, when the circuit structure is also considered via majority and inverter
synthesis, our analysis clearly indicates that in order to match and eventually
outperform CMOS performance, MTJ efficiency has to be improved by 3-4 orders of
magnitude. While it is clear that for the time being the MTJ-based-spintronic
way cannot compete with CMOS, further transducer developments may tip the
balance, which, when combined with information non-volatility, may make
spintronic implementation for certain applications that require a large number
of calculations and have a rather limited amount of interaction with the
environment.
