  Wireless baseband processing (WBP) is a key element of wireless
communications, with a series of signal processing modules to improve data
throughput and counter channel fading. Conventional hardware solutions, such as
digital signal processors (DSPs) and more recently, graphic processing units
(GPUs), provide various degrees of parallelism, yet they both fail to take into
account the cyclical and consecutive character of WBP. Furthermore, the large
amount of data in WBPs cannot be processed quickly in symmetric multiprocessors
(SMPs) due to the unpredictability of memory latency. To address this issue, we
propose a hierarchical dataflow-driven architecture to accelerate WBP. A
pack-and-ship approach is presented under a non-uniform memory access (NUMA)
architecture to allow the subordinate tiles to operate in a bundled access and
execute manner. We also propose a multi-level dataflow model and the related
scheduling scheme to manage and allocate the heterogeneous hardware resources.
Experiment results demonstrate that our prototype achieves $2\times$ and
$2.3\times$ speedup in terms of normalized throughput and single-tile clock
cycles compared with GPU and DSP counterparts in several critical WBP
benchmarks. Additionally, a link-level throughput of $288$ Mbps can be achieved
with a $45$-core configuration.
