  The increasing growth of applications' memory capacity and performance
demands has led the CPU vendors to deploy heterogeneous memory systems either
within a single system or via disaggregation. For instance, systems like
Intel's Knights Landing and Sapphire Rapids can be configured to use high
bandwidth memory as a cache to main memory. While there is significant research
investigating the designs of DRAM caches, there has been little research
investigating DRAM caches from a full system point of view, because there is
not a suitable model available to the community to accurately study largescale
systems with DRAM caches at a cycle-level. In this work we describe a new
cycle-level DRAM cache model in the gem5 simulator which can be used for
heterogeneous and disaggregated systems. We believe this model enables the
community to perform a design space exploration for future generation of memory
systems supporting DRAM caches.
