  We investigate a wafer scale tunnel junction fabrication method, where a
plasma etched via through a dielectric layer covering bottom Al electrode
defines the tunnel junction area. The ex-situ tunnel barrier is formed by
oxidation of the bottom electrode in the junction area. Room temperature
resistance mapping over a 150 mm wafer give local deviation values of the
tunnel junction resistance that fall below 7.5 % with an average of 1.3 %. The
deviation is further investigated by sub-1 K measurements of a device, which
has one tunnel junction connected to four arrays consisting of N junctions (N =
41, junction diameter 700 nm). The differential conductance is measured in
single-junction and array Coulomb blockade thermometer operation modes. By
fitting the experimental data to the theoretical models we found an upper limit
for the local tunnel junction resistance deviation of ~5 % for the array of
2N+1 junctions. This value is of the same order as the minimum detectable
deviation defined by the accuracy of our experimental setup.
