  As an emerging post-CMOS Field Effect Transistor, Magneto-Electric FETs
(MEFETs) offer compelling design characteristics for logic and memory
applications, such as high-speed switching, low power consumption, and
non-volatility. In this paper, for the first time, a non-volatile MEFET-based
SRAM design named ME-SRAM is proposed for edge applications which can
remarkably save the SRAM static power consumption in the idle state through a
fast backup-restore process. To enable normally-off in-situ computing, the
ME-SRAM cell is integrated into a novel processing-in-SRAM architecture that
exploits a hardware-optimized bit-line computing approach for the execution of
Boolean logic operations between operands housed in a memory sub-array within a
single clock cycle. Our device-to-architecture evaluation results on Binary
convolutional neural network acceleration show the robust performance of ME-
SRAM while reducing energy consumption on average by a factor of 5.3 times
compared to the best in-SRAM designs.
