  We have entered the Noisy Intermediate-Scale Quantum Era. A plethora of
quantum processor prototypes allow evaluation of potential of the Quantum
Computing paradigm in applications to pressing computational problems of the
future. Growing data input rates and detector resolution foreseen in
High-Energy LHC (2030s) experiments expose the often high time and/or space
complexity of classical algorithms. Quantum algorithms can potentially become
the lower-complexity alternatives in such cases. In this work we discuss the
potential of Quantum Associative Memory (QuAM) in the context of LHC data
triggering. We examine the practical limits of storage capacity, as well as
store and recall errorless efficiency, from the viewpoints of the
state-of-the-art IBM quantum processors and LHC real-time charged track pattern
recognition requirements. We present a software prototype implementation of the
QuAM protocols and analyze the topological limitations for porting the simplest
QuAM instances to the public IBM 5Q and 14Q cloud-based superconducting chips.
