  Digital single-flux quantum (SFQ) technology promises to meet the demands of
ultra low power and high speed computing needed for future exascale
supercomputing platforms. However, clocking SFQ logic circuits remains a
challenge due to the presence of a large number of on-chip clock sinks, and
hence, decomposing large designs into multiple independent clock domains
similar to CMOS, have been proposed. However, such clock domains demand
efficient synchronizing First-in-first-out (FIFO) buffers and robust interfaces
to safely transfer data from one clock domain to another. In this brief, we
propose such a FIFO synchronizer and clock-domain crossing interface for both
uni and bi-directional data transfer without any significant degradation of the
clock frequency. Our proposal scales to complex gate-level pipelined SFQ logic
cores while demonstrating extremely low Bit Error Rate (BER) and is unaffected
by noise, given current SFQ lithography feature sizes.
