  Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum
device interface fabrication. Several previous works have studied the
characterization of CMOS technology at cryogenic temperatures for various
process nodes. However, CMOS characteristics for various width/length (W/L)
ratios and under different bias conditions still require further research. In
addition, no previous works have produced an integrated modeling process for
cryo-CMOS technology. In this paper, the results of characterization of
Semiconductor Manufacturing International Corporation (SMIC) 0.18 {\mu}m CMOS
technology at cryogenic temperatures (varying from 300 K to 4.2 K) are
presented. Measurements of thin- and thick-oxide NMOS and PMOS devices with
different W/L ratios are taken under four distinct bias conditions and at
different temperatures. The temperature-dependent parameters are revised and an
advanced CMOS model is proposed based on BSIM3v3 at the liquid nitrogen
temperature (LNT). The proposed model ensures precision at the LNT and is valid
for use in an industrial tape-out process. The proposed method presents a
calibration approach for BSIM3v3 that is available at different temperature
intervals.
