  This paper introduces reconfigurable computing (RC) and specifically chooses
one of the prototypes in this field, MorphoSys (M1) [1 - 5]. The paper
addresses the results obtained when using RC in mapping algorithms pertaining
to digital coding in relation to previous research [6 - 10]. The chosen
algorithms relate to cyclic coding techniques, namely the CCITT CRC-16 and the
CRC-16. A performance analysis study of the M1 RC system is also presented to
evaluate the efficiency of the algorithm execution on the M1 system. For
comparison purposes, three other systems where used to map the same algorithms
showing the advantages and disadvantages of each compared with the M1 system.
The algorithms were run on the 8x8 RC (reconfigurable) array of the M1
(MorphoSys) system; numerical examples were simulated to validate our results,
using the MorphoSys mULATE program, which simulates MorphoSys operations.
