  It is now widely accepted that the CMOS technology implementing irreversible
logic will hit a scaling limit beyond 2016, and that the increased power
dissipation is a major limiting factor. Reversible computing can potentially
require arbitrarily small amounts of energy. Recently several nano-scale
devices which have the potential to scale, and which naturally perform
reversible logic, have emerged. This paper addresses several fundamental issues
that need to be addressed before any nano-scale reversible computing systems
can be realized, including reliability and performance trade-offs and
architecture optimization. Many nano-scale devices will be limited to only near
neighbor interactions, requiring careful optimization of circuits. We provide
efficient fault-tolerant (FT) circuits when restricted to both 2D and 1D.
Finally, we compute bounds on the entropy (and hence, heat) generated by our FT
circuits and provide quantitative estimates on how large can we make our
circuits before we lose any advantage over irreversible computing.
