  Being the most widely used language across the world due to its simplicity
and with 35 keywords (v3.7), Python attracts both hardware and software
engineers. Python-based verification environment leverages open-source
libraries such as cocotb and cocotb-coverage that enables interfacing the
tesbenches with any available simulator and facilitating constrained
randomization, coverage respectively. These libraries significantly ease the
development of testbenches and have the potential to reduce the setup cost. The
goal of this paper is to assess the effectiveness of a Python-Cocotb
verification setup with design IPs and compare its features and performance
metrics with the current de-facto hardware verification language i.e.,
SystemVerilog.
