  The recent surge in hardware security is significant due to offshoring the
proprietary Intellectual property (IP). One distinct dimension of the
disruptive threat is malicious logic insertion, also known as Hardware Trojan
(HT). HT subverts the normal operations of a device stealthily. The diversity
in HTs activation mechanisms and their location in design brings no catch-all
detection techniques. In this paper, we propose to leverage principle features
of social network analysis to security analysis of Register Transfer Level
(RTL) designs against HT. The approach is based on investigating design
properties, and it extends the current detection techniques. In particular, we
perform both node- and graph-level analysis to determine the direct and
indirect interactions between nets in a design. This technique helps not only
in finding vulnerable nets that can act as HT triggering signals but also their
interactions to influence a particular net to act as HT payload signal. We
experiment the technique on 420 combinational HT instances, and on average, we
can detect both triggering and payload signals with accuracy up to 97.37%.
