  The performance and capacity of solid-state drives (SSDs) are continuously
improving to meet the increasing demands of modern data-intensive applications.
Unfortunately, communication between the SSD controller and memory chips (e.g.,
2D/3D NAND flash chips) is a critical performance bottleneck for many
applications. SSDs use a multi-channel shared bus architecture where multiple
memory chips connected to the same channel communicate to the SSD controller
with only one path. As a result, path conflicts often occur during the
servicing of multiple I/O requests, which significantly limits SSD parallelism.
It is critical to handle path conflicts well to improve SSD parallelism and
performance. Our goal is to fundamentally tackle the path conflict problem by
increasing the number of paths between the SSD controller and memory chips at
low cost. To this end, we build on the idea of using an interconnection network
to increase the path diversity between the SSD controller and memory chips. We
propose Venice, a new mechanism that introduces a low-cost interconnection
network between the SSD controller and memory chips and utilizes the path
diversity to intelligently resolve path conflicts. Venice employs three key
techniques: 1) a simple router chip added next to each memory chip without
modifying the memory chip design, 2) a path reservation technique that reserves
a path from the SSD controller to the target memory chip before initiating a
transfer, and 3) a fully-adaptive routing algorithm that effectively utilizes
the path diversity to resolve path conflicts. Our experimental results show
that Venice 1) improves performance by an average of 2.65x/1.67x over a
baseline performance-optimized/cost-optimized SSD design across a wide range of
workloads, 2) reduces energy consumption by an average of 61% compared to a
baseline performance-optimized SSD design.
