  In this paper, we describe a high-level synthesis (HLS) tool that
automatically allows area/throughput trade-offs for implementing streaming task
graphs (STG). Our tool targets a massively parallel processor array (MPPA)
architecture, very similar to the Ambric MPPA chip architecture, which is to be
implemented as an FPGA overlay. Similar to Ambric tools, our HLS tool accepts a
STG as input written in a subset of Java and a structural language in the style
of a Kahn Processing Network (KPN). Unlike the Ambric tools, our HLS tool
analyzes the parallelism internal to each Java "node" and evaluates the
throughput and area of several possible implementations. It then analyzes the
full graph for bottlenecks or excess compute capacity, selects an
implementation for each node, and even considers replicating or splitting nodes
while either minimizing area (for a fixed throughput target), or maximizing
throughput (for a fixed area target). In addition to traditional node selection
and replication methods used in prior work, we have uniquely implemented node
combining and splitting to find a better area/throughput trade-off. We present
two optimization approaches, a formal ILP formulation and a heuristic solution.
Results show that the heuristic is more flexible and can find design points not
available to the ILP, thereby achieving superior results.
