  In this paper, we have implemented and designed a sorting network for
reversible logic circuits synthesis in terms of n*n Toffoli gates. The
algorithm presented in this paper constructs a Toffoli Network based on
swapping bit strings. Reduction rules are then applied by simple template
matching and removing useless gates from the network. Random selection of bit
strings and reduction of control inputs are used to minimize both the number of
gates and gate width. The method produces near optimal results for up to
3-input 3-output circuits.
