  Ensuring high performance, while meeting the power budget is a challenging
task as the world is moving towards next-generation computing. Researchers and
designers are in search of new solutions for efficient computation. Spintronics
devices have been viewed as a promising way to deal with the escalating
difficulties of CMOS downscaling, explicitly, the Magnetic Tunnel Junction
(MTJ) devices have been the focal point of investigation. They possess some
essential features from the aforementioned perspective such as nonvolatility,
low power, and scalability. In light of the significance of MTJ devices in
next-generation computing, this paper presents a physics-based STT/SHE MTJ
model for hybrid MTJ/CMOS circuit simulation, that accurately emulates the
device physics and stochastic thermal noise behavior of the MTJ. It is vital to
have an MTJ compact model which is compatible with the open-source NGSPICE
simulation framework since previously developed models are reliant on
commercial EDA tools. In addition, for developing hybrid circuits with random
process fluctuations, a simulator-independent Monte-Carlo simulation capability
has been incorporated Finally, the STT/SHE-MTJ model is demonstrated using PCSA
read/write operation and the implementation of neuron MTJ.
