  The current work explores a geometrically engineered dual gate GaAs nanowire
FET with state of the art miniaturized dimensions for high performance charge
qubit operation at room temperature. Relevant gate voltages in such device can
create two voltage tunable quantum dots (VTQDs) underneath the gates, as well
as can manipulate their eigenstate detuning and the inter-dot coupling to
generate superposition, whereas a small drain bias may cause its collapse
leading to qubit read out. Such qubit operations, i.e., Initialization,
Manipulation, and Measurement, are theoretically modeled in the present work by
developing a second quantization filed operator based Schrodinger-Poisson
self-consistent framework coupled to non-equilibrium Greens function formalism.
The study shows that the Bloch sphere coverage can be discretized along polar
and azimuthal directions by reducing the nanowire diameter and increasing the
inter-dot separation respectively, that can be utilized for selective
information encoding. The theoretically obtained stability diagrams suggest
that downscaled nanowire diameter and increased gate separation sharpen the
bonding and anti-bonding states with reduced anticrossing leading to a gradual
transformation of the hyperbolic current mapping into a pair of straight lines.
However, the dephasing time in the proposed GaAs VTQD-based qubit may be
significantly improved by scaling down both the nanowire diameter and gate
separation. Therefore, the present study suggests an optimization window for
geometrical engineering of a dual gate nanowire FET qubit to achieve superior
qubit performance. Most importantly, such device is compatible with the
mainstream CMOS technology and can be utilized for large scale implementation
by little modification of the state of the art fabrication processes.
