  Pedestrian detection is one of the key problems in emerging self-driving car
industry. And HOG algorithm has proven to provide good accuracy for pedestrian
detection. There are plenty of research works have been done in accelerating
HOG algorithm on FPGA because of its low-power and high-throughput
characteristics. In this paper, we present a high-performance HOG architecture
for pedestrian detection on a low-cost FPGA platform. It achieves a maximum
throughput of 526 FPS with 640x480 input images, which is 3.25 times faster
than the state of the art design. The accelerator is integrated with SVM-based
prediction in realizing a pedestrian detection system. And the power
consumption of the whole system is comparable with the best existing
implementations.
