  Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has
developed a full wafer redistribution and embedding technology as base for a
large-scale neuromorphic hardware system. The paper will give an overview of
the neuromorphic computing platform at the KIP and the associated hardware
requirements which drove the described technological developments. In the first
phase of the project standard redistribution technologies from wafer level
packaging were adapted to enable a high density reticle-to-reticle routing on
200mm CMOS wafers. Neighboring reticles were interconnected across the scribe
lines with an 8{\mu}m pitch routing based on semi-additive copper
metallization. Passivation by photo sensitive benzocyclobutene was used to
enable a second intra-reticle routing layer. Final IO pads with flash gold were
generated on top of each reticle. With that concept neuromorphic systems based
on full wafers could be assembled and tested. The fabricated high density
inter-reticle routing revealed a very high yield of larger than 99.9%. In order
to allow an upscaling of the system size to a large number of wafers with
feasible effort a full wafer embedding concept for printed circuit boards was
developed and proven in the second phase of the project. The wafers were
thinned to 250{\mu}m and laminated with additional prepreg layers and copper
foils into a core material. After lamination of the PCB panel the reticle IOs
of the embedded wafer were accessed by micro via drilling, copper
electroplating, lithography and subtractive etching of the PCB wiring
structure. The created wiring with 50um line width enabled an access of the
reticle IOs on the embedded wafer as well as a board level routing. The panels
with the embedded wafers were subsequently stressed with up to 1000 thermal
cycles between 0C and 100C and have shown no severe failure formation over the
cycle time.
