  The proliferation of deep learning (DL) has led to the emergence of privacy
and security concerns. To address these issues, secure Two-party computation
(2PC) has been proposed as a means of enabling privacy-preserving DL
computation. However, in practice, 2PC methods often incur high computation and
communication overhead, which can impede their use in large-scale systems. To
address this challenge, we introduce RRNet, a systematic framework that aims to
jointly reduce the overhead of MPC comparison protocols and accelerate
computation through hardware acceleration. Our approach integrates the hardware
latency of cryptographic building blocks into the DNN loss function, resulting
in improved energy efficiency, accuracy, and security guarantees. Furthermore,
we propose a cryptographic hardware scheduler and corresponding performance
model for Field Programmable Gate Arrays (FPGAs) to further enhance the
efficiency of our framework. Experiments show RRNet achieved a much higher ReLU
reduction performance than all SOTA works on CIFAR-10 dataset.
