  The computing industry is forced to find alternative design approaches and
computing platforms to sustain increased power efficiency, while providing
sufficient performance. Among the examined solutions, Approximate Computing,
Hardware Acceleration, and Heterogeneous Computing have gained great momentum.
In this Dissertation, we introduce design solutions and methodologies, built on
top of the preceding computing paradigms, for the development of
energy-efficient DSP and AI accelerators. In particular, we adopt the promising
paradigm of Approximate Computing and apply new approximation techniques in the
design of arithmetic circuits. The proposed arithmetic approximation techniques
involve bit-level optimizations, inexact operand encodings, and skipping of
computations, while they are applied in both fixed- and floating-point
arithmetic. We also conduct an extensive exploration on combinations among the
approximation techniques and propose a low-overhead scheme for seamlessly
adjusting the approximation degree of our circuits at runtime. Based on our
methodology, these arithmetic approximation techniques are then combined with
hardware design techniques to implement approximate ASIC- and FPGA-based DSP
and AI accelerators. Moreover, we propose methodologies for the efficient
mapping of DSP/AI kernels on distinctive embedded devices, i.e., the
space-grade FPGAs and the heterogeneous VPUs. On the one hand, we cope with the
decreased flexibility of space-grade technology and the technical challenges
that arise in new FPGA tools. On the other hand, we unlock the full potential
of heterogeneity by exploiting all the diverse processors and memories. Based
on our methodology, we efficiently map computer vision algorithms onto the
radiation-hardened NanoXplore's FPGAs and accelerate DSP & CNN kernels on
Intel's Myriad VPUs.
