  This paper presents a new radix-2^k multi-path FFT architecture, named MSC
FFT, which is based on a single-path radix-2 serial commutator (SC) FFT
architecture. The proposed multi-path architecture has a very high hardware
utilization that results in a small chip area, while providing high throughput.
In addition, the adoption of radix-2^k FFT algorithms allows for simplifying
the rotators even further. It is achieved by optimizing the structure of the
processing element (PE). The implemented architecture is a 128-point 4-parallel
multi-path SC FFT using 90 nm process. Its area and power consumption at 250
MHz are only 0.167 mm2 and 14.81 mW, respectively. Compared with existing
works, the proposed design reduces significantly the chip rea and the power
consumption, while providing high throughput.
