  The proliferation of number of processing elements (PEs) in parallel computer
systems, along with the use of more extensive parallelization of algorithms
causes the interprocessor communications dominate VLSI chip space. This paper
proposes a new architecture to overcome this issue by using simple crosspoint
switches to pair PEs instead of a complex interconnection network. Based on the
cyclic permutation wiring idea described in \cite{oruc2016self}, this pairing
leads to a linear crosspoint array of $n(n-1)/2$ processing elements and as
many crosspoints. We demonstrate the versatility of this new parallel
architecture by designing fast searching and sorting algorithms for it. In
particular, we show that finding a minimum, maximum, and searching a list of
$n$ elements can all be performed in $O(1)$ time with elementary logic gates
with $O(n)$ fan-in, and in $O(\lg n)$ time with $O(1)$ fan-in. We further show
that sorting a list of $n$ elements can also be carried out in $O(1)$ time
using elementary logic gates with $O(n)$ fan-in and threshold logic gates. The
sorting time increases to $O(\lg n\lg\lg n)$ if only elementary logic gates
with $O(1)$ fan-in are used. The algorithm can find the maximum among $n$
elements in $O(1)$ time, and sort $n$ elements in $O(\lg n (\lg\lg n))$ time.
In addition, we show how other fundamental queries can be handled within the
same order of time complexities.
