  One of the biggest concerns in IoT is privacy and security. Encryption and
authentication need big power budgets, which battery-operated IoT end-nodes do
not have. Hardware accelerators designed for specific cryptographic operations
provide little to no flexibility for future updates. Custom instruction
solutions are smaller in area and provide more flexibility for new methods to
be implemented. One drawback of custom instructions is that the processor has
to wait for the operation to finish. Eventually, the response time of the
device to real-time events gets longer. In this work, we propose a processor
with an extended custom instruction for modular multiplication, which blocks
the processor, typically, two cycles for any size of modular multiplication
when used in Partial Execution mode. We adopted embedded and compressed
extensions of RISC-V for our proof-of-concept CPU. Our design is benchmarked on
recent cryptographic algorithms in the field of elliptic-curve cryptography.
Our CPU with 128-bit modular multiplication operates at 136MHz on ASIC and
81MHz on FPGA. It achieves up to 13x speed up on software implementations while
reducing overall power consumption by up to 95\% with 41\% average area
overhead over our base architecture.
