  Using a two-dimensional finite-differences scheme to model spin transport in
silicon devices with lateral geometry, we simulate the effects of spin
relaxation at interfacial boundaries, i.e. the exposed top surface and at an
electrostatically-controlled backgate with SiO_2 dielectric. These
gate-voltage-dependent simulations are compared to previous experimental
results and show that strong spin relaxation due to extrinsic effects yield an
Si/SiO_2 interfacial spin lifetime of ~ 1ns, orders of magnitude lower than
lifetimes in the bulk Si, whereas relaxation at the top surface plays no
substantial role. Hall effect measurements on ballistically injected electrons
gated in the transport channel yield the carrier mobility directly and suggest
that this reduction in spin lifetime is only partially due to enhanced
interfacial momentum scattering which induces random spin flips as in the
Elliott effect. Therefore, other extrinsic mechanisms such as those caused by
paramagnetic defects should also be considered in order to explain the dramatic
enhancement in spin relaxation at the gate interface over bulk values.
