  We propose a new fixed latency scheme for Xilinx gigabit transceivers that
will be used in the upgrade of the ATLAS forward muon spectrometer at the Large
Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link
between a frontend data serializer ASIC and a packet router. To achieve fixed
latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA,
while minimally relying on the embedded features of the FPGA transceivers. The
scheme is protocol independent and can be adapted to FPGA from other vendors
with similar resources. This paper presents a detailed implementation of the
fixed latency scheme, as well as simulations of the real environment in the
ATLAS forward muon region.
