  Finite state machines (FSM's) are implemented with sequential circuits and
are used to orchestrate the operation of hardware designs. Sequential
obfuscation schemes aimed at preventing IP theft often operate by augmenting a
design's FSM post-synthesis. Many such schemes are based on the ability to
recover the FSM's topology from the synthesized design. In this paper, we
present two tools which can improve the performance of topology extraction:
RECUT, which extracts the FSM implementation from a netlist, and REFSM-SAT,
which solves topology enumeration as a series of SAT problems. In some cases,
these tools can improve performance significantly over current methods,
attaining up to a 99\% decrease in runtime.
