  In recent years increasingly complex architectures for deep convolution
networks (DCNs) have been proposed to boost the performance on image
recognition tasks. However, the gains in performance have come at a cost of
substantial increase in computation and model storage resources. Fixed point
implementation of DCNs has the potential to alleviate some of these
complexities and facilitate potential deployment on embedded hardware. In this
paper, we propose a quantizer design for fixed point implementation of DCNs. We
formulate and solve an optimization problem to identify optimal fixed point
bit-width allocation across DCN layers. Our experiments show that in comparison
to equal bit-width settings, the fixed point DCNs with optimized bit width
allocation offer >20% reduction in the model size without any loss in accuracy
on CIFAR-10 benchmark. We also demonstrate that fine-tuning can further enhance
the accuracy of fixed point DCNs beyond that of the original floating point
model. In doing so, we report a new state-of-the-art fixed point performance of
6.78% error-rate on CIFAR-10 benchmark.
