  In this work, we propose an adder for the 2D NTC architecture, designed to
match the architectural constraints of many quantum computing technologies. The
chosen architecture allows the layout of logical qubits in two dimensions and
the concurrent execution of one- and two-qubit gates with nearest-neighbor
interaction only. The proposed adder works in three phases. In the first phase,
the first column generates the summation output and the other columns do the
carry-lookahead operations. In the second phase, these intermediate values are
propagated from column to column, preparing for computation of the final carry
for each register position. In the last phase, each column, except the first
one, generates the summation output using this column-level carry. The depth
and the number of qubits of the proposed adder are $\Theta(\sqrt{n})$ and O(n),
respectively. The proposed adder executes faster than the adders designed for
the 1D NTC architecture when the length of the input registers $n$ is larger
than 58.
