  Analog-to-digital converters (ADCs) allow physical signals to be processed
using digital hardware. The power consumed in conversion grows with the
sampling rate and quantization resolution, imposing a major challenge in
power-limited systems. A common ADC architecture is based on sample-and-hold
(S/H) circuits, where the analog signal is being tracked only for a fraction of
the sampling period. In this paper, we propose the concept of eSampling ADCs,
which harvest energy from the analog signal during the time periods where the
signal is not being tracked. This harvested energy can be used to supplement
the ADC itself, paving the way to the possibility of zero-power consumption and
power-saving ADCs. We analyze the tradeoff between the ability to recover the
sampled signal and the energy harvested, and provide guidelines for setting the
sampling rate in the light of accuracy and energy constraints. Our analysis
indicates that eSampling ADCs operating with up to 12 bits per sample can
acquire bandlimited analog signals such that they can be perfectly recovered
without requiring power from the external source. Furthermore, our theoretical
results reveal that eSampling ADCs can in fact save power by harvesting more
energy than they consume. To verify the feasibility of eSampling ADCs, we
present a circuit-level design using standard complementary metal oxide
semiconductor (CMOS) 65 nm technology. An eSampling 8-bit ADC which samples at
40 MHZ is designed on a Cadence Virtuoso platform. Our experimental study
involving Nyquist rate sampling of bandlimited signals demonstrates that such
ADCs are indeed capable of harvesting more energy than that spent during
analog-to-digital conversion, without affecting the accuracy.
