  The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher
which operates on a sequence of blocks each consists of 128, 192 or 256 bits.
Moreover, the cipher key for the AES algorithm is a sequence of 128, 192 or 256
bits. AES algorithm has many sources of parallelism. In this paper, a design of
parallel AES on the multiprocessor platform is presented. While most of the
previous designs either use pipelined parallelization or take advantage of the
Mix_Column parallelization, our design is based on combining pipelining of
rounds and parallelization of Mix_Column and Add_Round_Key transformations.
This model is divided into two levels: the first is pipelining different
rounds, while the second is through parallelization of both the Add_Round_Key
and the Mix_Column transformations. Previous work proposed for pipelining AES
algorithm was based on using nine stages, while, we propose the use of eleven
stages in order to exploit the sources of parallelism in both initial and final
round. This enhances the system performance compared to previous designs. Using
two-levels of parallelization benefits from the highly independency of
Add_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis shows
that the parallel implementation of the AES achieves a better performance. The
analysis shows that using pipeline increases significantly the degree of
improvement for both encryption and decryption by approximately 95%. Moreover,
parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column transformations
increases the degree of improvement by approximately 98%. This leads to the
conclusion that the proposed design is scalable and is suitable for real-time
applications.
