  Software-hardware co-design solutions for decimal computation can provide
several Pareto points to development of embedded systems in terms of hardware
cost and performance. This paper demonstrates how to accurately evaluate such
co-design solutions using RISC-V ecosystem. In a software-hardware co-design
solution, a part of solution requires dedicated hardware. In our evaluation
framework, we develop new decimal oriented instructions supported by an
accelerator. The framework can realize cycle-accurate analysis for performance
as well as hardware overhead for co-design solutions for decimal computation.
The obtained performance result is compared with an estimation with dummy
functions.
