  We investigate die-level and wafer-scale uniformity of Dolan-bridge and
bridgeless Manhattan Josephson junctions, using multiple substrates with and
without through-silicon vias (TSVs). Dolan junctions fabricated on planar
substrates have the highest yield and lowest room-temperature conductance
spread, equivalent to ~100 MHz in transmon frequency. In TSV-integrated
substrates, Dolan junctions suffer most in both yield and disorder, making
Manhattan junctions preferable. Manhattan junctions show pronounced conductance
decrease from wafer centre to edge, which we qualitatively capture using a
geometric model of spatially-dependent resist shadowing during junction
electrode evaporation. Analysis of actual junction overlap areas using scanning
electron micrographs supports the model, and further points to a remnant
spatial dependence possibly due to contact resistance.
