  The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in
MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the
gate has attracted much attention. Recently, we modeled this effect in the
framework of a FE polarization switching model. However, there is a large
amount of literature attributing this effect to a stabilization of quasi-static
(QS) negative capacitance (NC) in the FE. The technological implications of a
stabilized non-switching (NS) QSNC model vs a FE switching model are vastly
different; the latter precluding applications to sub-60 mV/dec SS scaled CMOS
due to speed limitations and power dissipated in switching. In this letter, we
provide a thorough analysis assessing the foundations of models of QSNC,
identifying which specific assumptions (ansatz) may be unlikely or unphysical,
and analyzing their applicability. We show that it is not reasonable to expect
QSNC for two separate capacitors connected in series (with a metal plate
between dielectric (DE) and FE layers). We propose a model clarifying under
which conditions a QS "apparent NC" for a FE layer in a FE-DE bi-layer stack
may be observed, quantifying the requirements of strong interface polarization
coupling in addition to capacitance matching. In this regime, our model
suggests the FE layer does not behave as a NC layer, simply, the coupling leads
to both the DE and FE behaving as high-k DE with similar permittivities. This
may be useful for scaled EOT devices but does not lead to sub-60 mV/dec SS.
