  Quantum Error Correction (QEC) is required in quantum computers to mitigate
the effect of errors on physical qubits. When adopting a QEC scheme based on
surface codes, error decoding is the most computationally expensive task in the
classical electronic back-end. Decoders employing neural networks (NN) are
well-suited for this task but their hardware implementation has not been
presented yet. This work presents a space exploration of fully-connected
feed-forward NN decoders for small distance surface codes. The goal is to
optimize the neural network for high decoding performance, while keeping a
minimalistic hardware implementation. This is needed to meet the tight delay
constraints of real-time surface code decoding. We demonstrate that hardware
based NN-decoders can achieve high decoding performance comparable to other
state-of-the-art decoding algorithms whilst being well below the tight delay
requirements $(\approx 440\ \mathrm{ns})$ of current solid-state qubit
technologies for both ASIC designs $(<30\ \mathrm{ns})$ and FPGA
implementations $(<90\ \mathrm{ns})$. These results designates NN-decoders as
fitting candidates for an integrated hardware implementation in future
large-scale quantum computers.
