  Recently, reversible circuit synthesis has been intensively studied. One of
the problems that has not been solved for a long time was exact minimization of
gate count (GC) in 4-bit circuits. Finally, last year a tool of practical usage
for finding optimal gate count Toffoli networks for any 4-variable function was
developed. However, not much work has been done yet on exact minimization of
quantum cost (QC) in 4-bit circuits. This paper presents an application of the
above mentioned tool to reducing QC of 4-bit reversible circuits. It is shown
that for benchmarks and for designs taken from recent publications it is
possible to obtain savings in QC of up to 74% comparing with previously known
circuits.
