  In this study, a time fractional dual-phase-lag model with temperature jump
boundary condition as a choice for the Fourier's law replacement in thermal
modeling of transistors, is utilized. In more details, the numerical simulation
of heat transfer in newly proposed TMTC field effect transistors using
fractional DPL equation has been investigated. Moreover, the Caputo fractional
derivative is employed to formulate the finite difference scheme for
discretization of the fractional DPL model. In order to obtain more precise
results for the peak temperature rise, the temperature and heat flux profiles,
the size-dependent thermal properties are taken into account. Also, the
temperature jump boundary condition has been also applied by means of a
mixed-type boundary condition. It is obtained that considering size-dependent
thermal characteristics for transistors under study, results in increase of the
peak temperature rise up to 250 percent. Furthermore, considering constant bulk
thermal properties for the silicon MOSFET, certain oscillations are observed in
the time-variation of the peak temperature rise for alpha= 0.7, 0.9 and 1. This
presents the so-called negative bias temperature instability appearing in
electronic nano-semiconductor devices. Finally, the hotspot temperature has
been researched in transistors containing two-dimensional materials with quasi
one-dimensional band structure channels. It is obtained that among the studied
FETs, titanium trisulfide with maximum temperature increase of 19.63 K exhibits
the least peak temperature rise. This presents that TiS3 may be an acceptable
silicon channel replacement as far as the thermal issues are concerned.
