  In this report, the hysteresis behaviors of PEI:LiClO4 and PEG:LiClO4
electrolyte gate and back gate Graphene-on-SiO2 FET were analyzed by
gate-voltage source-drain current modulation. It is shown that both the
sweeping rate and the sweep range will cause hysteresis behaviors in the form
of Dirac Point shifting or changes in the current. Different mechanisms
including charge trapping and electrical double layer capacitive effect are
proposed to explain the behavior qualitatively on both back gated and
electrolyte gated FET and partially confirmed with the present experimental
results.
