  The assumption of maximum parallelism support for the successful realization
of scalable quantum computers has led to homogeneous, ``sea-of-qubits''
architectures. The resulting architectures overcome the primary challenges of
reliability and scalability at the cost of physically unacceptable system area.
We find that by exploiting the natural serialization at both the application
and the physical microarchitecture level of a quantum computer, we can reduce
the area requirement while improving performance. In particular we present a
scalable quantum architecture design that employs specialization of the system
into memory and computational regions, each individually optimized to match
hardware support to the available parallelism. Through careful application and
system analysis, we find that our new architecture can yield up to a factor of
thirteen savings in area due to specialization. In addition, by providing a
memory hierarchy design for quantum computers, we can increase time performance
by a factor of eight. This result brings us closer to the realization of a
quantum processor that can solve meaningful problems.
