  Chiplet architectures are a promising paradigm to overcome the scaling
challenges of monolithic chips. Chiplets offer heterogeneity, modularity, and
cost-effectiveness. The design space of chiplet architectures is huge as there
are many degrees of freedom such as the number, size and placement of chiplets,
the topology of the inter-chiplet interconnect and many more. Existing tools
for cost and performance prediction are often too slow to explore this design
space. We present RapidChiplet, a fast, open-source toolchain to predict
latency and throughput of the inter-chiplet interconnect, as well as a chip's
manufacturing cost and thermal stability.
