  Silicon nanowires (Si NW) are ideal candidates for solution processable field
effect transistors (FETs). The interface between the nanowire channel and the
gate dielectric plays a crucial role in the FET performance, and it can be
responsible for unwanted effects such as hysteresis of the I-V characteristics
due to threshold voltage shift when the gate voltage is applied. Using
gate-voltage bias stress measurements we show that a large hysteresis of up to
40V in Si NW FETs with SiO2 dielectric is mainly due to the holes traps at the
nanowire/SiO2 interface. An approach for reducing this hysteresis to just 2.5V
using solution processable fluoropolymer dielectric Cytop in the top-gate
configuration is demonstrated. Experimental results suggest that the density of
surface traps in Si nanowire transistors is dictated mainly by the nature of
the dielectric layer. The influence of the gate dielectric was studied by
assessing the field effect transport behaviour of a representative double gate
FETs based on SiO2 bottom dielectric and top Cytop dielectric layer. Such
devices were characterised, revealing an order of magnitude higher hole traps
density at the nanowire/SiO2 interface (1x10^13cm-2) compared to that of
nanowire/fluoropolymer interface (7.5x10^11cm-2).
