  The Large Hadron Collider (LHC) at CERN plans to have a series of upgrades to
increase its instantaneous luminosity to 7.5 the nominal luminosity. The
increased luminosity drastically impacts the ATLAS trigger and readout data
rates. The inner-most station of the ATLAS muon spectrometer, the so-called
Small Wheels is being replaced with a New Small Wheel (NSW) system, consisting
of Micromegas and small-strip Thin Gap Chambers (sTGC) detectors. The
on-detector radiation levels required radiation tolerant electronics. The lower
radiation levels on the rim of the NSW allowed utilizing commercial electronic
chips, such as Field Programmable Gate Arrays (FPGAs), in the trigger chain of
the sTGC detectors. Those FPGAs require an ultra-low jitter clock for the
proper operation of their Gigabit transceivers (4.8 Gbps serial links). The
initial design was based on a clock provided by a radiation tolerant ASIC
designed at CERN, but due to its intrinsic jitter and consequent marginal error
rate on the transmission lines, a different approach had to be chosen. An
additional clock source based on commercial jitter cleaners, fan-out chips and
optical transmitters driving dedicated fibers was built. The new scheme
provides 64 low-jitter clocks (32 main and redundant) from the
radiation-protected area (USA15) to the trigger electronics over 60 m of OM3
fiber.
