  RISC-V, an open instruction set architecture, is getting the attention of
soft processor developers. Implementing only a basic 32-bit integer instruction
set of RISC-V, which is defined as RV32I, might be satisfactory for embedded
systems. However, multiplication and division instructions are not present in
RV32I, rather than defined as M-extension. Several research projects have
proposed both RV32I and RV32IM processor. However, there is no indication of
how much performance can be improved by adding M-extension to RV32I. In other
words, when we should consider adding M-extension into the soft processor and
how much hardware resource requirements will increase.
  In this paper, we propose an extension of the RVCoreP soft processor (which
implements RV32I instruction set only) to support RISC-V M-extension
instructions. A simple fork-join method is used to expand the execution
capability to support M-extension instructions as well as a possible future
enhancement. We then perform the benchmark using Dhrystone, Coremark, and
Embench programs. We found that RV32IM is 1.87 and 3.13 times better in
performance for radix-4 and DSP multiplier, respectively. In addition to that,
our RV32IM implementation is 13\% better than the equivalent RISC-V processor.
