  Sparse matrices and linear algebra are at the heart of scientific
simulations. Over the years, more than 70 sparse matrix storage formats have
been developed, targeting a wide range of hardware architectures and matrix
types, each of which exploit the particular strengths of an architecture, or
the specific sparsity patterns of the matrices.
  In this work, we explore the suitability of storage formats such as COO, CSR
and DIA for emerging architectures such as AArch64 CPUs and FPGAs. In addition,
we detail hardware-specific optimisations to these targets and evaluate the
potential of each contribution to be integrated into Morpheus, a modern library
that provides an abstraction of sparse matrices (currently) across x86 CPUs and
NVIDIA/AMD GPUs. Finally, we validate our work by comparing the performance of
the Morpheus-enabled HPCG benchmark against vendor-optimised implementations.
