  Recent developments in the interfacing of neurons with silicon chips may pave
the way for progress in constructing scalable neurocomputers. The assembly of
synthetic neuronal networks with predefined synaptic connections and controlled
geometric structure has been realized experimentally within the last decade.
Furthermore, when such neuronal networks are interfaced with semiconductors,
action potentials in neurons of the network can be elicited by capacitative
stimulators, and voltage measurements can be made by transistors incorporated
into the associated silicon chip. Despite the impressive progress, such
preliminary devices have not yet demonstrated the performance of useful
computations, and constructing larger devices can be both expensive and
time-consuming. Accordingly, an appropriate modeling framework with the
capability to simulate current experimental results in such devices may be used
to make useful predictions regarding their potential computational power. A
proposed modeling framework for functional neuronal networks interfaced with
silicon chips is presented below.
