  An Efficient Simulation of application specific instruction-set processors
(ASIP) is a challenging onus in the area of VLSI design. This paper
reconnoiters the possibility of use of ASIP simulators for ASIP Simulation.
This proposed study allow as the simulation of the cache memory design with
various ASIP simulators like Simple scalar and VEX. In this paper we have
implemented the memory configuration according to desire application. These
simulators performs the cache related results such as cache name, sets, cache
associativity, cache block size, cache replacement policy according to specific
application.
