  Using optimal phasor measurement unit placement as a prototypical problem, we
assess the computational viability of the current generation D-Wave Systems
2000Q quantum annealer for power systems design problems. We reformulate
minimum dominating set for the annealer hardware, solve the reformulation for a
standard set of IEEE test systems, and benchmark solution quality and time to
solution against the CPLEX Optimizer and simulated annealing. For some problem
instances the 2000Q outpaces CPLEX. For instances where the 2000Q underperforms
with respect to CPLEX and simulated annealing, we suggest hardware improvements
for the next generation of quantum annealers.
