  Computing elements of CPSs must be flexible to ensure interoperability; and
adaptive to cope with the evolving internal and external state, such as battery
level and critical tasks. Cryptography is a common task needed in CPSs to
guarantee private communication among different devices. In this work, we
propose a reconfigurable FPGA accelerator for AES workloads with different key
lengths. The accelerator architecture exploits tagged-dataflow models to
support the concurrent execution of multiple threads on the same accelerator.
This solution demonstrates to be more resource- and energy-efficient than a set
of non-reconfigurable accelerators while keeping high performance and
flexibility of execution.
