  A mathematical model of the voltage drop which arises in on-chip power
distribution networks is used to compare the maximum voltage drop in the case
of different geometric arrangements of the pads supplying power to the chip.
These include the square or Manhattan power pad arrangement which currently
predominates, as well as equilateral triangular and hexagonal arrangements. In
agreement with findings in the literature and with physical and SPICE models,
the equilateral power pad arrangement, independent of the underlying power mesh
configuration, is found to minimize the maximum voltage drop. This headline
finding is a consequence of relatively simple formulas for the voltage drop,
with explicit error bounds, which are established using complex analysis
techniques, and elliptic functions in particular.
