  We have designed, fabricated, and successfully tested a prototype
mixed-signal, 28x28-binary-input, 10-output, 3-layer neuromorphic network ("MLP
perceptron"). It is based on embedded nonvolatile floating-gate cell arrays
redesigned from a commercial 180-nm NOR flash memory. The arrays allow precise
(~1%) individual tuning of all memory cells, having long-term analog-level
retention and low noise. Each array performs a very fast and energy-efficient
analog vector-by-matrix multiplication, which is the bottleneck for signal
propagation in most neuromorphic networks. All functional components of the
prototype circuit, including 2 synaptic arrays with 101,780 floating-gate
synaptic cells, 74 analog neurons, and the peripheral circuitry for weight
adjustment and I/O operations, have a total area below 1 mm^2. Its testing on
the common MNIST benchmark set (at this stage, with a relatively low weight
import precision) has shown a classification fidelity of 94.65%, close to the
96.2% obtained in simulation. The classification of one pattern takes less than
1 us time and ~20 nJ energy - both numbers much better than for digital
implementations of the same task. Estimates show that this performance may be
further improved using a better neuron design and a more advanced memory
technology, leading to a >10^2 advantage in speed and a >10^4 advantage in
energy efficiency over the state-of-the-art purely digital (GPU and custom)
circuits, at classification of large, complex patterns.
