  As customized accelerator design has become increasingly popular to keep up
with the demand for high performance computing, it poses challenges for modern
simulator design to adapt to such a large variety of accelerators. Existing
simulators tend to two extremes: low-level and general approaches, such as RTL
simulation, that can model any hardware but require substantial effort and long
execution times; and higher-level application-specific models that can be much
faster and easier to use but require one-off engineering effort.
  This work proposes a compiler-driven simulation workflow that can model
configurable hardware accelerator. The key idea is to separate structure
representation from simulation by developing an intermediate language that can
flexibly represent a wide variety of hardware constructs. We design the Event
Queue (EQueue) dialect of MLIR, a dialect that can model arbitrary hardware
accelerators with explicit data movement and distributed event-based control;
we also implement a generic simulation engine to model EQueue programs with
hybrid MLIR dialects representing different abstraction levels. We demonstrate
two case studies of EQueue-implemented accelerators: the systolic array of
convolution and SIMD processors in a modern FPGA. In the former we show EQueue
simulation is as accurate as a state-of-the-art simulator, while offering
higher extensibility and lower iteration cost via compiler passes. In the
latter we demonstrate our simulation flow can guide designer efficiently
improve their design using visualizable simulation outputs.
