  Supporting the programming of stateful packet forwarding functions in
hardware has recently attracted the interest of the research community. When
designing such switching chips, the challenge is to guarantee the ability to
program functions that can read and modify data plane's state, while keeping
line rate performance and state consistency. Current state-of-the-art designs
are based on a very conservative all-or-nothing model: programmability is
limited only to those functions that are guaranteed to sustain line rate, with
any traffic workload. In effect, this limits the maximum time to execute state
update operations. In this paper, we explore possible options to relax these
constraints by using simulations on real traffic traces. We then propose a
model in which functions can be executed in a larger but bounded time, while
preventing data hazards with memory locking. We present results showing that
such flexibility can be supported with little or no throughput degradation.
