  The recent push for post-Moore computer architectures has introduced a wide
variety of application-specific accelerators. One particular accelerator, the
resistance network analogue, has been well received due to its ability to
efficiently solve partial differential equations by eliminating the iterative
stages required by today's numerical solvers. However, in the ago of
programmable integrated circuits, the static nature of the resistance network
analogue, and other analog mesh computers like it, has relegated it to an
academic curiosity. Recent developments in materials, such as the memristor,
have made the resistance network analogue viable for inclusion in future
heterogeneous computer architectures. However, selection of an appropriate
sized mesh to be incorporated into a computer system requires that
energy-quality trade-offs are made regarding the problem size and required
resolution of the solution. This paper provides an in-depth study of the
scaling of analog mesh computer hardware, from the perspective of energy per
bit and required resolution, introduces a metric to aid in quantifying analog
mesh computers with different parameters, and introduces a method of
virtualization which enables an analog mesh computer of a fixed size to
approximate the calculations of a larger-sized mesh.
