  Chips with hundreds to thousands of cores require scalable networks-on-chip
(NoCs). Customization of the NoC topology is necessary to reach the diverse
design goals of different chips. We introduce sparse Hamming graph, a novel NoC
topology with an adjustable costperformance trade-off that is based on four NoC
topology design principles we identified. To efficiently customize this
topology, we develop a toolchain that leverages approximate floorplanning and
link routing to deliver fast and accurate cost and performance predictions. We
demonstrate how to use our methodology to achieve desired cost-performance
trade-offs while outperforming established topologies in cost, performance, or
both.
