  Recent advances in quantum computing pose a serious threat on the security of
widely used public-key cryptosystems. Thus, new post-quantum cryptographic
algorithms have been proposed as part of the associated US NIST process to
enable secure, encrypted communication in the age of quantum computing. Many
hardware accelerators for structured lattice-based algorithms have already been
published to meet the strict power, area and latency requirements of low-power
IoT edge devices. However, the security of these algorithms is still uncertain.
Currently, many new attacks against the lattice structure are investigated to
judge on their security. In contrast, code-based algorithms, which rely on
deeply explored security metrics and are appealing candidates in the NIST
process, have not yet been investigated to the same depth in the context of IoT
due to the computational complexity and memory footprint of state-of-the-art
software implementations.
  In this paper, we present to the best of our knowledge the first HW/SW
co-design based implementation of the code-based Hamming Quasi Cyclic
Key-Encapsulation Mechanism. We profile and evaluate this algorithm in order to
explore the trade-off between software optimizations, tightly coupled hardware
acceleration by instruction set extension and modular, loosely coupled
accelerators. We provide detailed results on the energy consumption and
performance of our design and compare it to existing implementations of
lattice- and code-based algorithms. The design was implemented in two
technologies: FPGA and ASIC. Our results show that code-based algorithms are
valid alternatives in low-power IoT from an implementation perspective.
