  RRAM-based multi-core systems improve the energy efficiency and performance
of CNNs. Thereby, the distributed parallel execution of convolutional layers
causes critical data dependencies that limit the potential speedup. This paper
presents synchronization techniques for parallel inference of convolutional
layers on RRAM-based CIM architectures. We propose an architecture optimization
that enables efficient data exchange and discuss the impact of different
architecture setups on the performance. The corresponding compiler algorithms
are optimized for high speedup and low memory consumption during CNN inference.
We achieve more than 99% of the theoretical acceleration limit with a marginal
data transmission overhead of less than 4% for state-of-the-art CNN benchmarks.
