  This paper reviews recent progress and key challenges in process and
reliability for high-performance vertical GaN transistors and diodes, focusing
on the 200 mm CMOS-compatible technology. We particularly demonstrated the
potential of using 200 mm diameter CTE matched substrates for vertical power
transistors, and gate module optimizations for device robustness. An
alternative technology path based on coalescence epitaxy of GaN-on-Silicon is
also introduced, which could enable thick drift layers of very low dislocation
density.
