  Realizing compact and scalable Ising machines that are compatible with
CMOS-process technology is crucial to the effectiveness and practicality of
using such hardware platforms for accelerating computationally intractable
problems. Besides the need for realizing compact Ising spins, the
implementation of the coupling network, which describes the spin interaction,
is also a potential bottleneck in the scalability of such platforms. Therefore,
in this work, we propose an Ising machine platform that exploits the novel
behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as
classical Ising spins interacting through highly scalable and CMOS-process
compatible ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) which act as
coupling elements. We experimentally demonstrate the prototype building blocks
of this system, and evaluate the behavior of the scaled system using
simulations. We project that the proposed architecture can compute Ising
solutions with an efficiency of ~1.04 x 10^8 solutions/W/second. Our work not
only provides a pathway to realizing CMOS-compatible designs but also to
overcoming their scaling challenges.
