  Dynamic digital timing analysis is a less accurate but fast alternative to
highly accurate but slow analog simulations of digital circuits. It relies on
gate delay models, which allow the determination of input-to-output delays of a
gate on a per-transition basis. Accurate delay models not only consider the
effect of preceding output transitions here but also delay variations induced
by multi-input switching (MIS) effects in the case of multi-input gates.
Starting out from a first-order hybrid delay model for CMOS two-input NOR
gates, we develop a hybrid delay model for Muller C gates and show how to
augment these models and their analytic delay formulas by a first-order
interconnect. Moreover, we conduct a systematic evaluation of the resulting
modeling accuracy: Using SPICE simulations, we quantify the MIS effects on the
gate delays under various wire lengths, load capacitances, and input strengths
for two different CMOS technologies, comparing these results to the predictions
of appropriately parameterized versions of our new gate delay models. Overall,
our experimental results reveal that they capture all MIS effects with a
surprisingly good accuracy despite being first-order only.
