  Dynamic partial reconfiguration (DPR) allows one region of an
field-programmable gate array (FPGA) fabric to be reconfigured without
affecting the operations on the rest of the fabric. To use an FPGA as a
dynamically shared compute resource, one could partition and manage an FPGA
fabric as multiple DPR partitions that can be independently reconfigured at
runtime with different application function units (AFUs). Unfortunately,
dividing a fabric into DPR partitions with fixed boundaries causes the
available fabric resources to become fragmented. An AFU of a given size cannot
be loaded unless a sufficiently large DPR partition was floorplanned at build
time. To overcome this inefficiency, we devised an "amorphous" DPR technique
that is compatible with current device and tool support but does not require
the DPR partition boundaries to be a priori fixed. A collection of AFU
bitstreams can be simultaneously loaded on the fabric if their footprints (the
actual area used by an AFU) in the fabric do not overlap. We verified the
feasibility of amorphous DPR on Xilinx Zynq System-on-Chip (SoC) FPGAs using
Vivado. We evaluated the benefits of amorphous DPR in the context of a
dynamically reconfigurable vision processing pipeline framework.
