  In this work, we propose stochastic Binary Spiking Neural Network (sBSNN)
composed of stochastic spiking neurons and binary synapses (stochastic only
during training) that computes probabilistically with one-bit precision for
power-efficient and memory-compressed neuromorphic computing. We present an
energy-efficient implementation of the proposed sBSNN using 'stochastic bit' as
the core computational primitive to realize the stochastic neurons and
synapses, which are fabricated in 90nm CMOS process, to achieve efficient
on-chip training and inference for image recognition tasks. The measured data
shows that the 'stochastic bit' can be programmed to mimic spiking neurons, and
stochastic Spike Timing Dependent Plasticity (or sSTDP) rule for training the
binary synaptic weights without expensive random number generators. Our results
indicate that the proposed sBSNN realization offers possibility of up to 32x
neuronal and synaptic memory compression compared to full precision (32-bit)
SNN and energy efficiency of 89.49 TOPS/Watt for two-layer fully-connected SNN.
