  Hardware accelerators are key to the efficiency and performance of
system-on-chip (SoC) architectures. With high-level synthesis (HLS), designers
can easily obtain several performance-cost trade-off implementations for each
component of a complex hardware accelerator. However, navigating this design
space in search of the Pareto-optimal implementations at the system level is a
hard optimization task. We present COSMOS, an automatic methodology for the
design-space exploration (DSE) of complex accelerators, that coordinates both
HLS and memory optimization tools in a compositional way. First, thanks to the
co-design of datapath and memory, COSMOS produces a large set of Pareto-optimal
implementations for each component of the accelerator. Then, COSMOS leverages
compositional design techniques to quickly converge to the desired trade-off
point between cost and performance at the system level. When applied to the
system-level design (SLD) of an accelerator for wide-area motion imagery
(WAMI), COSMOS explores the design space as completely as an exhaustive search,
but it reduces the number of invocations to the HLS tool by up to 14.6x.
