  With the use of belief propagation (BP) decoding algorithm, low-density
parity-check (LDPC) codes can achieve near-Shannon limit performance. In order
to evaluate the error performance of LDPC codes, simulators running on CPUs are
commonly used. However, the time taken to evaluate LDPC codes with very good
error performance is excessive. In this paper, efficient LDPC block-code
decoders/simulators which run on graphics processing units (GPUs) are proposed.
We also implement the decoder for the LDPC convolutional code (LDPCCC). The
LDPCCC is derived from a pre-designed quasi-cyclic LDPC block code with good
error performance. Compared to the decoder based on the randomly constructed
LDPCCC code, the complexity of the proposed LDPCCC decoder is reduced due to
the periodicity of the derived LDPCCC and the properties of the quasi-cyclic
structure. In our proposed decoder architecture, $\Gamma$ (a multiple of a
warp) codewords are decoded together and hence the messages of $\Gamma$
codewords are also processed together. Since all the $\Gamma$ codewords share
the same Tanner graph, messages of the $\Gamma$ distinct codewords
corresponding to the same edge can be grouped into one package and stored
linearly. By optimizing the data structures of the messages used in the
decoding process, both the read and write processes can be performed in a
highly parallel manner by the GPUs. In addition, a thread hierarchy minimizing
the divergence of the threads is deployed, and it can maximize the efficiency
of the parallel execution. With the use of a large number of cores in the GPU
to perform the simple computations simultaneously, our GPU-based LDPC decoder
can obtain hundreds of times speedup compared with a serial CPU-based simulator
and over 40 times speedup compared with an 8-thread CPU-based simulator.
