  We simulate the logical Hadamard gate in the surface code under a
circuit-level noise model, compiling it to a physical circuit on square-grid
connectivity hardware. Our paper is the first to do this for a logical unitary
gate on a quantum error-correction code. We consider two proposals, both via
patch-deformation: one that applies a transversal Hadamard gate (i.e. a domain
wall through time) to interchange the logical $X$ and $Z$ strings, and another
that applies a domain wall through space to achieve this interchange. We
explain in detail why they perform the logical Hadamard gate by tracking how
the stabilisers and the logical operators are transformed in each quantum
error-correction round. We optimise the physical circuits and evaluate their
logical failure probabilities, which we find to be comparable to those of a
quantum memory experiment for the same number of quantum error-correction
rounds. We present syndrome-extraction circuits that maintain the same
effective distance under circuit-level noise as under phenomenological noise.
We also explain how a $SWAP$-quantum error-correction round (required to return
the patch to its initial position) can be compiled to only four two-qubit gate
layers. This can be applied to more general scenarios and, as a byproduct,
explains from first principles how the "stepping" circuits of the recent Google
paper [McEwen, Bacon, and Gidney, Quantum 7, 1172 (2023)] can be constructed.
