  Deploying Deep Neural Networks in low-power embedded devices for real
time-constrained applications requires optimization of memory and computational
complexity of the networks, usually by quantizing the weights. Most of the
existing works employ linear quantization which causes considerable degradation
in accuracy for weight bit widths lower than 8. Since the distribution of
weights is usually non-uniform (with most weights concentrated around zero),
other methods, such as logarithmic quantization, are more suitable as they are
able to preserve the shape of the weight distribution more precise. Moreover,
using base-2 logarithmic representation allows optimizing the multiplication by
replacing it with bit shifting. In this paper, we explore non-linear
quantization techniques for exploiting lower bit precision and identify
favorable hardware implementation options. We developed the Quantization Aware
Training (QAT) algorithm that allowed training of low bit width Power-of-Two
(PoT) networks and achieved accuracies on par with state-of-the-art floating
point models for different tasks. We explored PoT weight encoding techniques
and investigated hardware designs of MAC units for three different quantization
schemes - uniform, PoT and Additive-PoT (APoT) - to show the increased
efficiency when using the proposed approach. Eventually, the experiments showed
that for low bit width precision, non-uniform quantization performs better than
uniform, and at the same time, PoT quantization vastly reduces the
computational complexity of the neural network.
