  This paper introduces a fully free and open source software (FOSS)
architecture-neutral FPGA framework comprising of Yosys for Verilog synthesis,
and nextpnr for placement, routing, and bitstream generation. Currently, this
flow supports two commercially available FPGA families, Lattice iCE40 (up to 8K
logic elements) and Lattice ECP5 (up to 85K elements) and has been
hardware-proven for custom-computing machines including a low-power
neural-network accelerator and an OpenRISC system-on-chip capable of booting
Linux. Both Yosys and nextpnr have been engineered in a highly flexible manner
to support many of the features present in modern FPGAs by separating
architecture-specific details from the common mapping algorithms. This
framework is demonstrated on a longest-path case study to find an atypical
single source-sink path occupying up to 45% of all on-chip wiring.
