  Hardware based memory pooling enabled by interconnect standards like CXL have
been gaining popularity amongst cloud providers and system integrators. While
pooling memory resources has cost benefits, it comes at a penalty of increased
memory access latency. With yet another addition to the memory hierarchy, local
DRAM can be potentially used as a block cache(DRAM Cache) for fabric attached
memory(FAM) and data prefetching techniques can be used to hide the FAM access
latency. This paper proposes a system for prefetching sub-page blocks from FAM
into DRAM cache for improving the data access latency and application
performance. We further optimize our DRAM cache prefetch mechanism through
enhancements that mitigate the performance degradation due to bandwidth
contention at FAM. We consider the potential for providing additional
functionality at the CXL-memory node through weighted fair queuing of demand
and prefetch requests. We compare such a memory-node level approach to adapting
prefetch rate at the compute-node based on observed latencies. We evaluate the
proposed system in single node and multi-node configurations with applications
from SPEC, PARSEC, Splash and GAP benchmark suites. Our evaluation suggests
DRAM cache prefetching result in 7% IPC improvement and both of proposed
optimizations can further increment IPC by 7-10%.
