  Triple Modular Redundancy (TMR) has been traditionally used to ensure
complete tolerance to a single fault or a faulty processing unit, where the
processing unit may be a circuit or a system. However, TMR incurs more than
200% overhead in terms of area and power compared to a single processing unit.
Hence, alternative redundancy approaches were proposed in the literature to
mitigate the design overheads associated with TMR, but they provide only
partial or moderate fault tolerance. This research presents a new
fault-tolerant design approach based on approximate computing called FAC that
has the same fault tolerance as TMR and achieves significant reductions in the
design metrics for physical implementation. FAC is suited for a plethora of
error-tolerant applications. Here, the performance of TMR and FAC has been
evaluated for a digital image processing application. The image processing
results obtained confirm the usefulness of FAC. When an example processing unit
was implemented using a 28-nm CMOS technology, FAC achieved a 15.3% reduction
in delay, a 19.5% reduction in area, and a 24.7% reduction in power compared to
TMR.
