  Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient
superconductor logic family. The latency of AQFP circuits is relatively long
compared to that of other superconductor logic families and thus such circuits
require low-latency clocking schemes. In a previous study, we proposed a
low-latency clocking scheme called delay-line clocking, in which the latency
for each logic operation is determined by the propagation delay of the
excitation current, and demonstrated a simple AQFP buffer chain that adopts
delay-line clocking. However, it is unclear whether more complex AQFP circuits
can adopt delay-line clocking. In the present study, we demonstrate AQFP logic
gates (AND and XOR gates) that use delay-line clocking as a step towards
implementing large-scale AQFP circuits with delay-line clocking. AND and XOR
gates with a latency of approximately 20 ps per gate are shown to operate at up
to 5 and 4 GHz, respectively, in experiments. We also demonstrate that
delay-line clocking enables phase skipping operation, in which some of the AQFP
buffers for phase synchronization are removed to reduce the junction count and
energy dissipation. The results indicate that delay-line clocking can enable
low-latency, low-energy, large-scale AQFP circuits.
