  Stencil computation is one of the fundamental computing patterns in many
application domains such as scientific computing and image processing. While
there are promising studies that accelerate stencils on FPGAs, there lacks an
automated acceleration framework to systematically explore both spatial and
temporal parallelisms for iterative stencils that could be either
computation-bound or memory-bound. In this paper, we present SASA, a scalable
and automatic stencil acceleration framework on modern HBM-based FPGAs. SASA
takes the high-level stencil DSL and FPGA platform as inputs, automatically
exploits the best spatial and temporal parallelism configuration based on our
accurate analytical model, and generates the optimized FPGA design with the
best parallelism configuration in TAPA high-level synthesis C++ as well as its
corresponding host code. Compared to state-of-the-art automatic stencil
acceleration framework SODA that only exploits temporal parallelism, SASA
achieves an average speedup of 3.74x and up to 15.73x speedup on the HBM-based
Xilinx Alveo U280 FPGA board for a wide range of stencil kernels.
