  Recommendation systems, social network analysis, medical imaging, and data
mining often involve processing sparse high-dimensional data. Such
high-dimensional data are naturally represented as tensors, and they cannot be
efficiently processed by conventional matrix or vector computations. Sparse
Tucker decomposition is an important algorithm for compressing and analyzing
these sparse high-dimensional data sets. When energy efficiency and data
privacy are major concerns, hardware accelerators on resource-constraint
platforms become crucial for the deployment of tensor algorithms. In this work,
we propose a hybrid computing framework containing CPU and FPGA to accelerate
sparse Tucker factorization. This algorithm has three main modules:
tensor-times-matrix (TTM), Kronecker products, and QR decomposition with column
pivoting (QRP). In addition, we accelerate the former two modules on a Xilinx
FPGA and the latter one on a CPU. Our hybrid platform achieves $23.6 \times
\sim 1091\times$ speedup and over $93.519\% \sim 99.514 \%$ energy savings
compared with CPU on the synthetic and real-world datasets.
