  This article presents a reconfigurable physically unclonable function (PUF)
design fabricated using 65-nm CMOS technology. A subthreshold-inverter-based
static PUF cell achieves 0.3% native bit error rate (BER) at 0.062-fJ per bit
core energy efficiency. A flexible, native transistor-based voltage regulation
scheme achieves low-overhead supply regulation with 6-mV/V line sensitivity,
making the PUF resistant against voltage variations. Additionally, the PUF cell
is designed to be reconfigurable with no area overhead, which enables
stabilization without redundancy on chip. Thanks to the highly stable and
self-regulated PUF cell and the zero-overhead stabilization scheme, a 0.00182%
native BER is obtained after reconfiguration. The proposed design shows
0.12%/10 {\deg}C and 0.057%/0.1-V bit error across the military-grade
temperature range from -55 {\deg}C to 125 {\deg}C and supply voltage variation
from 0.7 to 1.4 V. The total energy per bit is 15.3 fJ. Furthermore, the
unstable bits can be detected by sweeping the body bias instead of temperature
during enrollment, thereby significantly reducing the testing costs. Last but
not least, the prototype exhibits almost ideal uniqueness and randomness, with
a mean inter-die Hamming distance (HD) of 0.4998 and a 1020x inter-/intra-die
HD separation. It also passes both NIST 800-22 and 800-90B randomness tests.
