  With continued feature size scaling, even state of the art semiconductor
manufacturing processes will often run into layouts with poor printability and
yield. Identifying lithography hotspots is important at both physical
verification and early physical design stages. While detailed lithography
simulations can be very accurate, they may be too computationally expensive for
full-chip scale and physical design inner loops. Meanwhile, pattern matching
and machine learning based hotspot detection methods can provide acceptable
quality and yet fast turn-around-time for full-chip scale physical verification
and design. In this paper, we discuss some key issues and recent results on
lithography hotspot detection and mitigation in nanometer VLSI.
