  Write disturbance error (WDE) appears as a serious reliability problem
preventing phase-change memory (PCM) from general commercialization, and
therefore several studies have been proposed to mitigate WDEs.
Verify-and-correction (VnC) eliminates WDEs by always verifying the data
correctness on neighbors after programming, but incurs significant performance
overhead. Encoding-based schemes mitigate WDEs by reducing the number of
WDE-vulnerable data patterns; however, mitigation performance notably
fluctuates with applications. Moreover, encoding-based schemes still rely on
VnC-based schemes. Cache-based schemes lower WDEs by storing data in a write
cache, but it requires several megabytes of SRAM to significantly mitigate
WDEs. Despite the efforts of previous studies, these methods incur either
significant performance or area overhead. Therefore, a new approach, which does
not rely on VnC-based schemes or application data patterns, is highly
necessary. Furthermore, the new approach should be transparent to processors
(i.e., in-module), because the characteristic of WDEs is determined by
manufacturers of PCM products. In this paper, we present an in-module
disturbance barrier (IMDB) that mitigates WDEs on demand. IMDB includes a
two-level hierarchy comprising two SRAM-based tables, whose entries are managed
with a dedicated replacement policy that sufficiently utilizes the
characteristics of WDEs. The naive implementation of the replacement policy
requires hundreds of read ports on SRAM, which is infeasible in real hardware;
hence, an approximate comparator is also designed. We also conduct a rigorous
exploration of architecture parameters to obtain a cost-effective design. The
proposed method significantly reduces WDEs without noticeable speed degradation
or additional energy consumption compared to previous methods.
