  The construction of topological error correction codes requires the ability
to fabricate a lattice of physical qubits embedded on a manifold with a
non-trivial topology such that the quantum information is encoded in the global
degrees of freedom (i.e. the topology) of the manifold. However, the
manufacturing of large-scale topological devices will undoubtedly suffer from
fabrication errors---permanent faulty components such as missing physical
qubits or failed entangling gates---introducing permanent defects into the
topology of the lattice and hence significantly reducing the distance of the
code and the quality of the encoded logical qubits. In this work we investigate
how fabrication errors affect the performance of topological codes, using the
surface code as the testbed. A known approach to mitigate defective lattices
involves the use of primitive SWAP gates in a long sequence of syndrome
extraction circuits. Instead, we show that in the presence of fabrication
errors the syndrome can be determined using the supercheck operator approach
and the outcome of the defective gauge stabilizer generators without any
additional computational overhead or the use of SWAP gates. We report numerical
fault-tolerance thresholds in the presence of both qubit fabrication and gate
fabrication errors using a circuit-based noise model and the minimum-weight
perfect matching decoder. Our numerical analysis is most applicable to 2D
chip-based technologies, but the techniques presented here can be readily
extended to other topological architectures. We find that in the presence of 8%
qubit fabrication errors, the surface code can still tolerate a computational
error rate of up to 0.1%.
