  The demand for low power processing is increasing due to mobile and portable
devices. In a processor unit, an adder is an important building block since it
is used in Floating Point Units (FPU) and Arithmetic Logic Units (ALU). Also,
pipeline techniques are used extensively to improve the throughput of the
processing unit. To implement a pipeline requires adding a register at each
sub-stage that result in increasing the latency. Moreover, designing a low
power pipeline adder with low latency has drawn a lot of attention. In a
pipelined architecture that uses Dual Edge Triggered (DET) based registers can
help in reducing the latency since they can capture input data at both clock
edges. However, for high input activity, a DET flip-flop consumes more power
than a Single-Edge Triggered (SET) flip-flop. Moreover, it is required to
replace each Flip-Flop (FF) in the processor with Dual Edge Triggered (DET)
Flip-Flop which will be a considerable area and power overhead. Therefore, it
is desirable to have a switchable DET to SET depending on input activity or
load condition to reduce the dynamic power consumption. In this paper, we are
proposing a new shift register which imitates DET FF based shift register
without the need of special DET FF. The proposed shift register improved the
latency in a 4-bit pipelined adder by two-fold. Additionally, the power delay
product was reduced by 44.16 %.
