  Stability of ultra-low-voltage SRAM bitcells in retention mode is threatened
by two types of uncertainty: process variability and intrinsic noise. While
variability dominates the failure probability, noise-induced bit flips in
weakened bitcells lead to dynamic instability. We study both effects jointly in
a unified SPICE simulation framework. Starting from a synthetic representation
of process variations introduced in a previous work, we identify the cases of
poor noise immunity that require thorough noise analyses. Relying on a rigorous
and systematic methodology, we simulate them in the time domain so as to
emulate a true data retention operation. Short times to failure, unacceptable
for a practical ultra-low-power memory system application, are recorded. The
transient bit-flip mechanism is analysed and a dynamic failure criterion
involving the unstable point is established. We conclude that, beyond static
variability, the dynamic noise inflates defectiveness among SRAM bitcells. We
also discuss the limits of existing analytical formulas from the literature,
which rely on a linear near-equilibrium approximation of the SRAM dynamics to,
inaccurately, predict the mean time to failure.
