  This paper describes a new all-digital technique for calibration of the
mismatches in time-interleaved analog-to-digital converters (TIADCs) to reduce
the circuit area. The proposed technique gives the first order approximation of
the gain mismatches and sample-time mismatches, and employs first order
approximation FIR filter banks to calibrate the sampled signal, which do not
need large number of FIR taps. In the case of a two-channel 12-bit TIADC, the
proposed technique improves SINAD of simulated data from 45dB to 69dB, and
improves SINAD of measured data from 47dB to 53dB, while the number of FIR taps
is only 30. In the case of slight mismatches, 24-bit FIR coefficient is
sufficient to correct 12-bit signals, which makes it easy to implement this
technique in hardware. In addition, this technique is not limited by the number
of sub-ADC channels and can be calculated in parallel in hardware, these
features enable this technique to be versatile and capable of real-time
calibration.
