  Recent advancements in neural network quantisation have yielded remarkable
outcomes, with three-bit networks reaching state-of-the-art full-precision
accuracy in complex tasks. These achievements present valuable opportunities
for accelerating neural networks by computing in reduced precision.
Implementing it on FPGAs can take advantage of bit-level reconfigurability,
which is not available on conventional CPUs and GPUs. Simultaneously, the high
data intensity of neural network processing has inspired computing-in-memory
paradigms, including on FPGA platforms. By programming the effects of trained
model weights as lookup operations in soft logic, the transfer of weight data
from memory units can be avoided, alleviating the memory bottleneck. However,
previous methods face poor scalability - the high logic utilisation limiting
them to small networks/sub-networks of binary models with low accuracy. In this
paper, we introduce Table Lookup Multiply-Accumulate (TLMAC) as a framework to
compile and optimise quantised neural networks for scalable lookup-based
processing. TLMAC clusters and maps unique groups of weights to lookup-based
processing elements, enabling highly parallel computation while taking
advantage of parameter redundancy. Further place and route algorithms are
proposed to reduce LUT utilisation and routing congestion. We demonstrate that
TLMAC significantly improves the scalability of previous related works. Our
efficient logic mapping and high degree of reuse enables entire ImageNet-scale
quantised models with full-precision accuracy to be implemented using
lookup-based computing on one commercially available FPGA.
