  Many cache designs have been proposed to guard against contention-based
side-channel attacks. One well-known type of cache is the randomized remapping
cache. Many randomized remapping caches provide fixed or over protection, which
leads to permanent performance degradation, or they provide flexible
protection, but sacrifice performance against strong contention-based attacks.
To improve the secure cache design, we extend an existing secure cache design,
CEASER-SH cache, and propose the SEA cache. The novel cache configurations in
both caches are logical associativity, which allows the cache line to be placed
not only in its mapped cache set but also in the subsequent cache sets. SEA
cache allows each user or each process to have a different local logical
associativity. Hence, only those users or processes that request extra
protection against contention-based attacks are protected with high logical
associativity. Other users or processes can access the cache with lower latency
and higher performance. Compared to a CEASER-SH cache with logical
associativity of 8, an SEA cache with logical associativity of 1 for normal
protection users and 16 for high protection users has a Cycles Per Instruction
penalty that is about 0.6% less for users under normal protections and provides
better security against contention-based attacks. Based on a 45nm technology
library, and compared to a conventional cache, we estimate the power overhead
is about 20% and the area overhead is 3.4%.
