  This paper presents the design and test results of a Gigabit Cable Receiver
ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel
detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the
CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six
(GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B
via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the
equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two
transmitting channels (TX) that pre-emphasize the signals from lpGBT before
sending them to RD53B through the same cables. No Single-Event Upset (SEU) is
observed in any tested channels of GBCR2 in a 400 MeV proton beam. The
extrapolated bit error rate for the future HL-LHC application is below
8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed
to improve the immunity to single-event-upset by applying the Triple Modular
Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3
have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each
receiver channel of GBCR3 consumes 75% more power than that of GBCR2.
