  There have been ample successful examples of applying Xilinx Vivado's
"function-to-module" high-level synthesis (HLS) where the subject is
algorithmic in nature. In this work, we carried out a design study to assess
the effectiveness of applying Vivado-HLS in structural design. We employed
Vivado-HLS to synthesize C functions corresponding to standalone
network-on-chip (NoC) routers as well as complete multi-endpoint NoCs.
Interestingly, we find that describing a complete NoC comprising router
submodules faces fundamental difficulties not present in describing the routers
as standalone modules. Ultimately, we succeeded in using Vivado-HLS to produce
router and NoC modules that are exact cycle- and bit-accurate replacements of
our reference RTL-based router and NoC modules. Furthermore, the routers and
NoCs resulting from HLS and RTL are comparable in resource utilization and
critical path delay. Our experience subjectively suggests that HLS is able to
simplify the design effort even though much of the structural details had to be
provided in the HLS description through a combination of coding discipline and
explicit pragmas. The C++ source code can be found at
https://github.com/zhipengzhaocmu/HLS_NoC.
