  Even though polar codes were adopted in the latest 5G cellular standard, they
still have the fundamental problem of high decoding latency. Aiming at solving
this problem, a fast simplified successive cancellation (Fast-SSC) decoder
based on the new class of sequence repetition (SR) nodes has been proposed
recently in \cite{sr2020} and has a lower required number of time steps than
other existing Fast-SSC decoders in theory. This paper focuses on the hardware
implementation of this SR node-based fast-SSC (SRFSC) decoder. The
implementation results for a polar code with length 1024 and code rate 1/2 show
that our implementation has a throughput of $505$ Mbps on an Altera Stratix IV
FPGA, which is 17.9% higher with respect to the previous work.
