  In-Memory Computing (IMC) introduces a new paradigm of computation that
offers high efficiency in terms of latency and power consumption for AI
accelerators. However, the non-idealities and defects of emerging technologies
used in advanced IMC can severely degrade the accuracy of inferred Neural
Networks (NN) and lead to malfunctions in safety-critical applications. In this
paper, we investigate an architectural-level mitigation technique based on the
coordinated action of multiple checksum codes, to detect and correct errors at
run-time. This implementation demonstrates higher efficiency in recovering
accuracy across different AI algorithms and technologies compared to more
traditional methods such as Triple Modular Redundancy (TMR). The results show
that several configurations of our implementation recover more than 91% of the
original accuracy with less than half of the area required by TMR and less than
40% of latency overhead.
