  Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been
widely studied as a way to reduce STT-RAM's write energy and latency overheads.
Given a relaxed retention time STT-RAM level one (L1) cache, we analyze the
impacts of dynamic voltage and frequency scaling (DVFS) -- a common
optimization in modern processors -- on STT-RAM L1 cache design. Our analysis
reveals that, apart from the fact that different applications may require
different retention times, the clock frequency, which is typically ignored in
most STT-RAM studies, may also significantly impact applications' retention
time needs. Based on our findings, we propose an asymmetric-retention core
(ARC) design for multicore architectures. ARC features retention time
heterogeneity to specialize STT-RAM retention times to applications' needs. We
also propose a runtime prediction model to determine the best core on which to
run an application, based on the applications' characteristics, their retention
time requirements, and available DVFS settings. Results reveal that the
proposed approach can reduce the average cache energy by 20.19% and overall
processor energy by 7.66%, compared to a homogeneous STT-RAM cache design.
