  On embedded processors that are increasingly equipped with multiple CPU
cores, static hardware partitioning is an established means of consolidating
and isolating workloads onto single chips. This architectural pattern is
suitable for mixed-criticality workloads that need to satisfy both, real-time
and safety requirements, given suitable hardware properties. In this work, we
focus on exploiting contemporary virtualisation mechanisms to achieve freedom
from interference respectively isolation between workloads. Possibilities to
achieve temporal and spatial isolation-while maintaining real-time
capabilities-include statically partitioning resources, avoiding the sharing of
devices, and ascertaining zero interventions of superordinate control
structures. This eliminates overhead due to hardware partitioning, but implies
certain hardware capabilities that are not yet fully implemented in
contemporary standard systems. To address such hardware limitations, the
customisable and configurable RISC-V instruction set architecture offers the
possibility of swift, unrestricted modifications. We present findings on the
current RISC-V specification and its implementations that necessitate
interventions of superordinate control structures. We identify numerous issues
adverse to implementing our goal of achieving zero interventions respectively
zero overhead: On the design level, and especially with regards to handling
interrupts. Based on micro-benchmark measurements, we discuss the implications
of our findings, and argue how they can provide a basis for future extensions
and improvements of the RISC-V architecture.
