  This paper presents an advanced DAG-based algorithm for datapath synthesis
that targets area minimization using logic-level resource sharing. The problem
of identifying common specification logic is formulated using unweighted graph
isomorphism problem, in contrast to a weighted graph isomorphism using AIGs. In
the context of gate-level datapath circuits, our algorithm solves the un-
weighted graph isomorphism problem in linear time. The experiments are
conducted within an industrial synthesis flow that includes the complete
high-level synthesis, logic synthesis and placement and route procedures.
Experimental results show a significant runtime improvements compared to the
existing datapath synthesis algorithms.
