  Radio Access Networks (RAN) workloads are rapidly scaling up in data
processing intensity and throughput as the 5G (and beyond) standards grow in
number of antennas and sub-carriers. Offering flexible Processing Elements
(PEs), efficient memory access, and a productive parallel programming model,
many-core clusters are a well-matched architecture for next-generation
software-defined RANs, but staggering performance requirements demand a high
number of PEs coupled with extreme Power, Performance and Area (PPA)
efficiency. We present the architecture, design, and full physical
implementation of Terapool-SDR, a cluster for Software Defined Radio (SDR) with
1024 latency-tolerant, compact RV32 PEs, sharing a global view of a 4MiB,
4096-banked, L1 memory. We report various feasible configurations of
TeraPool-SDR featuring an ultra-high bandwidth PE-to-L1-memory interconnect,
clocked at 730MHz, 880MHz, and 924MHz (TT/0.80 V/25 {\deg}C) in 12nm FinFET
technology. The TeraPool-SDR cluster achieves high energy efficiency on all SDR
key kernels for 5G RANs: Fast Fourier Transform (93GOPS/W),
Matrix-Multiplication (125GOPS/W), Channel Estimation (96GOPS/W), and Linear
System Inversion (61GOPS/W). For all the kernels, it consumes less than 10W, in
compliance with industry standards.
