  Confronted with the challenge of high performance for applications and the
restriction of hardware resources for field-programmable gate arrays (FPGAs),
partial dynamic reconfiguration (PDR) technology is anticipated to accelerate
the reconfiguration process and alleviate the device shortage. In this paper,
we propose an integrated optimization framework for task partitioning,
scheduling and floorplanning on partially dynamically reconfigurable FPGAs. The
partitions, schedule, and floorplan of the tasks are represented by the
partitioned sequence triple P-ST (PS,QS,RS), where (PS,QS) is a hybrid nested
sequence pair (HNSP) for representing the spatial and temporal partitions, as
well as the floorplan, and RS is the partitioned dynamic configuration order of
the tasks. The floorplanning and scheduling of task modules can be computed
from the partitioned sequence triple P-ST in O(n^2) time. To integrate the
exploration of the scheduling and floorplanning design space, we use a
simulated annealing-based search engine and elaborate a perturbation method,
where a randomly chosen task module is removed from the partition sequence
triple and then inserted back into a proper position selected from all the
(n+1)^3 possible combinations of partitions, schedule and floorplan. The
experimental results demonstrate the efficiency and effectiveness of the
proposed framework.
