  Emerging Persistent Memory technologies (also PM, Non-Volatile DIMMs, Storage
Class Memory or SCM) hold tremendous promise for accelerating popular
data-management applications like in-memory databases. However, programmers now
need to deal with ensuring the atomicity of transactions on Persistent Memory
resident data and maintaining consistency between the order in which processors
perform stores and that in which the updated values become durable.
  The problem is specially challenging when high-performance isolation
mechanisms like Hardware Transactional Memory (HTM) are used for concurrency
control. This work shows how HTM transactions can be ordered correctly and
atomically into PM by the use of a novel software protocol combined with a
Persistent Memory Controller, without requiring changes to processor cache
hardware or HTM protocols. In contrast, previous approaches require significant
changes to existing processor microarchitectures. Our approach, evaluated using
both micro-benchmarks and the STAMP suite compares well with standard
(volatile) HTM transactions. It also yields significant gains in throughput and
latency in comparison with persistent transactional locking.
