  Moore Law states that transistor density will double every two years, which
is sustained until today due to continuous multi-directional innovations, such
as extreme ultraviolet lithography, novel patterning techniques etc., leading
the semiconductor industry towards 3nm node and beyond. For any patterning
scheme, the most important metric to evaluate the quality of printed patterns
is EPE, with overlay being its largest contribution. Overlay errors can lead to
fatal failures of IC devices such as short circuits or broken connections in
terms of P2P electrical contacts. Therefore, it is essential to develop
effective overlay analysis and control techniques to ensure good functionality
of fabricated semiconductor devices. In this work we have used an imec N14 BEOL
process flow using LELE patterning technique to print metal layers with minimum
pitch of 48nm with 193i lithography. FF structures are decomposed into two mask
layers (M1A and M1B) and then the LELE flow is carried out to make the final
patterns. Since a single M1 layer is decomposed into two masks, control of
overlay between the two masks is critical. The goal of this work is of two-fold
as, (a) to quantify the impact of overlay on capacitance and (b) to see if we
can predict the final capacitance measurements with selected machine learning
models at an early stage. To do so, scatterometry spectra are collected on
these electrical test structures at (a)post litho, (b)post TiN hardmask etch,
and (c)post Cu plating and CMP. Critical Dimension and overlay measurements for
line-space pattern are done with SEM post litho, post etch and post Cu CMP.
Various machine learning models are applied to do the capacitance prediction
with multiple metrology inputs at different steps of wafer processing. Finally,
we demonstrate that by using appropriate machine learning models we are able to
do better prediction of electrical results.
