  Field Programmable Gate Arrays(FPGA) exceed the computing power of software
based implementations by breaking the paradigm of sequential execution and
accomplishing more per clock cycle by enabling hardware level parallelization
at an architectural level. Introducing parallel architectures for a
computationally intensive algorithm like Rapidly Exploring Random Trees(RRT)
will result in an exploration that is fast, dense and uniform. Through a cost
function delineated in later sections, FPGA based combinatorial architecture
delivers superlative speed-up but consumes very high power while hierarchical
architecture delivers relatively lower speed-up with acceptable power
consumption levels. To combine the qualities of both, a hybrid architecture,
that encompasses both combinatorial and hierarchical architecture, is designed.
To determine the number of RRT nodes to be allotted to the combinatorial and
hierarchical blocks of the hybrid architecture, a cost function, comprised of
fundamentally inversely related speed-up and power parameters, is formulated.
This maximization of cost function, with its associated constraints,is then
mathematically solved using a modified branch and bound, that leads to optimal
allocation of RRT modules to both blocks. It is observed that this hybrid
architecture delivers the highest performance-per-watt out of the three
architectures for differential, quad-copter and fixed wing kinematics.
