  Adiabatic Quantum-Flux-Parametron (AQFP) logic is a promising emerging device
technology that promises six orders of magnitude lower power than CMOS.
However, AQFP is challenged by operation at only ultra-low temperatures, has
high latency and area, and requires a complex clocking scheme. In particular,
every logic gate, buffer, and splitter must be clocked and each pair of
connected clocked gates requires overlapping alternating current (AC) clock
signals. In particular, clocked buffers need to be used to balance
re-convergent logic paths, a problem that is exacerbated by every multi-node
fanout needing a tree of clocked splitters. To reduce circuit area many works
have proposed buffer and splitter insertion optimization algorithms and recent
works have demonstrated a phase-skipping clocking scheme that reduces latency
and area. This paper proposes the first algorithm to optimize buffer and
splitter insertion for circuits that adopt phase-skipping and demonstrate the
resulting performance improvements for a suite of AQFP benchmark circuits.
