  In this work novel results concerning Network-on-Chip-based turbo decoder
architectures are presented. Stemming from previous publications, this work
concentrates first on improving the throughput by exploiting adaptive-bandwidth
reduction techniques. This technique shows in the best case an improvement of
more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders
require higher area than binary ones. This characteristic has the negative
effect of increasing the data width of the network nodes. Thus, the second
contribution of this work is to reduce the network complexity to support
doublebinary codes, by exploiting bit-level and pseudo-floating-point
representation of the extrinsic information. These two techniques allow for an
area reduction of up to more than the 40% with a performance degradation of
about 0.2 dB.
