  Bayesian neural networks offer better estimates of model uncertainty compared
to frequentist networks. However, inference involving Bayesian models requires
multiple instantiations or sampling of the network parameters, requiring
significant computational resources. Compared to traditional deep learning
networks, spiking neural networks (SNNs) have the potential to reduce
computational area and power, thanks to their event-driven and spike-based
computational framework. Most works in literature either address frequentist
SNN models or non-spiking Bayesian neural networks. In this work, we
demonstrate an optimization framework for developing and implementing efficient
Bayesian SNNs in hardware by additionally restricting network weights to be
binary-valued to further decrease power and area consumption. We demonstrate
accuracies comparable to Bayesian binary networks with full-precision Bernoulli
parameters, while requiring up to $25\times$ less spikes than equivalent binary
SNN implementations. We show the feasibility of the design by mapping it onto
Zynq-7000, a lightweight SoC, and achieve a $6.5 \times$ improvement in
GOPS/DSP while utilizing up to 30 times less power compared to the
state-of-the-art.
