  Neuromorphic computing describes the use of VLSI systems to mimic
neuro-biological architectures and is also looked at as a promising alternative
to the traditional von Neumann architecture. Any new computing architecture
would need a system that can perform floating-point arithmetic. In this paper,
we describe a neuromorphic system that performs IEEE 754-compliant
floating-point multiplication. The complex process of multiplication is divided
into smaller sub-tasks performed by components Exponent Adder, Bias Subtractor,
Mantissa Multiplier and Sign OF/UF. We study the effect of the number of
neurons per bit on accuracy and bit error rate, and estimate the optimal number
of neurons needed for each component.
