  In sub-10nm FinFETs, Line-edge-roughness (LER) and metal-gate granularity
(MGG) are the two most dominant sources of variability and are mostly modeled
semi-empirically. In this work, compact models of LER and MGG are used. We show
an accurate process-induced variability (PIV) aware compact model-based circuit
performance estimation for Design-Technology Co-optimization (DTCO). This work
is carried out using an experimentally validated BSIM-CMG model on a 7nm FinFET
node. First, we have shown performance bench-marking of LER and MGG models with
the state-of-the-art and shown {\textbackslash}4x({\textbackslash}2.3x)
accuracy improvement for NMOS(PMOS) in the estimation of device figure of
merits (DFoMs). Second, RO and SRAM circuits performance estimation is carried
out for LER and MGG variability. Further, {\textbackslash}22\% more optimistic
estimate of ({\sigma}/{\mu})\textsubscript{SHM} (Static Hold Margin) compared
to the state-of-the-art model with V\textsubscript{DD} variation is shown.
Finally, we demonstrate our improved DFoMs accuracy translated to more accurate
circuits figure of merits (CFoMs) performance estimation. For worst-case SHM
<EMAIL_ADDRESS>V) compared to state-of-the-art,
dynamic(standby) power reduction by {\textbackslash}73\%({\textbackslash}61\%)
is shown. Thus, our enhanced variability model accuracy enables more credible
DTCO with significantly better performance estimates.
