  The Network on Chip (NoC) paradigm is rapidly replacing bus based System on
Chip (SoC) designs due to their inherent disadvantages such as non-scalability,
saturation and congestion. Currently very few tools are available for the
simulation and evaluation of on-chip architectures. This study proposes a
generic object oriented model for performance evaluation of on-chip
interconnect architectures and algorithms. The generic nature of the proposed
model can help the researchers in evaluation of any kind of on-chip switching
networks. The model was applied on 2D-Mesh and 2D-Diagonal-Mesh on-chip
switching networks for verification and selection of best out of both the
analyzed architectures. The results show the superiority of 2D-Diagonal-Mesh
over 2D-Mesh in terms of average packet delay.
