  The semiconductor industry is reaching a fascinating confluence in several
evolutionary trends that will likely lead to a number of revolutionary changes
in the design, implementation, scaling, and the use of computer systems.
However, recently Moore's law has come to a stand-still since device scaling
beyond 65 nm is not practical. 2D integration has problems like memory latency,
power dissipation, and large foot-print. 3D technology comes as a solution to
the problems posed by 2D integration. The utilization of 3D is limited by the
problem of temperature crisis. It is important to develop an accurate power
profile extraction methodology to design 3D structure. In this paper, design of
3D integration of memory is considered and hence the static power dissipation
of the memory cell is analysed in transistor level and is used to accurately
model the inter-layer thermal effects for 3D memory stack. Subsequently,
packaging of the chip is considered and modelled using an architecture level
simulator. This modelling is intended to analyse the thermal effects of 3D
memory, its reliability and lifetime of the chip, with greater accuracy.
