  Temporal Neural Networks (TNNs) use time as a resource to represent and
process information, mimicking the behavior of the mammalian neocortex. This
work focuses on implementing TNNs using off-the-shelf digital CMOS technology.
A microarchitecture framework is introduced with a hierarchy of building blocks
including: multi-neuron columns, multi-column layers, and multi-layer TNNs. We
present the direct CMOS gate-level implementation of the multi-neuron column
model as the key building block for TNNs. Post-synthesis results are obtained
using Synopsys tools and the 45 nm CMOS standard cell library. The TNN
microarchitecture framework is embodied in a set of characteristic equations
for assessing the total gate count, die area, compute time, and power
consumption for any TNN design. We develop a multi-layer TNN prototype of 32M
gates. In 7 nm CMOS process, it consumes only 1.54 mm^2 die area and 7.26 mW
power and can process 28x28 images at 107M FPS (9.34 ns per image). We evaluate
the prototype's performance and complexity relative to a recent
state-of-the-art TNN model.
