  The miniaturization of transistors down to 5nm and beyond, plus the
increasing complexity of integrated circuits, significantly aggravate short
channel effects, and demand analysis and optimization of more design corners
and modes. Simulators need to model output variables related to circuit timing,
power, noise, etc., which exhibit nonlinear behavior. The existing simulation
and sign-off tools, based on a combination of closed-form expressions and
lookup tables are either inaccurate or slow, when dealing with circuits with
more than billions of transistors. In this work, we present CSM-NN, a scalable
simulation framework with optimized neural network structures and processing
algorithms. CSM-NN is aimed at optimizing the simulation time by accounting for
the latency of the required memory query and computation, given the underlying
CPU and GPU parallel processing capabilities. Experimental results show that
CSM-NN reduces the simulation time by up to $6\times$ compared to a
state-of-the-art current source model based simulator running on a CPU. This
speedup improves by up to $15\times$ when running on a GPU. CSM-NN also
provides high accuracy levels, with less than $2\%$ error, compared to HSPICE.
