  Subsequence Dynamic Time Warping (sDTW) is the metric of choice when
performing many sequence matching and alignment tasks. While sDTW is flexible
and accurate, it is neither simple nor fast to compute; significant research
effort has been spent devising parallel implementations on the GPU that
leverage efficient memory access and computation patterns, as well as features
offered by specific vendors and architectures (notably NVIDIA's). We present an
implementation of sDTW on AMD hardware using HIP and ROCm. Our implementation
employs well-known parallel patterns, as well as lower-level features offered
by ROCm. We use shuffling for intra-wavefront communication and shared memory
to transfer data between consecutive wavefronts. By constraining the input data
to batches of 512 queries of length 2,000, we optimized for peak performance
the width of reference elements operated on by a single thread.
