  Since hardware oftentimes serves as the root of trust in our modern
interconnected world, malicious hardware manipulations constitute a ubiquitous
threat in the context of the Internet of Things (IoT). Hardware reverse
engineering is a prevalent technique to detect such manipulations.
  Over the last years, an active research community has significantly advanced
the field of hardware reverse engineering. Notably, many open research
questions regarding the extraction of functionally correct netlists from Field
Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits
(ASICs) have been tackled. In order to facilitate further analysis of recovered
netlists, a software framework is required, serving as the foundation for
specialized algorithms. Currently, no such framework is publicly available.
  Therefore, we provide the first open-source gate-library agnostic framework
for gate-level netlist analysis. In this positional paper, we demonstrate the
workflow of our modular framework HAL on the basis of two case studies and
provide profound insights on its technical foundations.
