  In high energy physics experiments (HEP), high speed and fault resilient data
communication is needed between detectors/sensors and the host PC. Transient
faults can occur in the communication hardware due to various external effects
like presence of charged particles, noise in the environment or radiation
effects in HEP experiments and that leads to single/multiple bit error. In
order to keep the communication system functional in such a radiation
environment where direct intervention of human is not possible, a high speed
data acquisition (DAQ) architecture is necessary which supports error recovery.
This design presents an efficient implementation of field programmable gate
array (FPGA) based high speed DAQ system with optical communication link
supported by multi-bit error correcting model. The design has been implemented
on Xilinx Kintex-7 board and is tested for board to board communication as well
as for PC communication using PCI (Peripheral Component Interconnect express).
Data communication speed up to 4.8 Gbps has been achieved in board to board and
board to PC communication and estimation of resource utilization and critical
path delay are also measured.
