  Spin Transfer Torque RAM (STTRAM) is a promising candidate for Last Level
Cache (LLC) due to high endurance, high density and low leakage. One of the
major disadvantages of STTRAM is high write latency and write current.
Additionally, the latency and current depends on the polarity of the data being
written. These features introduce major security vulnerabilities and expose the
cache memory to side channel attacks. In this paper we propose a novel side
channel attack model where the adversary can monitor the supply current of the
memory array to partially identify the sensitive cache data that is being read
or written. We propose several low cost solutions such as short retention
STTRAM, 1-bit parity, multi-bit random write and constant current write driver
to mitigate the attack. 1-bit parity reduces the number of distinct write
current states by 30% for 32-bit word and the current signature is further
obfuscated by multi-bit random writes. The constant current write makes it more
challenging for the attacker to extract the entire word using a single supply
current signature.
