  One of the most critical aspects of integrating loosely-coupled accelerators
in heterogeneous SoC architectures is orchestrating their interactions with the
memory hierarchy, especially in terms of navigating the various cache-coherence
options: from accelerators accessing off-chip memory directly, bypassing the
cache hierarchy, to accelerators having their own private cache. By running
real-size applications on FPGA-based prototypes of many-accelerator multi-core
SoCs, we show that the best cache-coherence mode for a given accelerator varies
at runtime, depending on the accelerator's characteristics, the workload size,
and the overall SoC status.
  Cohmeleon applies reinforcement learning to select the best coherence mode
for each accelerator dynamically at runtime, as opposed to statically at design
time. It makes these selections adaptively, by continuously observing the
system and measuring its performance. Cohmeleon is accelerator-agnostic,
architecture-independent, and it requires minimal hardware support. Cohmeleon
is also transparent to application programmers and has a negligible software
overhead. FPGA-based experiments show that our runtime approach offers, on
average, a 38% speedup with a 66% reduction of off-chip memory accesses
compared to state-of-the-art design-time approaches. Moreover, it can match
runtime solutions that are manually tuned for the target architecture.
