  This research work focuses on the design of a high-resolution fast Fourier
transform (FFT) /inverse fast Fourier transform (IFFT) processors for
constraints analysis purpose. Amongst the major setbacks associated with such
high resolution, FFT processors are the high power consumption resulting from
the structural complexity and computational inefficiency of floating-point
calculations. As such, a parallel pipelined architecture was proposed to
statically scale the resolution of the processor to suite adequate trade-off
constraints. The quantization was applied to provide an approximation to
address the finite word-length constraints of digital signal processing (DSP).
An optimum operating mode was proposed, based on the
signal-to-quantization-noise ratio (SQNR) as well as the statistical theory of
quantization, to minimize the tradeoff issues associated with selecting the
most application-efficient floating-point processing capability in contrast to
their resolution quality.
