  Data logging at an upgraded KEKB accelerator or the J-PARC facility,
currently under commission, requires a high density data acquisition platform
with integrated data reduction CPUs. To follow market trends, we have developed
a DAQ platform based on the PCI bus, a choice which permits a fast DAQ and a
long expected lifetime of the system. The platform is a 9U-VME motherboard
consisting of four slots for signal digitization modules, readout FIFOs for
data buffering, and three PMC slots, on one of which resides a data reduction
CPU. We have performed long term and thermal stability tests. The readout speed
on the platform has been measured up to 125 MB/s in DMA mode.
