  We investigate an approach that uses low-level analysis and the
execution-cache-memory (ECM) performance model in combination with tuning of
hardware parameters to lower energy requirements of memory-bound applications.
The ECM model is extended appropriately to deal with software optimizations
such as non-temporal stores. Using incremental steps and the ECM model, we
analytically quantify the impact of various single-core optimizations and
pinpoint microarchitectural improvements that are relevant to energy
consumption. Using a 2D Jacobi solver as example that can serve as a blueprint
for other memory-bound applications, we evaluate our approach on the four most
recent Intel Xeon E5 processors (Sandy Bridge-EP, Ivy Bridge-EP, Haswell-EP,
and Broadwell-EP). We find that chip energy consumption can be reduced in the
range of 2.0-2.4$\times$ on the examined processors.
