  Enabling high energy efficiency is crucial for embedded implementations of
deep learning. Several studies have shown that the DRAM-based off-chip memory
accesses are one of the most energy-consuming operations in deep neural network
(DNN) accelerators, and thereby limit the designs from achieving efficiency
gains at the full potential. DRAM access energy varies depending upon the
number of accesses required as well as the energy consumed per-access.
Therefore, searching for a solution towards the minimum DRAM access energy is
an important optimization problem. Towards this, we propose the ROMANet
methodology that aims at reducing the number of memory accesses, by searching
for the appropriate data partitioning and scheduling for each layer of a
network using a design space exploration, based on the knowledge of the
available on-chip memory and the data reuse factors. Moreover, ROMANet also
targets decreasing the number of DRAM row buffer conflicts and misses, by
exploiting the DRAM multi-bank burst feature to improve the energy-per-access.
Besides providing the energy benefits, our proposed DRAM data mapping also
results in an increased effective DRAM throughput, which is useful for
latency-constraint scenarios. Our experimental results show that the ROMANet
saves DRAM access energy by 12% for the AlexNet, by 36% for the VGG-16, and by
46% for the MobileNet, while also improving the DRAM throughput by 10%, as
compared to the state-of-the-art.
