  Automatic transistor sizing in circuit design continues to be a formidable
challenge. Despite that Bayesian optimization (BO) has achieved significant
success, it is circuit-specific, limiting the accumulation and transfer of
design knowledge for broader applications. This paper proposes (1) efficient
automatic kernel construction, (2) the first transfer learning across different
circuits and technology nodes for BO, and (3) a selective transfer learning
scheme to ensure only useful knowledge is utilized. These three novel
components are integrated into BO with Multi-objective Acquisition Ensemble
(MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver
state-of-the-art performance: up to 2x simulation reduction and 1.2x design
improvement over the baselines.
