  Reconfigurable packet processing pipelines have emerged as a common building
block for offloading fast and efficient packet processing to programmable
switches and SmartNICs. However, designing or extending such architectures is
complex, laborious, and resource intensive, due to the large design space
coupled with the need for building architecture-specific compilers and RTL
implementations before any evaluation is feasible.
  In this paper, we present Kugelblitz, a framework for rapidly designing,
implementing and evaluating reconfigurable packet processing pipeline
architectures. Kugelblitz comprises domain specific abstractions for separately
representing pipeline architectures and protocol processing programs, a
compiler for automatically mapping programs to specific architectures, and a
hardware generator outputting complete RTL implementations for specific
pipeline architectures. Kugelblitz enables meaningful full-system evaluation
including chip area and timing from VLSI synthesis of the generated RTL, and
end-to-end system benchmarks running real application workloads in full system
simulation. In our evaluation, we demonstrate that Kugelblitz generates
realistic and efficient RTL implementations, scales to large pipelines, enables
fast design exploration, and provides meaningful application offload
performance results.
