  In this paper, we report an encoding and decoding method for
irregular-quasic-cyclic low-density parity-check (IR-QC-LDPC) codes with multi
rates. The algorithm is applicable to parity-check matrices which have
dual-diagonal parity structure. The decoding adopts normalized min-sum
algorithm(NMSA). The whole verification of encoding and decoding algorithm are
simulated with MATLAB, if initial bit error ratio is 6% , the code rate of 2/3
is selected, and if the initial bit error ratio is 1.04%, the code rate of 5/6
is selected. We migrate the algorithm from MATLAB to Field Program Gate
Array(FPGA) and implement this algorithm based on FPGA. Based on FPGA the
throughput of encoding is 183.36Mbps while the average decoding throughput is
27.85Mbps with the initial bit error ratio is 6%.
