  Switches today provide a small set of scheduling algorithms. While we can
tweak scheduling parameters, we cannot modify algorithmic logic, or add a
completely new algorithm, after the switch has been designed. This paper
presents a design for a programmable packet scheduler, which allows scheduling
algorithms---potentially algorithms that are unknown today---to be programmed
into a switch without requiring hardware redesign.
  Our design builds on the observation that scheduling algorithms make two
decisions: in what order to schedule packets and when to schedule them.
Further, in many scheduling algorithms these decisions can be made when packets
are enqueued. We leverage this observation to build a programmable scheduler
using a single abstraction: the push-in first-out queue (PIFO), a priority
queue that maintains the scheduling order and time for such algorithms.
  We show that a programmable scheduler using PIFOs lets us program a wide
variety of scheduling algorithms. We present a detailed hardware design for
this scheduler for a 64-port 10 Gbit/s shared-memory switch with <4% chip area
overhead on a 16-nm standard-cell library. Our design lets us program many
sophisticated algorithms, such as a 5-level hierarchical scheduler with
programmable scheduling algorithms at each level.
