  In this paper C-Slow Retiming (CSR) on RTL is discussed. CSR multiplies the
functionality of cores by adding the same number of registers into each path.
The technique is ideal for FPGAs with their already existing registers.
Previously publications are limited to adding registers on netlist level, which
generates a lot of system verification problems and which is assumed to be the
major drawback to use this technology in the modern multicore times. The paper
shows how CSR can efficiently be done with timing driven automatic RTL
modification. The methodology provided with this paper can be used as guidance
for using CSR in high level synthesis (HLS). The paper shows the results of a
CSR-ed complex RISC core on RTL implemented on FPGAs.
