  Partitioning is a well studied research problem in the area of VLSI physical
design automation. In this problem, input is an integrated circuit and output
is a set of almost equal disjoint blocks. The main objective of partitioning is
to assign the components of circuit to blocks in order to minimize the numbers
of inter-block connections. A partitioning algorithm using hypergraph was
proposed by Fiduccia and Mattheyses with linear time complexity which has been
popularly known as FM algorithm. Most of the hypergraph based partitioning
algorithms proposed in the literature are variants of FM algorithm. In this
paper, we have proposed a novel variant of FM algorithm by using pair wise
swapping technique. We have performed a comparative experimental study of FM
algorithm and our proposed algorithm using two dataset such as ISPD98 and
ISPD99. Experimental results show that performance of our proposed algorithm is
better than the FM algorithm using the above dataset.
