  We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of
the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC
operation. This ASIC is based on a previously submitted demonstrator ASIC
designed for timing performance evaluation, and includes all features necessary
for the various operation modes, as well as the migration to the TSMC 130 nm
CMOS technology. We present the TDC design with the emphasis on added features
and performance optimization. Tests of the timing performance demonstrate that
this ASIC meets the design specifications. The TDC has a bin size of about 780
ps, and a timing bin variations within 40 ps for all 24 channels with leading
and trailing edge digitization, while the power consumption has been limited to
250 mW, corresponding to a consumption of about 5.2 mW per edge measurement.
