  Sorting is needed in many application domains. The data is read from memory
and sent to a general purpose processor or application specific hardware for
sorting. The sorted data is then written back to the memory. Reading/writing
data from/to memory and transferring data between memory and processing unit
incur a large latency and energy overhead. In this work, we develop, to the
best of our knowledge, the first architectures for in-memory sorting of data.
We propose two architectures. The first architecture is applicable to the
conventional format of representing data, weighted binary radix. The second
architecture is proposed for the developing unary processing systems where data
is encoded as uniform unary bitstreams. The two architectures have different
advantages and disadvantages, making one or the other more suitable for a
specific application. However, the common property of both is a significant
reduction in the processing time compared to prior sorting designs. Our
evaluations show on average 37x and 138x energy reduction for binary and unary
designs, respectively, as compared to conventional CMOS off-memory sorting
systems.
