  The open-source RISC-V ISA is gaining traction, both in industry and
academia. The ISA is designed to scale from micro-controllers to server-class
processors. Furthermore, openness promotes the availability of various
open-source and commercial implementations. Our main contribution in this work
is a thorough power, performance, and efficiency analysis of the RISC-V ISA
targeting baseline "application class" functionality, i.e. supporting the Linux
OS and its application environment based on our open-source single-issue
in-order implementation of the 64 bit ISA variant (RV64GC) called Ariane. Our
analysis is based on a detailed power and efficiency analysis of the RISC-V ISA
extracted from silicon measurements and calibrated simulation of an Ariane
instance (RV64IMC) taped-out in GlobalFoundries 22 FDX technology. Ariane runs
at up to 1.7 GHz and achieves up to 40 Gop/sW peak efficiency. We give insight
into the interplay between functionality required for application-class
execution (e.g. virtual memory, caches, multiple modes of privileged operation)
and energy cost. Our analysis indicates that ISA heterogeneity and simpler
cores with a few critical instruction extensions (e.g. packed SIMD) can
significantly boost a RISC-V core's compute energy efficiency.
