  A new generation of manycore processors is on the rise that offers dozens and
more cores on a chip and, in a sense, fuses host processor and accelerator. In
this paper we target the efficient training of generalized linear models on
these machines. We propose a novel approach for achieving parallelism which we
call Heterogeneous Tasks on Homogeneous Cores (HTHC). It divides the problem
into multiple fundamentally different tasks, which themselves are parallelized.
For evaluation, we design a detailed, architecture-cognizant implementation of
our scheme on a recent 72-core Knights Landing processor that is adaptive to
the cache, memory, and core structure. Our library efficiently supports dense
and sparse datasets as well as 4-bit quantized data for further possible gains
in performance. We show benchmarks for Lasso and SVM with different data sets
against straightforward parallel implementations and prior software. In
particular, for Lasso on dense data, we improve the state-of-the-art by an
order of magnitude.
