  Deep convolutional neural networks have dominated the pattern recognition
scene by providing much more accurate solutions in computer vision problems
such as object recognition and object detection. Most of these solutions come
at a huge computational cost, requiring billions of multiply-accumulate
operations and, thus, making their use quite challenging in real-time
applications that run on embedded mobile (resource-power constrained) hardware.
This work presents the architecture, the high-level synthesis design, and the
implementation of SqueezeJet, an FPGA accelerator for the inference phase of
the SqueezeNet DCNN architecture, which is designed specifically for use in
embedded systems. Results show that SqueezeJet can achieve 15.16 times speed-up
compared to the software implementation of SqueezeNet running on an embedded
mobile processor with less than 1% drop in top-5 accuracy.
