  With the prevalence of deep learning (DL) in many applications, researchers
are investigating different ways of optimizing FPGA architecture and CAD to
achieve better quality-of-results (QoR) on DL-based workloads. In this
optimization process, benchmark circuits are an essential component; the QoR
achieved on a set of benchmarks is the main driver for architecture and CAD
design choices. However, current academic benchmark suites are inadequate, as
they do not capture any designs from the DL domain. This work presents a new
suite of DL acceleration benchmark circuits for FPGA architecture and CAD
research, called Koios. This suite of 19 circuits covers a wide variety of
accelerated neural networks, design sizes, implementation styles, abstraction
levels, and numerical precisions. These designs are larger, more data parallel,
more heterogeneous, more deeply pipelined, and utilize more FPGA architectural
features compared to existing open-source benchmarks. This enables researchers
to pin-point architectural inefficiencies for this class of workloads and
optimize CAD tools on more realistic benchmarks that stress the CAD algorithms
in different ways. In this paper, we describe the designs in our benchmark
suite, present results of running them through the Verilog-to-Routing (VTR)
flow using a recent FPGA architecture model, and identify key insights from the
resulting metrics. On average, our benchmarks have 3.7x more netlist
primitives, 1.8x and 4.7x higher DSP and BRAM densities, and 1.7x higher
frequency with 1.9x more near-critical paths compared to the widely-used VTR
suite. Finally, we present two example case studies showing how architectural
exploration for DL-optimized FPGAs can be performed using our new benchmark
suite.
