  Our recent work (Ayral et al., 2020 IEEE Computer Society Annual Symposium on
VLSI (ISVLSI)) showed the first implementation of the Quantum Divide and
Compute (QDC) method, which allows to break quantum circuits into smaller
fragments with fewer qubits and shallower depth. QDC can thus deal with the
limited number of qubits and short coherence times of noisy, intermediate-scale
quantum processors. This article investigates the impact of different noise
sources -- readout error, gate error and decoherence -- on the success
probability of the QDC procedure. We perform detailed noise modeling on the
Atos Quantum Learning Machine, allowing us to understand tradeoffs and
formulate recommendations about which hardware noise sources should be
preferentially optimized. We describe in detail the noise models we used to
reproduce experimental runs on IBM's Johannesburg processor. This work also
includes a detailed derivation of the equations used in the QDC procedure to
compute the output distribution of the original quantum circuit from the output
distribution of its fragments. Finally, we analyze the computational complexity
of the QDC method for the circuit under study via tensor-network
considerations, and elaborate on the relation the QDC method with
tensor-network simulation methods.
