  One of the largest obstacles to building a quantum computer is gate error,
where the physical evolution of the state of a qubit or group of qubits during
a gate operation does not match the intended unitary transformation. Gate error
stems from a combination of control errors and random single qubit errors from
interaction with the environment. While great strides have been made in
mitigating control errors, intrinsic qubit error remains a serious problem that
sets the primary limit for gate fidelity in modern superconducting qubit
architectures. Simultaneously, recent developments of small error-corrected
logical qubit devices promise significant increases in logical state lifetime,
but translating those improvements into increases in gate fidelity is a complex
challenge. In this Letter, we propose a new formalism for implementing gates on
and between small logical qubit devices which inherit the parent device's
tolerance to single qubit errors which occur at any time before or during the
gate. Using a standard phenomenological noise model for superconducting qubits,
we demonstrate a universal one- and two-qubit gate set with error rates an
order of magnitude lower than those for equivalent operations on single qubits
or pairs of qubits, running for the same total duration. The effective logical
gate error rate in these models displays superlinear error reduction with
linear increases in single qubit lifetime, proving that passive error
correction is capable of increasing gate fidelity. These developments further
suggest that incorporating small logical qubits into a measurement based code
could substantially improve code performance.
