  State-of-the-art in-memory computation has recently emerged as the most
promising solution to overcome design challenges related to data movement
inside current computing systems. One of the approaches to performing in-memory
computation is based on the analog behavior of the data stored inside the
memory cell. These approaches proposed various system architectures for that.
In this paper, we investigated the effect of threshold voltage suppression on
the access transistors of the In-SRAM multiplication and accumulation (MAC)
accelerator to improve and enhance the performance of bit line (bit line bar)
discharge rate that will increase the accuracy of MAC operation. We provide a
comprehensive analytical analysis followed by circuit implementation, including
a Monte-Carlo simulation by a 65nm CMOS technology. We confirmed the efficiency
of our method (SMART) for a four-by-four-bit MAC operation. The proposed
technique improves the accuracy while consuming 0.683 pJ per computation from a
power supply of 1V. Our novel technique presents less than 0.009 standard
deviations for the worst-case incorrect output scenario.
