  ATLAS detector at the LHC will undergo a major Phase-II upgrade for the High
Luminosity LHC. The upgrade affects all major ATLAS systems, including the
Trigger and Data Acquisition systems. As part of the Level-0 Trigger System,
the Global Trigger uses full-granularity calorimeter cells to perform
algorithms, refines the trigger objects and applies topological requirements.
The Global Trigger uses a Global Common Module as the building block of its
design. To achieve a high input and output bandwidth and substantial processing
power, the Global Common Module will host the most advanced FPGAs and optical
modules. In order to evaluate the new generation of optical modules and FPGAs
running at high data rates (up to 28 Gb/s), a Global Trigger Technological
Demonstrator board has been designed and tested. The main hardware blocks of
the board are the Xilinx Virtex Ultrascale+ 9P FPGA and a number of optical
modules, including high-speed Finisar BOA and Samtec FireFly modules. Long-run
link tests have been performed for the Finisar BOA and Samtec FireFly optical
modules running at 25.65 and 27.58 Gb/s respectively. Successful results
demonstrating a good performance of the optical modules when communicating with
the FPGA have been obtained. The paper provides a hardware overview and
measurement results of the Technological Demonstrator.
