  Deep neural networks (DNN) are increasingly being accelerated on
application-specific hardware such as the Google TPU designed especially for
deep learning. Timing speculation is a promising approach to further increase
the energy efficiency of DNN accelerators. Architectural exploration for timing
speculation requires detailed gate-level timing simulations that can be
time-consuming for large DNNs that execute millions of multiply-and-accumulate
(MAC) operations. In this paper we propose FATE, a new methodology for fast and
accurate timing simulations of DNN accelerators like the Google TPU. FATE
proposes two novel ideas: (i) DelayNet, a DNN based timing model for MAC units;
and (ii) a statistical sampling methodology that reduces the number of MAC
operations for which timing simulations are performed. We show that FATE
results in between 8 times-58 times speed-up in timing simulations, while
introducing less than 2% error in classification accuracy estimates. We
demonstrate the use of FATE by comparing to conventional DNN accelerator that
uses 2's complement (2C) arithmetic with an alternative implementation that
uses signed magnitude representations (SMR). We show that that the SMR
implementation provides 18% more energy savings for the same classification
accuracy than 2C, a result that might be of independent interest.
