  There is an extremely high demand for a high speed, low power, low leakage,
and low noise Static Random-Access Memory (SRAM) for high performance cache
memories. The energy efficiency of SRAM is of paramount importance in both high
performance and ultralow-power portable, battery operated electronic systems.
In this article the factors affecting the over-all speed and total energy
consumption of a conventional 6T SRAM cell/array with 6 FETs, particularly
roles of access tran-sistors are analyzed to highlight the needs and directions
for improvement. A hybrid 6T SRAM with two access FETs being replaced by
light-effect transistors (LETs) and the electrical word lines replaced by
optical waveguides (OWGs) is proposed. This hybrid SRAM is analyzed to reveal
its potential in im-provement of the switching speed and thus total energy
con-sumption over the conventional 6T SRAM. Numerical analyses of a prototype
hybrid SRAM array of 64 KB show a factor of 7 and 34 reduction in read delay
and read energy consumption, respectively; and 4 and 6 in write delay and write
energy con-sumption, respectively, when the access FETs are replaced by LETs.
The potential impacts on the peripheral and assist cir-cuits due to this hybrid
structure and application of the LETs there are also briefly discussed.
