  Over the past few decades, network topology design for general purpose,
shared memory multicores has been primarily driven by human experts who use
their insights to arrive at network designs that balance the competing goals of
performance requirements (e.g., latency, bandwidth) and cost constraints (e.g.,
router radix, router counts). On the other hand, there have been automatic NoC
synthesis methods for SoCs to optimize for application-specific communication
and objectives such as resource usage or power. Unfortunately, these techniques
do not lend themselves to the general-purpose context, where directly applying
these previous NoC synthesis techniques in the general-purpose context yields
poor results, even worse than expert-designed networks. We design and develop
an automatic network design methodology - NetSmith - to design networks for
general-purpose, shared memory multicores that comprehensively outperform
expert-designed networks.
  We employ NetSmith in the context of interposer networks for chiplet-based
systems where there has been significant recent work on network topology design
(e.g., Kite, Butter Donut, Double Butterfly). NetSmith generated topologies are
capable of achieving significantly higher throughput (50% to 75% higher) while
also reducing average hop count by 8% to 13.5%) than previous expert-designed
and synthesized networks. Full system simulations using PARSEC benchmarks
demonstrate that the improved network performance translates to improved
application performance with up to 11% mean speedup over previous NoI
topologies.
