  Decision trees are considered one of the most powerful tools for data
classification. Accelerating the decision tree search is crucial for
on-the-edge applications that have limited power and latency budget. In this
paper, we propose a Content Addressable Memory (CAM) Compiler for Decision Tree
(DT) inference acceleration. We propose a novel "adaptive-precision" scheme
that results in a compact implementation and enables an efficient bijective
mapping to Ternary Content Addressable Memories while maintaining high
inference accuracies. In addition, a Resistive-CAM (ReCAM) functional
synthesizer is developed for mapping the decision tree to the ReCAM and
performing functional simulations for energy, latency, and accuracy
evaluations. We study the decision tree accuracy under hardware non-idealities
including device defects, manufacturing variability, and input encoding noise.
We test our framework on various DT datasets including \textit{Give Me Some
Credit}, \textit{Titanic}, and \textit{COVID-19}. Our results reveal up to
{42.4\%} energy savings and up to 17.8x better energy-delay-area product
compared to the state-of-art hardware accelerators, and up to 333 million
decisions per sec for the pipelined implementation.
