  This work presents a SystemC-TLM based simulator for a RISC-V
microcontroller. This simulator is focused on simplicity and easy expandable of
a RISC-V. It is built around a full RISC-V instruction set simulator that
supports full RISC-V ISA and extensions M, A, C, Zicsr and Zifencei. The ISS is
encapsulated in a TLM-2 wrapper that enables it to communicate with any other
TLM-2 compatible module. The simulator also includes a very basic set of
peripherals to enable a complete SoC simulator. The running code can be
compiled with standard tools and using standard C libraries without
modifications. The simulator is able to correctly execute the riscv-compliance
suite. The entire simulator is published as a docker image to ease its
installation and use by developers. A porting of FreeRTOSv10.2.1 for the
simulated SoC is also published.
