  A large semantic gap between the high-level synthesis (HLS) design and the
low-level (on-board or RTL) simulation environment often creates a barrier for
those who are not FPGA experts. Moreover, such low-level simulation takes a
long time to complete. Software-based HLS simulators can help bridge this gap
and accelerate the simulation process; however, we found that the current FPGA
HLS commercial software simulators sometimes produce incorrect results. In
order to solve this correctness issue while maintaining the high speed of a
software-based simulator, this paper proposes a new HLS simulation flow named
FLASH. The main idea behind the proposed flow is to extract the scheduling
information from the HLS tool and automatically construct an equivalent
cycle-accurate simulation model while preserving C semantics. Experimental
results show that FLASH runs three orders of magnitude faster than the RTL
simulation.
