  The efficiency improvement of hardware accelerators such as
single-instruction-multiple-data (SIMD) and coarse-grained reconfigurable
architecture (CGRA) empowers the rapid advancement of AI and machine learning
applications. These streaming applications consist of numerous vector
operations that can be naturally parallelized. Despite the outstanding
achievements of today's hardware accelerators, their potential is limited by
their instruction set design. Traditional instruction sets, designed for
microprocessors and accelerators, focus on computation and pay little attention
to instruction composability and instruction-level cooperation. It leads to a
rigid instruction set that is difficult to extend and significant control
overhead in hardware. This paper presents an instruction set that is composable
in both spatial and temporal sense and suitable for streaming applications. The
proposed instruction set contains significantly fewer instruction types but can
still efficiently implement complex multi-level loop structures, which is
essential for accelerating streaming applications. It is also a
resource-centric instruction set that can be conveniently extended by adding
new hardware resources, thus creating a custom heterogeneous computation
machine. Besides presenting the composable instruction set, we propose a simple
yet efficient instruction scheduling algorithm. We analyzed the scalability of
the scheduling algorithm and compared the efficiency of our compiled programs
against RISC-V programs. The results indicate that our scheduling algorithm
scales linearly, and our instruction set leads to near-optimal execution
latency. The mapped applications on CIS are nearly 10 times faster than the
RISC-V version.
