  This work presents an efficient ASIC implementation of successive
cancellation (SC) decoder for polar codes. SC is a low-complexity depth-first
search decoding algorithm, favorable for beyond-5G applications that require
extremely high throughput and low power. The ASIC implementation of SC in this
work exploits many techniques including pipelining and unrolling to achieve
Tb/s data throughput without compromising power and area metrics. To reduce the
complexity of the implementation, an adaptive log-likelihood ratio (LLR)
quantization scheme is used. This scheme optimizes bit precision of the
internal LLRs within the range of 1-5 bits by considering irregular
polarization and entropy of LLR distribution in SC decoder. The performance
cost of this scheme is less than 0.2 dB when the code block length is 1024 bits
and the payload is 854 bits. Furthermore, some computations in SC take large
space with high degree of parallelization while others take longer time steps.
To optimize these computations and reduce both memory and latency, register
reduction/balancing (R-RB) method is used. The final decoder architecture is
called optimized polar SC (OPSC). The post-placement-routing results at 16nm
FinFet ASIC technology show that OPSC decoder achieves 1.2 Tb/s coded
throughput on 0.79 mm$^2$ area with 0.95 pJ/bit energy efficiency.
