  We present a novel design of a strained topological insulator spin-orbit
torque random access memory (STI-SOTRAM) bit cell comprising a
piezoelectric/magnet (gating)/topological insulator (TI)/magnet (storage)
heterostructure that leverages the TI's high charge-to-spin conversion
efficiency coupled with the piezo-induced strain-based gating mechanism for
low-power in-memory computing. The piezo-induced strain effectively modulates
the conductivity of the topological surface state (TSS) by altering the gating
magnet's magnetization from out-to-in-plane, facilitating the storage magnet's
spin-orbit torque (SOT) switching. Through comprehensive coupled stochastic
Landau-Lifshitz-Gilbert (LLG) simulations, we explore the device dynamics,
anisotropy-stress phase space for switching, and write conditions and
demonstrate a significant reduction in energy dissipation compared to
conventional heavy metal (HM)-based SOT switching. Additionally, we project the
energy consumption for in-memory Boolean operations (AND and OR). Our findings
suggest the promise of the STI-SOTRAM for low-power, high-performance edge
computing.
