  The electromigration (EM)-induced reliability issues in very large scale
integration (VLSI) circuits have attracted increased attention due to the
continuous technology scaling. Traditional EM models often lead to overly
pessimistic prediction incompatible with the shrinking design margin in future
technology nodes. Motivated by the latest success of neural networks in solving
differential equations in physical problems, we propose a novel mesh-free model
to compute EM-induced stress evolution in VLSI circuits. The model utilizes a
specifically crafted space-time physics-informed neural network (STPINN) as the
solver for EM analysis. By coupling the physics-based EM analysis with dynamic
temperature incorporating Joule heating and via effect, we can observe stress
evolution along multi-segment interconnect trees under constant, time-dependent
and space-time-dependent temperature during the void nucleation phase. The
proposed STPINN method obviates the time discretization and meshing required in
conventional numerical stress evolution analysis and offers significant
computational savings. Numerical comparison with competing schemes demonstrates
a 2x ~ 52x speedup with a satisfactory accuracy.
