  Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive
electronics technologies. SFQ systems operate at tens of gigahertz with up to
three orders of magnitude smaller power as compared to CMOS. In conventional
SFQ systems, most gates require clock signal. Each gate should have the fanins
with equal logic depth, necessitating insertion of path-balancing (PB) DFFs,
incurring prohibitive area penalty. Multiphase clocking is the effective method
for reducing the path-balancing overhead at the cost of reduced throughput.
However, existing tools are not directly applicable for technology mapping of
multiphase systems. To overcome this limitation, in this work, we propose a
technology mapping tool for multiphase systems. Our contribution is threefold.
First, we formulate a phase assignment as a Constraint Programming with
Satisfiability (CP-SAT) problem, to determine the phase of each element within
the network. Second, we formulate the path balancing problem as a CP-SAT to
optimize the number of DFFs within an asynchronous datapath. Finally, we
integrate these methods into a technology mapping flow to convert a logic
network into a multiphase SFQ circuit. In our case studies, by using seven
phases, the size of the circuit (expressed as the number of Josephson
junctions) is reduced, on average, by 59.94 % as compared to the dual
(fast-slow) clocking method, while outperforming the state-of-the-art
single-phase SFQ mapping tools.
