  As CMOS nears the end of the projected scaling roadmap, significant effort
has been devoted to the search for new materials and devices that can realize
memory and logic. Spintronics, is one of the promising directions for the
Post-CMOS era. While the potential of spintronic memories is relatively well
known, realizing logic remains an open and critical challenge. All Spin Logic
(ASL) is a recently proposed logic style that realizes Boolean logic using
spin-transfer-torque (STT) devices based on the principle of non-local spin
torque. ASL has advantages such as density, non-volatility, and low operating
voltage. However, it also suffers from drawbacks such as low speed and static
power dissipation. Recent work has shown that, in the context of simple
arithmetic circuits (adders, multipliers), the efficiency of ASL can be greatly
improved using techniques that utilize its unique characteristics. An
evaluation of ASL across a broad range of circuits, considering the known
optimization techniques, is an important next step in determining its
viability. In this work, we propose a systematic methodology for the synthesis
of ASL circuits. Our methodology performs various optimizations that benefit
ASL, such as intra-cycle power gating, stacking of ASL nanomagnets, and
fine-grained logic pipelining. We utilize the proposed methodology to evaluate
the suitability of ASL implementations for a wide range of benchmarks viz.
random combinational and sequential logic, digital signal processing circuits,
and the Leon SPARC3 general-purpose processor. Based on our evaluation, we
identify (i) the large current requirement of nanomagnets at fast switching
speeds, (ii) the static power dissipation in the all-metallic devices, and
(iii) the short spin flip length in interconnects as key bottlenecks that limit
the competitiveness of ASL.
