  Limited memory bandwidth is a critical bottleneck in modern systems.
3D-stacked DRAM enables higher bandwidth by leveraging wider
Through-Silicon-Via (TSV) channels, but today's systems cannot fully exploit
them due to the limited internal bandwidth of DRAM. DRAM reads a whole row
simultaneously from the cell array to a row buffer, but can transfer only a
fraction of the data from the row buffer to peripheral IO circuit, through a
limited and expensive set of wires referred to as global bitlines. In presence
of wider memory channels, the major bottleneck becomes the limited data
transfer capacity through these global bitlines. Our goal in this work is to
enable higher bandwidth in 3D-stacked DRAM without the increased cost of adding
more global bitlines. We instead exploit otherwise-idle resources, such as
global bitlines, already existing within the multiple DRAM layers by accessing
the layers simultaneously. Our architecture, Simultaneous Multi Layer Access
(SMLA), provides higher bandwidth by aggregating the internal bandwidth of
multiple layers and transferring the available data at a higher IO frequency.
  To implement SMLA, simultaneous data transfer from multiple layers through
the same IO TSVs requires coordination between layers to avoid channel
conflict. We first study coordination by static partitioning, which we call
Dedicated-IO, that assigns groups of TSVs to each layer. We then provide a
simple, yet sophisticated mechanism, called Cascaded-IO, which enables
simultaneous access to each layer by time-multiplexing the IOs. By operating at
a frequency proportional to the number of layers, SMLA provides a higher
bandwidth (4X for a four-layer stacked DRAM). Our evaluations show that SMLA
provides significant performance improvement and energy reduction (55%/18% on
average for multi-programmed workloads, respectively) over a baseline
3D-stacked DRAM with very low area overhead.
