  Time measurement plays a crucial rule for the purpose of particle
identification in high energy physical experiments. With the upgrading of
physical goal and the developing of electronics, modern time measurement system
meets the requirement of excellent resolution specification as well as high
integrity. Due to Field Programmable Gate Array (FPGA), FPGA time-to-digital
converter (TDC) becomes one of mature and prominent time measurement methods in
recent years. For correcting time-walk effect caused by leading timing,
time-over-threshold (TOT) measurement should be added in the FPGA TDC. TOT can
be obtained by measuring the interval time of signal leading and trailing edge.
Unfortunately, a traditional TDC can recognize only one kind of signal edge,
the leading or the trailing. Generally, to measure the interval, two TDC
channels can be used at the same time, one for leading, the other for trailing.
However, this method will increase the amount of used FPGA resource and reduce
the TDC's integrity unavoidably. This paper presents one method of TOT
measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measure
can be achieved in only one TDC input channel. The consumed resources and time
resolution can both be guaranteed. Test shows that this TDC can achieve
resolution better than 15 ps for leading edge measurement and 37 ps for TOT
measurement. Furthermore, the TDC measuring dead time is about 2 clock cycles,
which makes it be good for applications of higher physical event rate
