  High sampling speed can be achieved using multiple Analog-to-Digital
Converters (ADCs) based on the Time-Interleaving A/D Conversion (TIADC)
technique. Various types of methods were proposed to correct the mismatch
errors among parallel ADC channels in TIADC systems, which would deteriorate
the system performance. Traditional correction methods based on digital signal
processing have good performance, however often only for input signals limited
in a narrow frequency band. In this paper, we present our recent work on design
of an 8-Gsps 12-bit TIADC system and implementation of real-time mismatch
correction algorithms in FPGA devices, over a broad band of input signal
frequencies. Tests were also conducted to evaluate the systems performance, and
the results indicate that the Effective Number of Bits (ENOB) is enhanced to be
better than 8.5 bits (<800 MHz) and 8 bits from 800 MHz to 1.6 GHz after
correction, almost the same with that of the ADC chip employed.
