  Due to the increasing challenges posed by the relentless rise in the design
complexity of integrated circuits, Boolean Satisfiability (SAT) has emerged as
a robust alternative to structural APTG techniques. However, the high cost of
transforming a circuit testing problem to a Conjunctive Normal Form (CNF)
limits the application of SAT in industrial ATPG scenarios, resulting in a loss
of test coverage. In Order to address this problem, this paper proposes a
conflict-driven structural learning (CDSL) ATPG algorithm firstly, in which the
conflict-driven heuristic methods in modern SAT solver are implemented on the
logic cone of fault propagation and activation directly. The proposed CDSL
algorithm is composed of three parts: (1) According to the implication graph,
various conflict constraints have been learned to prune search space. (2)
Conflict-driven implication and justification have been applied to increase
decision accuracy and solving efficiency. (3) A conflict-based diagnosis method
is further proposed in the case of low coverage debug, leading to making the
aborted faults testable by relaxing or modifying some constraints on primary
inputs. Extensive experimental results on industrial circuits demonstrate the
effectiveness and efficiency of the proposed CDSL algorithm. It is shown that
compared with the SAT-based ATPG, the proposed CDSL can on average decrease
$25.6\%$ aborted faults with $94.51\%$ less run time. With a two-stage
computational flow, it has shown that the proposed CDSL can lead to $46.37\%$
less aborted faults than a one-stage structural algorithm, further with the
$3.19\%$ improvement on fault coverage. In addition, the conflict diagnosis can
lead to $8.89\%$ less aborted faults on average, and $0.271\%$ improvement in
fault coverage rate.
