  Analog-to-digital converters (ADCs) are a major contributor to the power
consumption of multiple-input multiple-output (MIMO) communication systems with
large number of antennas. Use of low resolution ADCs has been proposed as a
means to decrease power consumption in MIMO receivers. However, reducing the
ADC resolution leads to performance loss in terms of achievable transmission
rates. In order to mitigate the rate-loss, the receiver can perform analog
processing of the received signals before quantization. Prior works consider
one-shot analog processing where at each channel-use, analog linear
combinations of the received signals are fed to a set of one-bit threshold
ADCs. In this paper, a receiver architecture is proposed which uses a sequence
of delay elements to allow for blockwise linear combining of the received
analog signals. In the high signal to noise ratio regime, it is shown that the
proposed architecture achieves the maximum achievable transmission rate given a
fixed number of one-bit ADCs. Furthermore, a tradeoff between transmission rate
and the number of delay elements is identified which quantifies the increase in
maximum achievable rate as the number of delay elements is increased.
