  Field Programmable Gate Arrays (FPGAs) are more prone to be affected by
transient faults in presence of radiation and other environmental hazards
compared to Application Specific Integrated Circuits (ASICs). Hence, error
mitigation and recovery techniques are absolutely necessary to protect the FPGA
hardware from soft errors arising due to such transient faults. In this paper,
a new efficient multi-bit error correcting method for FPGAs is proposed using
adaptive cross parity check (ACPC) code. ACPC is easy to implement and the
needed decoding circuit is also simple. In the proposed scheme total
configuration memory is partitioned into two parts. One part will contain ACPC
hardware, which is static and assumed to be unaffected by any kind of errors.
Other portion will store the binary file for logic, which is to be protected
from transient error and is assumed to be dynamically reconfigurable (Partial
reconfigurable area). Binary file from the secondary memory passes through ACPC
hardware and the bits for forward error correction (FEC) field are calculated
before entering into the reconfigurable portion. In the runtime scenario, the
data from the dynamically reconfigurable portion of the configuration memory
will be read back and passed through the ACPC hardware. The ACPC hardware will
correct the errors before the data enters into the dynamic configuration
memory. We propose a first of its kind methodology for novel transient fault
correction using ACPC code for FPGAs. To validate the design we have tested the
proposed methodology with Kintex FPGA. We have also measured different
parameters like critical path, power consumption, overhead resource and error
correction efficiency to estimate the performance of our proposed method.
