  A common approach to protect confidential information is to use a stream
cipher which combines plain text bits with a pseudo-random bit sequence. Among
the existing stream ciphers, Non-Linear Feedback Shift Register (NLFSR)-based
ones provide the best trade-off between cryptographic security and hardware
efficiency. In this paper, we show how to further improve the hardware
efficiency of Grain stream cipher. By transforming the NLFSR of Grain from its
original Fibonacci configuration to the Galois configuration and by introducing
a clock division block, we double the throughput of the 80 and 128-bit key
1bit/cycle architectures of Grain with no area penalty.
