  With technology scaling, lower supply voltages, and higher operating
frequencies clock distribution networks become more and more vulnerable to
transients faults. These faults can cause circuit-wide effects and thus,
significantly contribute to the functional failure rate of the circuit. This
paper proposes a methodology to analyse how the functional behaviour is
affected by Single-Event Transients in the clock distribution network. The
approach is based on logic-level simulation and thus, only uses the
register-transfer level description of a design. Therefore, a fault model is
proposed which implements the main effects due to radiation-induced transients
in the clock network. This fault model enables the computation of the
functional failure rate caused by Single-Event Transients for each individual
clock buffer, as well as the complete network. Further, it allows the
identification of the most vulnerable flip-flops related to Single-Event
Transients in the clock network.
  The proposed methodology is applied in a practical example and a fault
injection campaign is performed. In order to evaluate the impact of
Single-Event Transients in clock distribution networks, the obtained functional
failure rate is compared to the error rate caused by Single-Event Upsets in the
sequential logic.
