  Challenges at the quantum-classical interface are examined with the goal of
architecting a scaled-up quantum computer comprising many thousands of qubits
in the solid-state. Separating the distinct sub-systems of the interface that
perform readout and control, general arguments are given for why distributing
the components of these sub-systems over significant distances and across large
temperature gradients presents a major challenge to scaling-up the technology.
Largely addressing these issues, an architecture for the interface that
leverages cryo-CMOS circuits proximal to the quantum plane is motivated in
addition to protocols that enable massively parallel readout of qubits via
frequency multiplexing.
