  On modern field-programmable gate arrays (FPGAs), certain critical path
portions of the designs might be prearranged into many multi-cell macros during
synthesis. These movable macros with constraints of shape and resources lead to
challenging mixed-size placement for FPGA designs which cannot be addressed by
previous analytical placers. Moreover, general timing-driven placement
algorithms are facing challenges when handling real-world application design
and ultrascale FPGA architectures. In this work, we propose AMF-Placer 2.0, an
open-source comprehensive timing-driven analytical mixed-size FPGA placer. It
supports mixed-size placement of heterogeneous resources (e.g.,
LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA, with an interface to Xilinx Vivado.
Standing upon the shoulders of AMF-Placer 1.0, AMFPlacer 2.0 is equipped with a
series of new techniques for timing optimization, including a simple but
effective timing model, placement-blockage-aware anchor insertion, WNS-aware
timing-driven quadratic placement, and sector-guided detailed placement. Based
on a set of the latest large open-source benchmarks from various domains for
Xilinx Ultrascale FPGAs, experimental results indicate that critical path
delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than
those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively.
Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14%
and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Although
limited by the absence of the exact timing model of the device, the information
of design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the first
open-source FPGA placer which can handle the timingdriven mixed-size placement
of practical complex designs with various FPGA resources and achieves the
comparable quality to the latest commercial tools.
