  The upgrades of the Belle experiment and the KEKB accelerator aim to increase
the data set of the experiment by the factor 50. This will be achieved by
increasing the luminosity of the accelerator which requires a significant
upgrade of the detector. A new pixel detector based on DEPFET technology will
be installed to handle the increased reaction rate and provide better vertex
resolution. One of the features of the DEPFET detector is a long integration
time of 20 {\mu}s, which increases detector occupancy up to 3 %. The detector
will generate about 2 GB/s of data. An FPGA-based two-level read-out system,
the Data Handling Hybrid, was developed for the Belle 2 pixel detector. The
system consists of 40 read-out and 8 controller modules. All modules are built
in {\mu}TCA form factor using Xilinx Virtex-6 FPGA and can utilize up to 4 GB
DDR3 RAM. The system was successfully tested in the beam test at DESY in
January 2014. The functionality and the architecture of the Belle 2 Data
Handling Hybrid system as well as the performance of the system during the beam
test are presented in the paper.
