  AI chips commonly employ SRAM memory as buffers for their reliability and
speed, which contribute to high performance. However, SRAM is expensive and
demands significant area and energy consumption. Previous studies have explored
replacing SRAM with emerging technologies like non-volatile memory, which
offers fast-read memory access and a small cell area. Despite these advantages,
non-volatile memory's slow write memory access and high write energy
consumption prevent it from surpassing SRAM performance in AI applications with
extensive memory access requirements. Some research has also investigated eDRAM
as an area-efficient on-chip memory with similar access times as SRAM. Still,
refresh power remains a concern, leaving the trade-off between performance,
area, and power consumption unresolved. To address this issue, our paper
presents a novel mixed CMOS cell memory design that balances performance, area,
and energy efficiency for AI memory by combining SRAM and eDRAM cells. We
consider the proportion ratio of one SRAM and seven eDRAM cells in the memory
to achieve area reduction using mixed CMOS cell memory. Additionally, we
capitalize on the characteristics of DNN data representation and integrate
asymmetric eDRAM cells to lower energy consumption. To validate our proposed
MCAIMem solution, we conduct extensive simulations and benchmarking against
traditional SRAM. Our results demonstrate that MCAIMem significantly
outperforms these alternatives in terms of area and energy efficiency.
Specifically, our MCAIMem can reduce the area by 48\% and energy consumption by
3.4$\times$ compared to SRAM designs, without incurring any accuracy loss.
