  Extended reality (XR) applications are Machine Learning (ML)-intensive,
featuring deep neural networks (DNNs) with millions of weights, tightly
latency-bound (10-20 ms end-to-end), and power-constrained (low tens of mW
average power). While ML performance and efficiency can be achieved by
introducing neural engines within low-power systems-on-chip (SoCs),
system-level power for nontrivial DNNs depends strongly on the energy of
non-volatile memory (NVM) access for network weights. This work introduces
Siracusa, a near-sensor heterogeneous SoC for next-generation XR devices
manufactured in 16 nm CMOS. Siracusa couples an octa-core cluster of RISC-V
digital signal processing cores with a novel tightly-coupled "At-Memory"
integration between a state-of-the-art digital neural engine called N-EUREKA
and an on-chip NVM based on magnetoresistive memory(MRAM), achieving 1.7x
higher throughput and 3x better energy efficiency than XR SoCs using NVM as
background memory. The fabricated SoC prototype achieves an area efficiency of
65.2 GOp/s/mm2 and a peak energy efficiency of 8.84 TOp/J for DNN inference
while supporting complex heterogeneous application workloads, which combine ML
with conventional signal processing and control.
