  Sparse matrix multiplication (SpMM) is widely applied to numerous domains,
such as graph processing, machine learning, and data analytics. However, inner
product based SpMM induces redundant zero-element computing for mismatched
nonzero operands, while outer product based approach lacks input reuse across
Process Elements (PEs) and poor output locality for accumulating partial sum
(psum) matrices. Besides, current works only focus on sparse-sparse matrix
multiplication (SSMM) or sparse-dense matrix multiplication (SDMM), rarely
performing efficiently for both. To address these problems, this paper proposes
an unified SpMM accelerator, called IOPS, hybridizing inner with outer
products. It reuses the input matrix among PEs with inner product dataflow, and
removes zero-element calculations with outer product approach in each PE, which
can efficiently process SSMM and SDMM. Moreover, an address mapping method is
designed to accumulate the irregular sparse psum matrices, reducing the latency
and DRAM access of psum accumulating. Furthermore, an adaptive partition
strategy is proposed to tile the input matrices based on their sparsity ratios,
effectively utilizing the storage of architecture and reducing DRAM access.
Compared with the SSMM accelerator, SpArch, we achieve 1.7x~6.3x energy
efficiency and 1.2x~4.4x resource efficiency, with 1.4x~2.1x DRAM access
saving.
