  In this article, cache blocking is implemented for the Navier Stokes
equations with anti-aliasing support on mixed grids in PyFR for CPUs. In
particular, cache blocking is used as an alternative to kernel fusion to
eliminate unnecessary data movements between kernels at the main memory level.
Specifically, kernels that exchange data are grouped together, and these groups
are then executed on small sub-regions of the domain that fit in per-core
private data cache. Additionally, cache blocking is also used to efficiently
implement a tensor product factorisation of the interpolation operators
associated with anti-aliasing. By using cache blocking, the intermediate
results between application of the sparse factors are stored in per-core
private data cache, and a significant amount of data movement from main memory
is avoided. In order to assess the performance gains a theoretical model is
developed, and the implementation is benchmarked using a compressible 3D
Taylor-Green vortex test case on both hexahedral and prismatic grids, with
third- and forth-order solution polynomials. The expected performance gains
based on the theoretical model range from 1.99 to 2.62, and the speedups
obtained in practice range from 1.67 to 3.67 compared to PyFR v1.11.0.
