  In the recent past, the success of Neural Architecture Search (NAS) has
enabled researchers to broadly explore the design space using learning-based
methods. Apart from finding better neural network architectures, the idea of
automation has also inspired to improve their implementations on hardware.
While some practices of hardware machine-learning automation have achieved
remarkable performance, the traditional design concept is still followed: a
network architecture is first structured with excellent test accuracy, and then
compressed and optimized to fit into a target platform. Such a design flow will
easily lead to inferior local-optimal solutions. To address this problem, we
propose a new framework to jointly explore the space of neural architecture,
hardware implementation, and quantization. Our objective is to find a quantized
architecture with the highest accuracy that is implementable on given hardware
specifications. We employ FPGAs to implement and test our designs with limited
loop-up tables (LUTs) and required throughput. Compared to the separate
design/searching methods, our framework has demonstrated much better
performance under strict specifications and generated designs of higher
accuracy by 18\% to 68\% in the task of classifying CIFAR10 images. With 30,000
LUTs, a light-weight design is found to achieve 82.98\% accuracy and 1293
images/second throughput, compared to which, under the same constraints, the
traditional method even fails to find a valid solution.
