  In this contribution the emulation of an ASIC temperature and power
monitoring system (TPMon) for FPGA prototyping is presented and tested to
control processor temperatures under different control targets and operating
strategies. The approach for emulating the power monitor is based on an
instruction-level energy model. For emulating the temperature monitor, a
thermal RC model is used. The monitoring system supplies an invasive MPSoC
computing architecture with hardware status information (power and temperature
data of the processors within the system). These data are required for
resource-aware load distribution. As a proof of concept different operating
strategies and control targets were evaluated for a 2-tile invasive MPSoC
computing system.
