  Synchoros VLSI design style has been proposed as an alternative to standard
cell-based design. Standard cells are replaced by synchoros, large grain, VLSI
design objects called SiLago (Silicon Lego) blocks. This new design style
eliminates the need to synthesise ad hoc wires of any type: functional and
infrastructural. SiLago blocks are organised into region instances. In a region
instance, communication among SiLago blocks is synchronous and happens over a
regional network on chip (NoC), whose fragments are also absorbed into SiLago
blocks. Consequently, the regional NoCs get created by the abutment of SiLago
blocks. The clock tree used in a region is called regional clock tree (RCT).
The synchoros VLSI design style requires that the RCT, like the regional NoCs,
is also created by abutting its fragments. The RCT fragments are absorbed
within the SiLago blocks. The RCT created by abutment is not an ad-hoc clock
tree but a structured and predictable design with known cost metrics. The
design of such an RCT is the focus of this paper. The scheme is scalable, and
we demonstrate that the proposed RCT can be generated for valid VLSI designs of
~1.5 million gates. The RCT created by abutment is correct by construction, and
its properties are predictable. We have validated the generated RCTs with
static timing analysis to validate the correct-by-construction claim. Finally,
we show that the cost metrics of the SiLago RCT
