  This paper investigates the synthesis of robust controllers from logical
specification of regular properties given in an interval temporal logic QDDC.
Our specification encompasses both hard robustness and soft robustness. Here,
hard robustness guarantees invariance of commitment under user-specified
relaxed (weakened) assumptions. A systematic framework for logically specifying
the assumption weakening by means of a formula, called Robustness Criterion, is
presented. The soft robustness pertains to the ability of the controller to
maintain the commitment for as many inputs as possible, irrespective of any
assumption. We present a uniform method for the synthesis of a robust
controller which guarantees the specified hard robustness and it optimizes the
specified soft robustness. The method is implemented using a tool DCSynth,
which provides soft requirement optimized controller synthesis. Through the
case study of a synchronous bus arbiter, we experimentally show the impact of
hard robustness criteria as well as soft robustness on the ability of the
synthesized controllers to meet the commitment "as much as possible". Both, the
worst-case and the expected case behaviors are analyzed.
