  Large scale digital computing almost exclusively relies on the von-Neumann
architecture which comprises of separate units for storage and computations.
The energy expensive transfer of data from the memory units to the computing
cores results in the well-known von-Neumann bottleneck. Various approaches
aimed towards bypassing the von-Neumann bottleneck are being extensively
explored in the literature. Emerging non-volatile memristive technologies have
been shown to be very efficient in computing analog dot products in an in-situ
fashion. The memristive analog computation of the dot product results in much
faster operation as opposed to digital vector in-memory bit-wise Boolean
computations. However, challenges with respect to large scale manufacturing
coupled with the limited endurance of memristors have hindered rapid
commercialization of memristive based computing solutions. In this work, we
show that the standard 8 transistor (8T) digital SRAM array can be configured
as an analog-like in-memory multi-bit dot product engine. By applying
appropriate analog voltages to the read-ports of the 8T SRAM array, and sensing
the output current, an approximate analog-digital dot-product engine can be
implemented. We present two different configurations for enabling multi-bit dot
product computations in the 8T SRAM cell array, without modifying the standard
bit-cell structure. Since our proposal preserves the standard 8T-SRAM array
structure, it can be used as a storage element with standard read-write
instructions, and also as an on-demand analog-like dot product accelerator.
