  In our prior study of an L-bit priority encoder (PE), a so-called
one-directional-array to two-directional-array conversion method is deployed to
turn an L-bit input data into an MxN-bit matrix. Following this, an N-bit PE
and an M-bit PE are employed to obtain a row index and column index. From
those, the highest priority bit of L-bit input data is achieved. This brief
extends our previous work to construct a scalable architecture of
high-performance large-sized PEs. An optimum pair of (M, N) and look-ahead
signal are proposed to improve the overall PE performance significantly. The
evaluation is achieved by implementing a variety of PEs whose L varies from
4-bit to 4096-bit in 180-nm CMOS technology. According to post-place-and-route
simulation results, at PE size of 64 bits, 256 bits, and 2048 bits the
operating frequencies reach 649 MHz, 520 MHz, and 370 MHz, which are 1.2 times,
1.5 times, and 1.4 times, as high as state-of-the-art ones.
