  Convolutional Neural Networks (CNNs) are computationally intensive algorithms
that currently require dedicated hardware to be executed. In the case of
FPGA-Based accelerators, we point-out in this work the challenge of
Multi-Operand Adders (MOAs) and their high resource utilization in an FPGA
implementation of a CNN. To address this challenge, two optimization
strategies, that rely on time-multiplexing and approximate computing, are
investigated. At first glance, the two strategies looked promising to reduce
the footprint of a given architectural mapping, but when synthesized on the
device, none of them gave the expected results. Experimental sections analyze
the reasons of these unexpected results.
