  Racetrack memory is a new technology which utilizes magnetic domains along a
nanoscopic wire in order to obtain extremely high storage density. In racetrack
memory, each magnetic domain can store a single bit of information, which can
be sensed by a reading port (head). The memory has a tape-like structure which
supports a shift operation that moves the domains to be read sequentially by
the head. In order to increase the memory's speed, prior work studied how to
minimize the latency of the shift operation, while the no less important
reliability of this operation has received only a little attention.
  In this work we design codes which combat shift errors in racetrack memory,
called position errors. Namely, shifting the domains is not an error-free
operation and the domains may be over-shifted or are not shifted, which can be
modeled as deletions and sticky insertions. While it is possible to use
conventional deletion and insertion-correcting codes, we tackle this problem
with the special structure of racetrack memory, where the domains can be read
by multiple heads. Each head outputs a noisy version of the stored data and the
multiple outputs are combined in order to reconstruct the data. Under this
paradigm, we will show that it is possible to correct, with at most a single
bit of redundancy, $d$ deletions with $d+1$ heads if the heads are
well-separated. Similar results are provided for burst of deletions, sticky
insertions and combinations of both deletions and sticky insertions.
