  Fully-analog in-memory computing (IMC) architectures that implement both
matrix-vector multiplication and non-linear vector operations within the same
memory array have shown promising performance benefits over conventional IMC
systems due to the removal of energy-hungry signal conversion units. However,
maintaining the computation in the analog domain for the entire deep neural
network (DNN) comes with potential sensitivity to interconnect parasitics.
Thus, in this paper, we investigate the effect of wire parasitic resistance and
capacitance on the accuracy of DNN models deployed on fully-analog IMC
architectures. Moreover, we propose a partitioning mechanism to alleviate the
impact of the parasitic while keeping the computation in the analog domain
through dividing large arrays into multiple partitions. The SPICE circuit
simulation results for a 400 X 120 X 84 X 10 DNN model deployed on a
fully-analog IMC circuit show that a 94.84% accuracy could be achieved for
MNIST classification application with 16, 8, and 8 horizontal partitions, as
well as 8, 8, and 1 vertical partitions for first, second, and third layers of
the DNN, respectively, which is comparable to the ~97% accuracy realized by
digital implementation on CPU. It is shown that accuracy benefits are achieved
at the cost of higher power consumption due to the extra circuitry required for
handling partitioning.
