  The last few years have seen the emergence of IoT processors: ultra-low power
systems-on-chips (SoCs) combining lightweight and flexible micro-controller
units (MCUs), often based on open-ISA RISC-V cores, with application-specific
accelerators to maximize performance and energy efficiency. Overall, this
heterogeneity level requires complex hardware and a full-fledged software stack
to orchestrate the execution and exploit platform features. For this reason,
enabling agile design space exploration becomes a crucial asset for this new
class of low-power SoCs. In this scenario, high-level simulators play an
essential role in breaking the speed and design effort bottlenecks of
cycle-accurate simulators and FPGA prototypes, respectively, while preserving
functional and timing accuracy. We present GVSoC, a highly configurable and
timing-accurate event-driven simulator that combines the efficiency of C++
models with the flexibility of Python configuration scripts. GVSoC is fully
open-sourced, with the intent to drive future research in the area of highly
parallel and heterogeneous RISC-V based IoT processors, leveraging three
foundational features: Python-based modular configuration of the hardware
description, easy calibration of platform parameters for accurate performance
estimation, and high-speed simulation. Experimental results show that GVSoC
enables practical functional and performance analysis and design exploration at
the full-platform level (processors, memory, peripherals and IOs) with a
speed-up of 2500x with respect to cycle-accurate simulation with errors
typically below 10% for performance analysis.
