  While long polar codes can achieve the capacity of arbitrary binary-input
discrete memoryless channels when decoded by a low complexity successive
cancelation (SC) algorithm, the error performance of the SC algorithm is
inferior for polar codes with finite block lengths. The cyclic redundancy check
(CRC) aided successive cancelation list (SCL) decoding algorithm has better
error performance than the SC algorithm. However, current CRC aided SCL
(CA-SCL) decoders still suffer from long decoding latency and limited
throughput. In this paper, a reduced latency list decoding (RLLD) algorithm for
polar codes is proposed. Our RLLD algorithm performs the list decoding on a
binary tree, whose leaves correspond to the bits of a polar code. In existing
SCL decoding algorithms, all the nodes in the tree are traversed and all
possibilities of the information bits are considered. Instead, our RLLD
algorithm visits much fewer nodes in the tree and considers fewer possibilities
of the information bits. When configured properly, our RLLD algorithm
significantly reduces the decoding latency and hence improves throughput, while
introducing little performance degradation. Based on our RLLD algorithm, we
also propose a high throughput list decoder architecture, which is suitable for
larger block lengths due to its scalable partial sum computation unit. Our
decoder architecture has been implemented for different block lengths and list
sizes using the TSMC 90nm CMOS technology. The implementation results
demonstrate that our decoders achieve significant latency reduction and area
efficiency improvement compared with other list polar decoders in the
literature.
