  The use of FPGAs for efficient graph processing has attracted significant
interest. Recent memory subsystem upgrades including the introduction of HBM in
FPGAs promise to further alleviate memory bottlenecks. However, modern
multi-channel HBM requires much more processing pipelines to fully utilize its
bandwidth potential. Existing designs do not scale well, resulting in
underutilization of the HBM facilities even when all other resources are fully
consumed. In this paper, we re-examined the graph processing workloads and
found much diversity in processing. We also found that the diverse workloads
can be easily classified into two types, namely dense and sparse partitions.
This motivates us to propose a resource-efficient heterogeneous pipeline
architecture. Our heterogeneous architecture comprises of two types of
pipelines: Little pipelines to process dense partitions with good locality and
Big pipelines to process sparse partitions with the extremely poor locality.
Unlike traditional monolithic pipeline designs, the heterogeneous pipelines are
tailored for more specific memory access patterns, and hence are more
lightweight, allowing the architecture to scale up to more effectively with
limited resources. In addition, we propose a model-guided task scheduling
method that schedules partitions to the right pipeline types, generates the
most efficient pipeline combination and balances workloads. Furthermore, we
develop an automated open-source framework, called ReGraph, which automates the
entire development process. ReGraph outperforms state-of-the-art FPGA
accelerators by up to 5.9 times in terms of performance and 12times in terms of
resource efficiency.
