  Recent efforts for improving the performance of neural network (NN)
accelerators that meet today's application requirements have given rise to a
new trend of logic-based NN inference relying on fixed function combinational
logic. Mapping such large Boolean functions with many input variables and
product terms to digital signal processors (DSPs) on Field-programmable gate
arrays (FPGAs) needs a novel framework considering the structure and the
reconfigurability of DSP blocks during this process. The proposed methodology
in this paper maps the fixed function combinational logic blocks to a set of
Boolean functions where Boolean operations corresponding to each function are
mapped to DSP devices rather than look-up tables (LUTs) on the FPGAs to take
advantage of the high performance, low latency, and parallelism of DSP blocks.
% This paper also presents an innovative design and optimization methodology
for compilation and mapping of NNs, utilizing fixed function combinational
logic to DSPs on FPGAs employing high-level synthesis flow. % Our experimental
evaluations across several \REVone{datasets} and selected NNs demonstrate the
comparable performance of our framework in terms of the inference latency and
output accuracy compared to prior art FPGA-based NN accelerators employing
DSPs.
