  In energy-constrained scenarios such as IoT applications, the primary
requirement for System-on-Chips (SoCs) is to increase battery life. However,
when performing sub/near-threshold operations, the relatively large leakage
current hinders Static Random Access Memory (SRAM) from normal read/write
functionalities at the lowest possible voltage (VDDMIN). In this work, we
propose an Ultra8T SRAM to aggressively reduce VDDMIN by using a leakage
detection strategy where the safety sensing time on bitlines is quantified
without any additional hardware overhead. We validate the proposed Ultra8T
using a 256x64 array in 28nm CMOS technology. Post-simulations show successful
read operation at 0.25V with 1.11{\mu}s read delay, and the minimum energy
required is 1.69pJ at 0.4V.
