  In Carry Propagate Adders, carry propagation is the critical delay. For the
1-digit adders that they use, the most efficient scheme is to generate two
intermediate carries: C$_{out0}$ ($C_{in}$=0) and $C_{out1}$($C_{in}$=1). Then
multiplex them to produce the correct output according to $C_{in}$. For any
radix, the carry output has always a logical value 0 or 1. We show that using 0
and $V_{dd}$ levels for input and output carries instead of 0 and $V_{dd}$/3 in
quaternary full adders significantly reduce the carry propagation. We compare
such a quaternary full adder with binary full adders to implement N-digit carry
propagate adders.
