  Computation on a large volume of data at high speed and low power requires
energy-efficient computing architectures. Spiking neural network (SNN) with
bio-inspired spike-timing-dependent plasticity learning (STDP) is a promising
solution for energy-efficient neuromorphic systems than conventional artificial
neural network (ANN). Previous works on SNN with STDP learning primarily uses
memristive devices which are difficult to fabricate. Some reported works on SNN
makes use of memristor macro models, which are software-based and cannot give
complete insight into circuit implementation challenges. This article presents
for the first time, a full circuit-level implementation of the SNN system
featuring on-chip unsupervised STDP learning in standard CMOS technology. It
does not involve the use of FPGAs, CPUs or GPUs for training the neural
network. We demonstrated the complete circuit-level design, implementation and
simulation of SNN with on-chip training and inference for pattern
classification using 180 nm CMOS technology. A comprehensive comparison of the
proposed SNN circuit with the previous related work is also presented. To
demonstrate the versatility of the CMOS synapse circuit for application
scenarios requiring rate-based learning, we have tuned the pair-based STDP
circuit to obtain Bienenstock-Cooper-Munro (BCM) characteristics and applied it
to heart rate classification.
