  Continuing demands for increased compute efficiency and communication
bandwidth have led to the development of novel interconnect technologies with
the potential to outperform conventional electrical interconnects. With a
plurality of interconnect technologies to include electronics, photonics,
plasmonics, and hybrids thereof, the simple approach of counting on-chip
devices to capture performance is insufficient. While some efforts have been
made to capture the performance evolution more accurately, they eventually
deviate from the observed development pace. Thus, a holistic figure of merit
(FOM) is needed to adequately compare these recent technology paradigms. Here
we introduce the Capability-to-Latency-Energy-Amount-Resistance (CLEAR) FOM
derived from device and link performance criteria of both active optoelectronic
devices and passive components alike. As such CLEAR incorporates communication
delay, energy efficiency, on-chip scaling and economic cost. We show that CLEAR
accurately describes compute development including most recent machines. Since
this FOM is derived bottom-up, we demonstrate remarkable adaptability to
applications ranging from device-level to network and system-level. Applying
CLEAR to benchmark device, link, and network performance against fundamental
physical compute and communication limits shows that photonics is competitive
even for fractions of the die-size, thus making a case for on-chip optical
interconnects.
