  In comparison to the conventional complementary pull-up and pull-down logic
structure, the pass transistor logic (PTL) family reduces the number of
transistors required to perform logic functions, thereby reducing both area and
power consumption. However, this logic family requires inter-stage inverters to
ensure signal integrity in cascaded logic circuits, and inverters must be used
to provide each logical input signal in its complementary form. These inverters
and complementary signals increase the device count and significantly degrade
overall system efficiency.
  Dual-gate ambipolar field-effect transistors natively provide a
single-transistor XNOR operation and permit highly-efficient and compact
circuits due to their ambipolar capabilities. Similar to PTL, logic circuits
based on ambipolar field-effect transistors require complementary signals.
Therefore, numerous inverters are required, with significant energy and area
costs.
  Ambipolar field-effect transistors are a natural match for PTL, as hybrid
ambipolar-PTL circuits can simultaneously use these inverters to satisfy their
necessity in both PTL and ambipolar circuits. We therefore propose a new hybrid
ambipolar-PTL logic family that exploits the compact logic of PTL and the
ambipolar capabilities of ambipolar field-effect transistors. Novel hybrid
ambipolar-PTL circuits were designed and simulated in SPICE, demonstrating
strong signal integrity along with the efficiency advantages of using the
required inverters to simultaneously satisfy the requirements of PTL and
ambipolar circuits. In comparison to the ambipolar field-effect transistors in
the conventional CMOS logic structure, our hybrid full adder circuit can reduce
propagation delay by 47%, energy consumption by 88%, energy-delay product by a
factor of 9, and area-energy-delay product by a factor of 20.
