  The High-Luminosity LHC will provide the unique opportunity to explore the
nature of physics beyond the Standard Model of strong and electroweak
interactions. Highly selective first level triggers are essential for the
physics programme of the ATLAS experiment at the HL-LHC where the instantaneous
luminosity will exceed the LHC Run 1 instantaneous luminosity by almost an
order of magnitude. The ATLAS first level muon trigger rate is dominated by low
momentum muons, selected due to the moderate momentum resolution of the
resistive plate and thin gap trigger chambers. This limitation can be overcome
by including the data of the precision muon drift tube (MDT) chambers in the
first level trigger decision. This requires the fast continuous transfer of the
MDT hits to the off-detector trigger logic and a fast track reconstruction
algorithm performed in the trigger logic.
  In order to demonstrate the feasibility of reconstructing tracks in MDT
chambers within the short available first-level trigger latency of about
3~$\mu$s we implemented a seeded Hough transform on the ARM Cortex A9
microprocessor of a Xilinx Zynq FPGA and studied its performance with test-beam
data recorded in CERN's Gamma Irradiation Facility. We could show that by using
the ARM processor's Neon Single Instruction Multiple Data Engine to carry out 4
floating point operations in parallel the challenging latency requirement can
be matched.
