  We present a tool flow and results for a model-based hardware design for
FPGAs from Simulink descriptions which nicely integrates into existing
environments. While current commercial tools do not exploit some high-level
optimizations, we investigate the promising approach of using reusable
subcircuits for folding transformations to control embedded multiplier usage
and to optimize logic block usage. We show that resource improvements of up to
70% compared to the original model are possible, but it is also shown that
subcircuit selection is a critical task. While our tool flow provides good
results already, the investigation and optimization of subcircuit selection is
clearly identified as an additional keypoint to extend high-level control on
low-level FPGA mapping properties.
