  Superconducting digital Pulse-Conserving Logic (PCL) and Josephson SRAM
(JSRAM) memory together enable scalable circuits with energy efficiency 100x
beyond leading-node CMOS. Circuit designs support high throughput and low
latency when implemented in an advanced fabrication stack with
high-critical-current-density Josephson junctions of 1000$\mu$A/$\mu$m$^2$.
Pulse-conserving logic produces one single-flux-quantum output for each input,
and includes a three-input, three-output gate producing logical or3, majority3
and and3. Gate macros using dual-rail data encoding eliminate inversion latency
and produce efficient implementations of all standard logic functions. A full
adder using 70 Josephson junctions has a carry-out latency of 5ps corresponding
to an effective 12 levels of logic at 30 GHz. JSRAM (Josephson SRAM) memory
uses single-flux-quantum signals throughout an active array to achieve
throughput at the same clock rate as the logic. The unit cell has eight
Josephson junctions, signal propagation latency of 1ps, and a footprint of
2$\mu$m$^2$. Projected density of JSRAM is 4 MB/cm$^2$, and computational
density of pulse-conserving logic is on par with leading node CMOS accounting
for power densities and clock rates.
