  Network-on-Chip (NoC) is currently the paradigm of choice to interconnect the
different components of System-on-Chips (SoCs) or Chip Multiprocessors (CMPs).
As the levels of integration continue to grow, however, current NoCs face
significant scalability limitations and have prompted research in novel
interconnect technologies. Among these, wireless intra-chip communications have
been under intense scrutiny due to their low latency broadcast and
architectural flexibility. Thus far, the practicality of the idea has been
studied from the RF front-end and the network interface perspectives, whereas
little to no attention has been placed on another essential component: the data
converters. This article aims to fill this gap by providing a comprehensive
analysis of the requirements of the scenario, as well as of the current
performance and cost trends of Analog-to-Digital Converters (ADCs). Based on
Murmann's data, we demonstrate that ADCs will not be a roadblock for the
realization of wireless intra-chip communications although current designs do
not meet their demands fully.
