  A monolithic multi-channel analog transient recorder, implemented using
switched capacitor sample-and-hold circuits and a high-speed
analogically-adjustable delay-line-based write clock, has been designed,
fabricated and tested. The 2.1 by 6.9 mm layout, in 1.2 micron CMOS, includes
over 31,000 transistors and 2048 double polysilicon capacitors. The circuit
contains four parallel channels, each with a 512 deep switched-capacitor
sample-and-hold system. A 512 deep edge sensitive tapped active delay line uses
look-ahead and 16 way interleaving to develop the 512 sample and hold clocks,
each as little as 3.2 ns wide and 200 ps apart. Measurements of the device have
demonstrated 5 GHz maximum sample rate, at least 350 MHz bandwidth, an
extrapolated rms aperture uncertainty per sample of 0.7 ps, and a signal to rms
noise ratio of 2000:1.
