  Long polar codes can achieve the symmetric capacity of arbitrary binary-input
discrete memoryless channels under a low complexity successive cancelation (SC)
decoding algorithm. However, for polar codes with short and moderate code
length, the decoding performance of the SC algorithm is inferior. The cyclic
redundancy check (CRC) aided successive cancelation list (SCL) decoding
algorithm has better error performance than the SC algorithm for short or
moderate polar codes. In this paper, we propose an efficient list decoder
architecture for the CRC aided SCL algorithm, based on both algorithmic
reformulations and architectural techniques. In particular, an area efficient
message memory architecture is proposed to reduce the area of the proposed
decoder architecture. An efficient path pruning unit suitable for large list
size is also proposed. For a polar code of length 1024 and rate $\frac{1}{2}$,
when list size $L=2$ and 4, the proposed list decoder architecture is
implemented under a TSMC 90nm CMOS technology. Compared with the list decoders
in the literature, our decoder achieves 1.33 to 1.96 times hardware efficiency.
