  Tensor decomposition has become an essential tool in many applications in
various domains, including machine learning. Sparse Matricized Tensor Times
Khatri-Rao Product (MTTKRP) is one of the most computationally expensive
kernels in tensor computations. Despite having significant computational
parallelism, MTTKRP is a challenging kernel to optimize due to its irregular
memory access characteristics. This paper focuses on a multi-faceted memory
system, which explores the spatial and temporal locality of the data structures
of MTTKRP. Further, users can reconfigure our design depending on the behavior
of the compute units used in the FPGA accelerator. Our system efficiently
accesses all the MTTKRP data structures while reducing the total memory access
time, using a distributed cache and Direct Memory Access (DMA) subsystem.
Moreover, our work improves the memory access time by 3.5x compared with
commercial memory controller IPs. Also, our system shows 2x and 1.26x speedups
compared with cache-only and DMA-only memory systems, respectively.
