  We present the design and the test results of a dual-channel Vertical-Cavity
Surface-Emitting Laser (VCSEL) driver ASIC LOCld65 for detector front-end
readout. LOCld65 is designed in a commercial 65-nm CMOS technology with a power
supply of 1.2 V. LOCld65 contains two separate channels with the same structure
and the two channels share an I2C slave. Each channel consists of an input
amplifier, four stages of limiting amplifiers (LAs), a high-current output
driver, and a bias-current generator. In order to extend the bandwidth, the
input amplifier uses an inductive peaking technique and the LAs use a shared
inductive peaking technique. The input amplifier and the output driver each
utilize a Continuous-Time Linear Equalizer (CTLE). The LAs employ active
feedback. The modulation current, the bias current, the peaking strength of the
CTLEs, and the feedback strength of LAs are programmable through an I2C
interface. In order to protect from the radiation damage, the I2C slave is
implemented with triple modular redundancy. Each channel of LOCld65 is tested
to operate up to 14 Gbps with typical power dissipations (the VCSEL included)
of 68.3 mW/channel and 62.1 mW/channel at the VCSEL voltages of 3.3 V and 2.5
V, respectively. LOCld65 survives 4.9 kGy(SiO2). LOCld65 is an excellent match
for the serializer-deserializer ASIC lpGBT in single- or dual-channel optical
transmitters in HL-LHC upgrade applications.
