  We explore the use of Large Language Models (LLMs) to generate high-quality
Register-Transfer Level (RTL) code with minimal human interference. The
traditional RTL design workflow requires human experts to manually write
high-quality RTL code, which is time-consuming and error-prone. With the help
of emerging LLMs, developers can describe their requirements to LLMs which then
generate corresponding code in Python, C, Java, and more. Adopting LLMs to
generate RTL design in hardware description languages is not trivial, given the
complex nature of hardware design and the generated design has to meet the
timing and physical constraints.
  We propose VeriAssist, an LLM-powered programming assistant for Verilog RTL
design workflow. VeriAssist takes RTL design descriptions as input and
generates high-quality RTL code with corresponding test benches. VeriAssist
enables the LLM to self-correct and self-verify the generated code by adopting
an automatic prompting system and integrating RTL simulator in the code
generation loop. To generate an RTL design, VeriAssist first generates the
initial RTL code and corresponding test benches, followed by a
self-verification step that walks through the code with test cases to reason
the code behavior at different time steps, and finally it self-corrects the
code by reading the compilation and simulation results and generating final RTL
code that fixes errors in compilation and simulation. This design fully
leverages the LLMs' capabilities on multi-turn interaction and chain-of-thought
reasoning to improve the quality of the generated code. We evaluate VeriAssist
with various benchmark suites and find it significantly improves both syntax
and functionality correctness over existing LLM implementations, thus
minimizing human intervention and making RTL design more accessible to novice
designers.
