  Supported by their high power efficiency and recent advancements in High
Level Synthesis (HLS), FPGAs are quickly finding their way into HPC and cloud
systems. Large amounts of work have been done so far on loop and area
optimizations for different applications on FPGAs using HLS. However, a
comprehensive analysis of the behavior and efficiency of the memory controller
of FPGAs is missing in literature, which becomes even more crucial when the
limited memory bandwidth of modern FPGAs compared to their GPU counterparts is
taken into account. In this work, we will analyze the memory interface
generated by Intel FPGA SDK for OpenCL with different configurations for
input/output arrays, vector size, interleaving, kernel programming model,
on-chip channels, operating frequency, padding, and multiple types of
overlapped blocking. Our results point to multiple shortcomings in the memory
controller of Intel FPGAs, especially with respect to memory access alignment,
that can hinder the programmer's ability in maximizing memory performance in
their design. For some of these cases, we will provide work-arounds to improve
memory bandwidth efficiency; however, a general solution will require major
changes in the memory controller itself.
