  In VLSI chip design flow, Static Timing Analysis (STA) is used for fast and
accurate analysis of data-path delay. This process is fast because delay is
picked from Look Up Tables (LUT) rather than conventional SPICE simulations.
But accuracy of this method depends upon the underlying delay model with which
LUT was characterized. Non Linear Delay Model (NLDM) based LUTs are quite
common in industries. These LUT requires huge amount to time during
characterization because of huge number of SPICE simulations done at arbitrary
points. To improve this people proposed various other delay models like
alpha-power and piecewise linear delay models. Bulusu et al proposed Linear
Delay Model(LDM) which reduces LUT generation time to 50 percent. LDM divides
delay curve w.r.t input rise time(trin) into two different region one is linear
and other is non-linear. This boundary point between linear and non- linear
region was called break point (trb). Linear region will be done if we simulate
at only two points. This advantage will be possible by having knowledge of this
break point at various PVT corners. In this paper, We will analyze this break
point and will give a formula to find out this at various PVT corners.
Knowledge about (trb) will restrict LUT simulations only in non-linear region
and will help us in saving huge amount of time during LUT characterization.
