  In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which
is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold
digital circuit operation. Basically the principle of sub- threshold logics is
operating MOSFET in sub-threshold region and using the leakage current in that
region for switching action, there by drastically decreasing power. To reduce
the power consumption of sub-threshold circuits further, a novel body biasing
technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS
approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high
current drive, compared to CMOS circuits, operated at lower voltages. The VTMOS
is based on operating the MOS devices with an appropriate substrate bias which
varies with gate voltage, by connecting a positive bias voltage between gate
and substrate for NMOS and negative bias voltage between gate and substrate for
PMOS. With VTMOS, there is a considerable reduction in operating current and
power dissipation, while the remaining characteristics are almost the same as
those of DTMOS. Results of our investigations show that VTMOS circuits improves
the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold
region.. The performance analysis and comparison of VTMOS, DTMOS and CMOS is
made and test results of Power dissipation, Propagation delay and Power delay
product are presented to justify the superiority of VTMOS logic over
conventional sub-threshold logics using Hspice Tool. The dependency of these
parameters on frequency of operation has also been investigated.
