  As the conventional silicon metal-oxide-semiconductor field-effect transistor
(MOSFET) approaches its scaling limits; many novel device structures are being
extensively explored. Among them, the silicon nanowire transistor (SNWT) has
attracted broad attention. To understand device physics in depth and to assess
the performance limits of SNWTs, simulation is becoming increasingly important.
The objectives of this work are: 1) to theoretically explore the essential
physics of SNWTs (e.g., electrostatics, transport and band structure) by
performing computer-based simulations, and 2) to assess the performance limits
and scaling potentials of SNWTs and to address the SNWT design issues. The
computer based simulations carried out are essentially based on DFT using NEGF
formalism. A silicon nanowire has been modeled as PN diode (Zener Diode), PIN
diode, PIP & NIN diode configurations by selectively doping the nanowire and
simulated by biasing one end of the nanowire to ground and sweeping the other
end of the nanowire from -1 V to 1 V to obtain the electrical characteristics
of the respective diodes. In order to determine the effectiveness of the
modeled diodes in silicon nanowire, the same diodes have been modeled using a
germanium nanowire by selective doping and simulated in the same manner to
obtain the electrical characteristics of the germanium nanowire based diodes
which has been used as a reference to analyze the characteristics obtained
using silicon nanowire. The modeled diodes are extremely small in dimension
when compared to the conventional bulk silicon and germanium based diodes. This
work is followed by modeling and simulation of a gate all around nanowire field
effect transistor using two different gate dielectrics, followed by temperature
dependence of the nanowire FET characteristics and the off state current and
conductance variation using the two dielectrics.
