  We propose a new DRAM-based true random number generator (TRNG) that
leverages DRAM cells as an entropy source. The key idea is to intentionally
violate the DRAM access timing parameters and use the resulting errors as the
source of randomness. Our technique specifically decreases the DRAM row
activation latency (timing parameter tRCD) below manufacturer-recommended
specifications, to induce read errors, or activation failures, that exhibit
true random behavior. We then aggregate the resulting data from multiple cells
to obtain a TRNG capable of providing a high throughput of random numbers at
low latency.
  To demonstrate that our TRNG design is viable using commodity DRAM chips, we
rigorously characterize the behavior of activation failures in 282
state-of-the-art LPDDR4 devices from three major DRAM manufacturers. We verify
our observations using four additional DDR3 DRAM devices from the same
manufacturers. Our results show that many cells in each device produce random
data that remains robust over both time and temperature variation. We use our
observations to develop D-RanGe, a methodology for extracting true random
numbers from commodity DRAM devices with high throughput and low latency by
deliberately violating the read access timing parameters. We evaluate the
quality of our TRNG using the commonly-used NIST statistical test suite for
randomness and find that D-RaNGe: 1) successfully passes each test, and 2)
generates true random numbers with over two orders of magnitude higher
throughput than the previous highest-throughput DRAM-based TRNG.
