  We propose a Digital Neuron, a hardware inference accelerator for
convolutional deep neural networks with integer inputs and integer weights for
embedded systems. The main idea to reduce circuit area and power consumption is
manipulating dot products between input feature and weight vectors by Barrel
shifters and parallel adders. The reduced area allows the more computational
engines to be mounted on an inference accelerator, resulting in high throughput
compared to prior HW accelerators. We verified that the multiplication of
integer numbers with 3-partial sub-integers does not cause significant loss of
inference accuracy compared to 32-bit floating point calculation. The proposed
digital neuron can perform 800 MAC operations in one clock for computation for
convolution as well as full-connection. This paper provides a scheme that
reuses input, weight, and output of all layers to reduce DRAM access. In
addition, this paper proposes a configurable architecture that can provide
inference of adaptable feature of convolutional neural networks. The throughput
in terms of Watt of the digital neuron is achieved 754.7 GMACs/W.
