  Stateful logic is a promising processing-in-memory (PIM) paradigm to perform
logic operations using emerging nonvolatile memory cells. While most stateful
logic circuits to date focused on technologies such as resistive RAM, we
propose two approaches to designing stateful logic using spin orbit torque
(SOT) MRAM. The first approach utilizes the separation of read and write paths
in SOT devices to perform logic operations. In contrast to previous work, our
method utilizes a standard memory structure, and each row can be used as input
or output. The second approach uses voltage-gated SOT switching to allow
stateful logic in denser memory arrays. We present array structures to support
the two approaches and evaluate their functionality using SPICE simulations in
the presence of process variation and device mismatch.
