  A new method is discussed for the systematic synthesis, design and
performance optimization of varactor-based parametric frequency dividers (PFDs)
exhibiting an ultra-low power threshold ($P_{th}$). For the first time, it is
analytically shown that the $P_{th}$-value exhibited by any PFD can always be
expressed as an explicit closed-form function of the different impedances
forming its network. Such a unique and unexplored property permits to rely on
linear models, during the PFD design and performance optimization. The validity
of our analytical model has been verified, in a commercial circuit simulator,
through time-domain and frequency-domain algorithms. To demonstrate the
effectiveness of our new synthesis approach, we also report on a lumped
prototype of a 200:100MHz PFD, realized on a printed circuit board (PCB).
Although inductors with quality factors lower than 50 were used, the PFD
prototype exhibits a $P_{th}$-value lower than $-$15dBm. Such a low
$P_{th}$-value is the lowest one ever reported for passive varactor-based PFDs,
operating in the same frequency range.
