  Query co-processing on graphics processors (GPUs) has become an effective
means to improve the performance of main memory databases. However, the
relatively low bandwidth and high latency of the PCI-e bus are usually
bottleneck issues for co-processing. Recently, coupled CPU-GPU architectures
have received a lot of attention, e.g. AMD APUs with the CPU and the GPU
integrated into a single chip. That opens up new opportunities for optimizing
query co-processing. In this paper, we experimentally revisit hash joins, one
of the most important join algorithms for main memory databases, on a coupled
CPU-GPU architecture. Particularly, we study the fine-grained co-processing
mechanisms on hash joins with and without partitioning. The co-processing
outlines an interesting design space. We extend existing cost models to
automatically guide decisions on the design space. Our experimental results on
a recent AMD APU show that (1) the coupled architecture enables fine-grained
co-processing and cache reuses, which are inefficient on discrete CPU-GPU
architectures; (2) the cost model can automatically guide the design and tuning
knobs in the design space; (3) fine-grained co-processing achieves up to 53%,
35% and 28% performance improvement over CPU-only, GPU-only and conventional
CPU-GPU co-processing, respectively. We believe that the insights and
implications from this study are initial yet important for further research on
query co-processing on coupled CPU-GPU architectures.
