  In the era of post-Moore computing, network offload emerges as a solution to
two challenges: the imperative for low-latency communication and the push
towards hardware specialisation. Various methods have been employed to offload
protocol- and data-processing onto network interface cards (NICs), from
firmware modification to running full Linux on NICs for application execution.
The sPIN project enables users to define handlers executed upon packet arrival.
While simulations show sPIN's potential across diverse workloads, a full-system
evaluation is lacking. This work presents FPsPIN, a full FPGA-based
implementation of sPIN. FPsPIN is showcased through offloaded MPI datatype
processing, achieving a 96% overlap ratio. FPsPIN provides an adaptable
open-source research platform for researchers to conduct end-to-end experiments
on smart NICs.
