  We present a high performance low-power digital base-band architecture,
specially designed for an energy optimized duty-cycled wake-up receiver scheme.
Based on a careful wake-up beacon design, a structured wake-up beacon detection
technique leads to an architecture that compensates for the implementation loss
of a low-power wake-up receiver front-end at low energy and area costs. Design
parameters are selected by energy optimization and the architecture is easily
scalable to support various network sizes. Fabricated in 65nm CMOS, the digital
base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps,
with appropriate 97% wake-up beacon detection and 0.04% false alarm
probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at
f_max=5kHz and 0.018uW power consumption. Based on these results we show that
our digital base-band can be used as a companion to compensate for front-end
implementation losses resulting from the limited wake-up receiver power budget
at a negligible cost. This implies an improvement of the practical sensitivity
of the wake-up receiver, compared to what is traditionally reported.
