  Steep transistors are crucial in lowering power consumption of the integrated
circuits. However, the difficulties in achieving steepness beyond the Boltzmann
limit experimentally have hindered the fundamental challenges in application of
these devices in integrated circuits. From a sensitivity perspective, an ideal
switch should have a high sensitivity to the gate voltage and lower sensitivity
to the device design parameters like oxide and body thicknesses. In this work,
conventional tunnel-FET (TFET) and negative capacitance FET are shown to suffer
from high sensitivity to device design parameters using full-band atomistic
quantum transport simulations and analytical analysis. Although Dielectric
Engineered (DE-) TFETs based on 2D materials show smaller sensitivity compared
with the conventional TFETs, they have leakage issue. To mitigate this
challenge, a novel DE-TFET design has been proposed and studied.
