  Pre-silicon side-channel leakage assessment is a useful tool to identify
hardware vulnerabilities at design time, but it requires many high-resolution
power traces and increases the power simulation cost of the design. By
downsampling and averaging these high-resolution traces, we show that the power
simulation cost can be considerably reduced without significant loss of
side-channel leakage assessment quality. We introduce a theoretical basis for
our claims. Our results demonstrate up to 6.5-fold power-simulation speed
improvement on a gate-level side-channel leakage assessment of a RISC-V SoC.
Furthermore, we clarify the conditions under which the averaged sampling
technique can be successfully used.
