  Security is a growing problem that needs hardware support. Memristors provide
an alternative technology for hardware-supported security implementation. This
paper presents a specific technique that utilizes the benefits of hybrid
CMOS-memristors technology demonstrated with SHA3 over implementations that use
only memristor technology. In the proposed technique, SHA3 is implemented in a
set of perpendicular crossbar arrays structured to facilitate logic
implementation and circular bit rotation (Rho operation), which is perhaps the
most complex operation in SHA3 when carried out in memristor arrays. The Rho
operation itself is implemented with CMOS multiplexers (MUXs). The proposed
accelerator is standby power-free and circumvents the memory access bottleneck
in conventional computers. In addition, our design obscures the intermediate
values from the I/O interface and outperforms the state-of-the-art
memristor-based designs in terms of size and energy. Demonstrating the
memristor implementation of SHA3 provides an impetus for utilizing memristors
in information security applications.
