  Data movement costs constitute a significant bottleneck in modern machine
learning (ML) systems. When combined with the computational complexity of
algorithms, such as neural networks, designing hardware accelerators with low
energy footprint remains challenging. Finite state automata (FSA) constitute a
type of computation model used as a low-complexity learning unit in ML systems.
The implementation of FSA consists of a number of memory states. However, FSA
can be in one of the states at a given time. It switches to another state based
on the present state and input to the FSA. Due to its natural synergy with
memory, it is a promising candidate for in-memory computing for reduced data
movement costs. This work focuses on a novel FSA implementation using resistive
RAM (ReRAM) for state storage in series with a CMOS transistor for biasing
controls. We propose using multi-level ReRAM technology capable of
transitioning between states depending on bias pulse amplitude and duration. We
use an asynchronous control circuit for writing each ReRAM-transistor cell for
the on-demand switching of the FSA. We investigate the impact of the
device-to-device and cycle-to-cycle variations on the cell and show that FSA
transitions can be seamlessly achieved without degradation of performance.
Through extensive experimental evaluation, we demonstrate the implementation of
FSA on 1T1R ReRAM crossbar.
