  Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are
emerging devices, which are well suited to pursue scaling beyond lateral
scaling limitations around 7nm. This work explores the relative merits and
drawbacks of the technology in the context of logic cell design. We describe a
junctionless nanowire technology and associated compact model, which accurately
describes fabricated device behavior in all regions of operations for
transistors based on between 16 and 625 parallel nanowires of diameters between
22 and 50nm. We used this model to simulate the projected performance of
inverter logic gates based on passive load, active load and complementary
topologies and carry out an performance exploration for the number of nanowires
in transistors. In terms of compactness, through a dedicated full 3D layout
design, we also demonstrate a 1.4x reduction in lateral dimensions for the
complementary structure with respect to 7nm FinFET-based inverters.
