  The advancement of Deep Learning (DL) is driven by efficient Deep Neural
Network (DNN) design and new hardware accelerators. Current DNN design is
primarily tailored for general-purpose use and deployment on commercially
viable platforms. Inference at the edge requires low latency, compact and
power-efficient models, and must be cost-effective. Digital processors based on
typical von Neumann architectures are not conducive to edge AI given the large
amounts of required data movement in and out of memory. Conversely,
analog/mixed signal in-memory computing hardware accelerators can easily
transcend the memory wall of von Neuman architectures when accelerating
inference workloads. They offer increased area and power efficiency, which are
paramount in edge resource-constrained environments. In this paper, we propose
AnalogNAS, a framework for automated DNN design targeting deployment on analog
In-Memory Computing (IMC) inference accelerators. We conduct extensive hardware
simulations to demonstrate the performance of AnalogNAS on State-Of-The-Art
(SOTA) models in terms of accuracy and deployment efficiency on various Tiny
Machine Learning (TinyML) tasks. We also present experimental results that show
AnalogNAS models achieving higher accuracy than SOTA models when implemented on
a 64-core IMC chip based on Phase Change Memory (PCM). The AnalogNAS search
code is released: https://github.com/IBM/analog-nas
