  This report introduces a shared resource arbitration scheme "DPQ - Dynamic
Priority Queue" which provides bandwidth guarantees and low worst case latency
to each master in an MPSoC. Being a non-trivial candidate for timing analysis,
SDRAM has been chosen as a showcase, but the approach is valid for any shared
resource arbitration.
  Due to its significant cost, data rate and physical size advantages, SDRAM is
a potential candidate for cost sensitive, safety critical and space conserving
systems. The variable access latency is a major drawback of SDRAM that induces
largely over estimated Worst Case Execution Time (WCET) bounds of applications.
In this report we present the DPQ together with an algorithm to predict the
shared SDRAM's worst case latencies. We use the approach to calculate WCET
bounds of six hardware tasks executing on an Altera Cyclone III FPGA with
shared DDR2 memory. The results show that the DPQ is a fair arbitration scheme
and produces low WCET bounds.
