  All-digital basestation (BS) architectures enable superior spectral
efficiency compared to hybrid solutions in massive multi-user MIMO systems.
However, supporting large bandwidths with all-digital architectures at mmWave
frequencies is challenging as traditional baseband processing would result in
excessively high power consumption and large silicon area. The
recently-proposed concept of finite-alphabet equalization is able to address
both of these issues by using equalization matrices that contain low-resolution
entries to lower the power and complexity of high-throughput matrix-vector
products in hardware. In this paper, we explore two different finite-alphabet
equalization hardware implementations that tightly integrate the memory and
processing elements: (i) a parallel array of multiply-accumulate (MAC) units
and (ii) a bit-serial processing-in-memory (PIM) architecture. Our all-digital
VLSI implementation results in 28nm CMOS show that the bit-serial PIM
architecture reduces the area and power consumption up to a factor of 2x and
3x, respectively, when compared to a parallel MAC array that operates at the
same throughput.
