  Prototyping HPC systems with low-to-mid technology readiness level (TRL)
systems is critical for providing feedback to hardware designers, the system
software team (e.g., compiler developers), and early adopters from the
scientific community. The typical approach to hardware design and HPC system
prototyping often limits feedback or only allows it at a late stage. In this
paper, we present a set of tools for co-designing HPC systems, called software
development vehicles (SDV). We use an innovative RISC-V design as a
demonstrator, which includes a scalar CPU and a vector processing unit capable
of operating large vectors up to 16 kbits. We provide an incremental
methodology and early tangible evidence of the co-design process that provide
feedback to improve both architecture and system software at a very early stage
of system development.
