  In this work, we propose valley-coupled spin-hall memories (VSH-MRAMs) based
on monolayer WSe2. The key features of the proposed memories are (a) the
ability to switch magnets with perpendicular magnetic anisotropy (PMA) via VSH
effect and (b) an integrated gate that can modulate the charge/spin current
(IC/IS) flow. The former attribute results in high energy efficiency (compared
to the Giant-Spin Hall (GSH) effect-based devices with in-plane magnetic
anisotropy (IMA) magnets). The latter feature leads to a compact access
transistor-less memory array design. We experimentally measure the gate
controllability of the current as well as the nonlocal resistance associated
with VSH effect. Based on the measured data, we develop a simulation framework
(using physical equations) to propose and analyze single-ended and differential
VSH effect based magnetic memories (VSH-MRAM and DVSH-MRAM, respectively). At
the array level, the proposed VSH/DVSH-MRAMs achieve 50%/ 11% lower write time,
59%/ 67% lower write energy and 35%/ 41% lower read energy at iso-sense margin,
compared to single ended/differential (GSH/DGSH)-MRAMs. System level evaluation
in the context of general purpose processor and intermittently-powered system
shows up to 3.14X and 1.98X better energy efficiency for the proposed
(D)VSH-MRAMs over (D)GSH-MRAMs respectively. Further, the differential sensing
of the proposed DVSH-MRAM leads to natural and simultaneous in-memory
computation of bit-wise AND and NOR logic functions. Using this feature, we
design a computation-in-memory (CiM) architecture that performs Boolean logic
and addition (ADD) with a single array access. System analysis performed by
integrating our DVSH-MRAM: CiM in the Nios II processor across various
application benchmarks shows up to 2.66X total energy savings, compared to
DGSH-MRAM: CiM.
