  Since the advent of new nanotechnologies, the variability of gate delay due
to process variations has become a major concern. This paper proposes a new
gate delay model that includes impact from both process variations and multiple
input switching. The proposed model uses orthogonal polynomial based
probabilistic collocation method to construct a delay analytical equation from
circuit timing performance. From the experimental results, our approach has
less that 0.2% error on the mean delay of gates and less than 3% error on the
standard deviation.
