  In this paper,we present Generic System Verilog Universal Verification
Methodology based Reusable Verification Environment for efficient verification
of Image Signal Processing IP's/SoC's. With the tight schedules on all projects
it is important to have a strong verification methodology which contributes to
First Silicon Success. Deploy methodologies which enforce full functional
coverage and verification of corner cases through pseudo random test scenarios
is required. Also, standardization of verification flow is needed. Previously,
inside imaging group of ST, Specman (e)/Verilog based Verification Environment
for IP/Subsystem level verification and C/C++/Verilog based Directed
Verification Environment for SoC Level Verification was used for Functional
Verification. Different Verification Environments were used at IP level and SoC
level. Different Verification/Validation Methodologies were used for SoC
Verification across multiple sites. Verification teams were also looking for
the ways how to catch bugs early in the design cycle? Thus, Generic System
Verilog Universal Verification Methodology (UVM) based Reusable Verification
Environment is required to avoid the problem of having so many methodologies
and provides a standard unified solution which compiles on all tools. The main
aim of development of this Generic and automatic verification environment is to
develop an efficient and unified verification environment (at IP/Subsystem/SoC
Level) which reuses the already developed Verification components and also
sequences written at IP/Subsystem level can be reused at SoC Level both with
Host BFM and actual Core using Incisive Software Extension (ISX) and Virtual
Register Interface (VRI)/Verification Abstraction Layer (VAL) approaches.
IP-XACT based tools are used for automatically configuring the environment for
various imaging IPs/SoCs.
