  A time-efficient and comprehensive verification is a fundamental part of the
design process for modern computing platforms, and it becomes ever more
important and critical to optimize as the latter get ever more complex.
SupeRFIVe is a methodology for the functional verification of superscalar
processors that leverages an instruction set simulator to validate their
correctness according to a simulation-based approach, interfacing a testbench
for the design under test with the instruction set simulator by means of socket
communication. We demonstrate the effectiveness of the SupeRFIVe methodology by
applying it to verify the functional correctness of a RISC-V dual-issue
superscalar CPU, leveraging the state-of-the-art RISC-V instruction set
simulator Spike and executing a set of benchmark applications from the open
literature.
