  The algorithm-to-hardware High-level synthesis (HLS) tools today are
purported to produce hardware comparable in quality to handcrafted designs,
particularly with user directive driven or domains specific HLS. However, HLS
tools are not readily equipped for when an application/algorithm needs to
scale. We present a (work-in-progress) semi-automated framework to map
applications over a packet-switched network of modules (single FPGA) and then
to seamlessly partition such a network over multiple FPGAs over quasi-serial
links. We illustrate the framework through three application case studies: LDPC
Decoding, Particle Filter based Object Tracking, and Matrix Vector
Multiplication over GF(2). Starting with high-level representations of each
case application, we first express them in an intermediate message passing
formulation, a model of communicating processing elements. Once the processing
elements are identified, these are either handcrafted or realized using HLS.
The rest of the flow is automated where the processing elements are plugged on
to a configurable network-on-chip (CONNECT) topology of choice, followed by
partitioning the 'on-chip' links to work seamlessly across chips/FPGAs.
