  Multi-channel electrophysiology systems for recording of neuronal activity
face significant data throughput limitations, hampering real-time,
data-informed experiments. These limitations impact both experimental
neurobiology research and next-generation neuroprosthetics. We present a novel
solution that leverages the high integration density of 22nm FDSOI CMOS
technology to address these challenges. The proposed highly integrated
programmable System-on-Chip comprises 68-channel 0.41 \textmu W/Ch recording
frontends, spike detectors, 16-channel 0.87-4.39 \textmu W/Ch action potential
and 8-channel 0.32 \textmu W/Ch local field potential codecs, as well as a
MAC-assisted power-efficient processor operating at 25 MHz (5.19 \textmu
W/MHz). The system supports on-chip training processes for compression,
training and inference for neural spike sorting. The spike sorting achieves an
average accuracy of 91.48% or 94.12% depending on the utilized features. The
proposed PSoC is optimized for reduced area (9 mm2) and power. On-chip
processing and compression capabilities free up the data bottlenecks in data
transmission (up to 91% space saving ratio), and moreover enable a fully
autonomous yet flexible processor-driven operation. Combined, these design
considerations overcome data-bottlenecks by allowing on-chip feature extraction
and subsequent compression.
