  Memristors provide a tempting solution for weighted synapse connections in
neuromorphic computing due to their size and non-volatile nature. However,
memristors are unreliable in the commonly used voltage-pulse-based programming
approaches and require precisely shaped pulses to avoid programming failure. In
this paper, we demonstrate a current-limiting-based solution that provides a
more predictable analog memory behavior when reading and writing memristive
synapses. With our proposed design READ current can be optimized by about 19x
compared to the 1T1R design. Moreover, our proposed design saves about 9x
energy compared to the 1T1R design. Our 3T1R design also shows promising write
operation which is less affected by the process variation in MOSFETs and the
inherent stochastic behavior of memristors. Memristors used for testing are
hafnium oxide based and were fabricated in a 65nm hybrid CMOS-memristor
process. The proposed design also shows linear characteristics between the
voltage applied and the resulting resistance for the writing operation. The
simulation and measured data show similar patterns with respect to voltage
pulse-based programming and current compliance-based programming. We further
observed the impact of this behavior on neuromorphic-specific applications such
as a spiking neural network
