  Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power
superconductor logic family. AQFP logic gates are powered and clocked by
dedicated clocking schemes using ac excitation currents to implement an
energy-efficient switching process, adiabatic switching. We have proposed a
low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP
logic gates. In order to test more complex circuits, a serializer/deserializer
(SerDes) should be incorporated into the AQFP circuit under test, since the
number of input/output (I/O) cables is limited by equipment. Therefore, in the
present study we propose and develop a novel SerDes for testing
delay-line-clocked AQFP circuits by combining AQFP and rapid
single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ
hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate
the data storage during serial-to-parallel and parallel-to-serial conversion.
Furthermore, all the component circuits in the hybrid SerDes are clocked by the
identical excitation current to synchronize the AQFP and RSFQ parts. We
fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder,
which is the largest delay-line-clocked circuit ever designed) integrated with
the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that
the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with
only a few I/O cables and is thus a powerful tool for the development of very
large-scale integration AQFP circuits.
