  Safe memory reclamation (SMR) algorithms are crucial for preventing
use-after-free errors in optimistic data structures. SMR algorithms typically
delay reclamation for safety and reclaim objects in batches for efficiency. It
is difficult to strike a balance between performance and space efficiency.
Small batch sizes and frequent reclamation attempts lead to high overhead,
while freeing large batches can lead to long program interruptions and high
memory footprints. An ideal SMR algorithm would forgo batching, and reclaim
memory immediately, without suffering high reclamation overheads. To this end,
we propose Conditional Access: a set of hardware instructions that offer
immediate reclamation and low overhead in optimistic data structures.
Conditional Access harnesses cache coherence to enable threads to efficiently
detect potential use-after-free errors without explicit shared memory
communication, and without introducing additional coherence traffic. We
implement and evaluate Conditional Access in Graphite, a multicore simulator.
Our experiments show that Conditional Access can rival the performance of
highly optimized and carefully tuned SMR algorithms while simultaneously
allowing immediate reclamation. This results in concurrent data structures with
similar memory footprints to their sequential counterparts.
