  In this paper we present an FPGA-based implementation of linear programming
(LP) decoding. LP decoding frames error correction as an optimization problem.
This is in contrast to variants of belief propagation (BP) decoding that view
error correction as a problem of graphical inference. There are many advantages
to taking the optimization perspective: convergence guarantees, improved
performance in certain regimes, and a methodology for incorporating the latest
developments in optimization techniques. However, LP decoding, when implemented
with standard LP solvers, does not easily scale to the blocklengths of modern
error-correction codes. In earlier work, we showed that by drawing on
decomposition methods from optimization theory, specifically the alternating
direction method of multipliers (ADMM), we could build an LP decoding solver
that was competitive with BP, both in terms of performance and speed. We also
observed empirically that LP decoders have much better high-SNR performance in
the "error floor" regime, a trait of particular relevance to optical transport
and storage applications. While our previous implementation was in floating
point, in this paper we report initial results of a fixed-point, hardware-based
realization of our ADMM-LP decoder.
