  Read disturbance in modern DRAM chips is a widespread phenomenon and is
reliably used for breaking memory isolation, a fundamental building block for
building robust systems. RowHammer and RowPress are two examples of read
disturbance in DRAM where repeatedly accessing (hammering) or keeping active
(pressing) a memory location induces bitflips in other memory locations.
Unfortunately, shrinking technology node size exacerbates read disturbance in
DRAM chips over generations. As a result, existing defense mechanisms suffer
from significant performance and energy overheads, limited effectiveness, or
prohibitively high hardware complexity.
  In this paper, we tackle these shortcomings by leveraging the spatial
variation in read disturbance across different memory locations in real DRAM
chips. To do so, we 1) present the first rigorous real DRAM chip
characterization study of spatial variation of read disturbance and 2) propose
Sv\"ard, a new mechanism that dynamically adapts the aggressiveness of existing
solutions based on the row-level read disturbance profile. Our experimental
characterization on 144 real DDR4 DRAM chips representing 10 chip designs
demonstrates a large variation in read disturbance vulnerability across
different memory locations: in the part of memory with the worst read
disturbance vulnerability, 1) up to 2x the number of bitflips can occur and 2)
bitflips can occur at an order of magnitude fewer accesses, compared to the
memory locations with the least vulnerability to read disturbance. Sv\"ard
leverages this variation to reduce the overheads of five state-of-the-art read
disturbance solutions, and thus significantly increases system performance.
