  This paper proposes the implementation of programmable threshold logic gate
(TLG) crossbar array based on modified TLG cells for high speed processing and
computation. The proposed TLG array operation does not depend on input signal
and time pulses, comparing to the existing architectures. The circuit is
implemented using TSMC $180nm$ CMOS technology. The on-chip area and power
dissipation of the simulated $3\times 4$ TLG array is $1463 \mu m^2$ and $425
\mu W$, respectively.
