  We consider practical hardware implementation of Polar decoders. To reduce
latency due to the serial nature of successive cancellation (SC), existing
optimizations improve parallelism with two approaches, i.e., multi-bit decision
or reduced path splitting. In this paper, we combine the two procedures into
one with an error-pattern-based architecture. It simultaneously generates a set
of candidate paths for multiple bits with pre-stored patterns. For rate-1 (R1)
or single parity-check (SPC) nodes, we prove that a small number of
deterministic patterns are required to guarantee performance preservation. For
general nodes, low-weight error patterns are indexed by syndrome in a look-up
table and retrieved in O(1) time. The proposed flip-syndrome-list (FSL) decoder
fully parallelizes all constituent code blocks without sacrificing performance,
thus is suitable for ultra-low-latency applications. Meanwhile, two code
construction optimizations are presented to further reduce complexity and
improve performance, respectively.
