  Low-power potential of mixed-signal design makes it an alluring option to
accelerate Deep Neural Networks (DNNs). However, mixed-signal circuitry suffers
from limited range for information encoding, susceptibility to noise, and
Analog to Digital (A/D) conversion overheads. This paper aims to address these
challenges by offering and leveraging the insight that a vector dot-product
(the basic operation in DNNs) can be bit-partitioned into groups of spatially
parallel low-bitwidth operations, and interleaved across multiple elements of
the vectors. As such, the building blocks of our accelerator become a group of
wide, yet low-bitwidth multiply-accumulate units that operate in the analog
domain and share a single A/D converter. The low-bitwidth operation tackles the
encoding range limitation and facilitates noise mitigation. Moreover, we
utilize the switched-capacitor design for our bit-level reformulation of DNN
operations. The proposed switched-capacitor circuitry performs the group
multiplications in the charge domain and accumulates the results of the group
in its capacitors over multiple cycles. The capacitive accumulation combined
with wide bit-partitioned operations alleviate the need for A/D conversion per
operation. With such mathematical reformulation and its switched-capacitor
implementation, we define a 3D-stacked microarchitecture, dubbed BIHIWE.
