  Two optical data link data transmission Application Specific Integrated
Circuits (ASICs), the baseline and its backup, have been designed for the ATLAS
Liquid Argon (LAr) Calorimeter Phase-I trigger upgrade. The latency of each
ASIC and that of its corresponding receiver implemented in a back-end
Field-Programmable Gate Array (FPGA) are critical specifications. In this
paper, we present the latency measurements and simulation of two ASICs. The
measurement results indicate that both ASICs achieve their design goals and
meet the latency specifications. The consistency between the simulation and
measurements validates the ASIC latency characterization.
