  In recent times, Resistive RAMs (ReRAMs) have gained significant prominence
due to their unique feature of supporting both non-volatile storage and logic
capabilities. ReRAM is also reported to provide extremely low power consumption
compared to the standard CMOS storage devices. As a result, researchers have
explored the mapping and design of diverse applications, ranging from
arithmetic to neuromorphic computing structures to ReRAM-based platforms.
ReVAMP, a general-purpose ReRAM computing platform, has been proposed recently
to leverage the parallelism exhibited in a crossbar structure. However, the
technology mapping on ReVAMP remains an open challenge. Though the technology
mapping with device/area-constraints have been proposed, crossbar constraints
are not considered so far. In this work, we address this problem. Two
technology mapping flows are proposed, considering different runtime-efficiency
trade-offs. Both the mapping flows take crossbar constraints into account and
generate feasible mapping for a variety of crossbar dimensions. Our proposed
algorithms are highly scalable and reveal important design hints for
ReRAM-based implementations.
