  Integrated circuits (ICs) are the foundation of all computing systems. They
comprise high-value hardware intellectual property (IP) that are at risk of
piracy, reverse-engineering, and modifications while making their way through
the geographically-distributed IC supply chain. On the frontier of hardware
security are various design-for-trust techniques that claim to protect designs
from untrusted entities across the design flow. Logic locking is one technique
that promises protection from the gamut of threats in IC manufacturing. In this
work, we perform a critical review of logic locking techniques in the
literature, and expose several shortcomings. Taking inspiration from other
cybersecurity competitions, we devise a community-led benchmarking exercise to
address the evaluation deficiencies. In reflecting on this process, we shed new
light on deficiencies in evaluation of logic locking and reveal important
future directions. The lessons learned can guide future endeavors in other
areas of hardware security.
