  In general when considering cache coherence, write back schemes are the
default. These schemes invalidate all other copies of a data block during a
write. In this paper we propose several hybrid schemes that will switch between
updating and invalidating on processor writes at runtime, depending on program
conditions. We created our own cache simulator on which we could implement our
schemes, and generated data sets from both commercial benchmarks and through
artificial methods to run on the simulator. We analyze the results of running
the benchmarks with various schemes, and suggest further research that can be
done in this area.
