  The increasing demand for heterogeneous functionality in the automotive
industry and the evolution of chip manufacturing processes have led to the
transition from federated to integrated critical real-time embedded systems
(CRTESs). This leads to higher integration challenges of conventional timing
predictability techniques due to access contention on shared resources, which
can be resolved by providing system-level observability and controllability in
hardware. We focus on the interconnect as a shared resource and propose
AXI-REALM, a lightweight, modular, and technology-independent real-time
extension to industry-standard AXI4 interconnects, available open-source.
AXI-REALM uses a credit-based mechanism to distribute and control the bandwidth
in a multi-subordinate system on periodic time windows, proactively prevents
denial of service from malicious actors in the system, and tracks each
manager's access and interference statistics for optimal budget and period
selection. We provide detailed performance and implementation cost assessment
in a 12nm node and an end-to-end functional case study implementing AXI-REALM
into an open-source Linux-capable RISC-V SoC. In a system with a
general-purpose core and a hardware accelerator's DMA engine causing
interference on the interconnect, AXI-REALM achieves fair bandwidth
distribution among managers, allowing the core to recover 68.2 % of its
performance compared to the case without contention. Moreover, near-ideal
performance (above 95 %) can be achieved by distributing the available
bandwidth in favor of the core, improving the worst-case memory access latency
from 264 to below eight cycles. Our approach minimizes buffering compared to
other solutions and introduces only 2.45 % area overhead compared to the
original SoC.
