  This study proposes a new router architecture to improve the performance of
dynamic allocation of virtual channels. The proposed router is designed to
reduce the hardware complexity and to improve power and area consumption,
simultaneously. In the new structure of the proposed router, all of the
controlling components have been implemented sequentially inside the allocator
router modules. This optimizes communications between the controlling
components and eliminates the most of hardware overloads of modular
communications. Eliminating additional communications also reduces the hardware
complexity. In order to show the validity of the proposed design in real
hardware resources, the proposed router has been implemented onto a
Field-Programmable Gate Array (FPGA). Since the implementation of a
Network-on-Chip (NoC) requires certain amount of area on the chip, the
suggested approach is also able to reduce the demand of hardware resources. In
this method, the internal memory of the FPGA is used for implementing control
units. This memory is faster and can be used with specific patterns. The use of
the FPGA memory saves the hardware resources and allows the implementation of
NoC based FPGA.
