  We present the characterization of a readout Application-Specific Integrated
Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC
upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm
CMOS technology, reads out a 16x16 pixel matrix of the Low-Gain Avalanche
Detector (LGAD). The jitter contribution from ETROC is required to be below 40
ps to achieve the 50 ps overall time resolution per hit. The analog readout
circuits in ETROC consist of the preamplifier and the discriminator. The
preamplifier handles the LGAD charge signal with the most probable value of
around 15 fC. The discriminator generates the digital pulse, which provides the
Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width)
information. The prototype of ETROC (ETROC0) that implements a single channel
of analog readout circuits has been evaluated with charge injection. The jitter
of the analog readout circuits, measured from the discriminator's leading edge,
is better than 16 ps for a charge larger than 15 fC with the sensor
capacitance. The time walk resulting from different pulse heights can be
corrected using the TOT measurement. The time resolution distribution has a
standard deviation of 29 ps after the time-walk correction from the charge
injection. At room temperature, the preamplifier's power consumption is
measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode,
respectively. The measured power consumption of the discriminator is 0.84 mW
per pixel. With the ASIC alone or the LGAD sensor, The characterization
performances fulfill the ETL's challenging requirements.
