  SRAM bitcells in retention mode behave as autonomous stochastic nonlinear
dynamical systems. From observation of variability-aware transient noise
simulations, we provide an unidimensional model, fully characterizable by
conventional deterministic SPICE simulations, insightfully explaining the
mechanism of intrinsic noise-induced bit flips. The proposed model is exploited
to, first, explain the reported inaccuracy of existing closed-form
near-equilibrium formulas aimed at predicting the mean time to failure and,
secondly, to propose a closer estimate attractive in terms of CPU time.
