  Natural language interfaces have exhibited considerable potential in the
automation of Verilog generation derived from high-level specifications through
the utilization of large language models, garnering significant attention.
Nevertheless, this paper elucidates that visual representations contribute
essential contextual information critical to design intent for hardware
architectures possessing spatial complexity, potentially surpassing the
efficacy of natural-language-only inputs. Expanding upon this premise, our
paper introduces an open-source benchmark for multi-modal generative models
tailored for Verilog synthesis from visual-linguistic inputs, addressing both
singular and complex modules. Additionally, we introduce an open-source visual
and natural language Verilog query language framework to facilitate efficient
and user-friendly multi-modal queries. To evaluate the performance of the
proposed multi-modal hardware generative AI in Verilog generation tasks, we
compare it with a popular method that relies solely on natural language. Our
results demonstrate a significant accuracy improvement in the multi-modal
generated Verilog compared to queries based solely on natural language. We hope
to reveal a new approach to hardware design in the large-hardware-design-model
era, thereby fostering a more diversified and productive approach to hardware
design.
