  Recent research interest in emerging logic systems based on quantum dots has
been sparked by the experimental demonstration of nanometer-scale logic devices
composed of atomically sized quantum dots made of silicon dangling bonds
(SiDBs), along with the availability of SiQAD, a computer-aided design tool
designed for this technology. Latest design automation frameworks have enabled
the synthesis of SiDB circuits that reach the size of
$32\times10^3\,\text{nm}^{2}$ -- orders of magnitude more complex than their
hand-designed counterparts. However, current SiDB simulation engines do not
take defects into account, which is important to consider for these sizable
systems. This work proposes a formulation for incorporating fixed-charge
simulation into established ground state models to cover an important class of
defects that has a non-negligible effect on nearby SiDBs at the $10\,\text{nm}$
scale and beyond. The formulation is validated by implementing it into SiQAD's
simulation engine and computationally reproducing experiments on multiple
defect types, revealing a high level of accuracy. The new capability is applied
towards studying the tolerance of several established logic gates against the
introduction of a single nearby defect to establish the corresponding minimum
required clearance. These findings are compared against existing metrics to
form a foundation for logic robustness studies.
