  Network-on-Chip (NoC) paradigm has been proposed as an auspicious solution to
handle the strict communication requirements between the increasingly large
number of cores on a single multi and many-core chips. However, NoC systems are
exposed to a variety of manufacturing, design and energetic particles factors
making them vulnerable to permanent (hard) faults and transient (soft) errors.
In this paper, we present a comprehensive soft error and hard fault tolerant
3D-NoC architecture, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC
(3D-FETO). With the aid of adaptive algorithms, 3D-FETO is capable of detecting
and recovering from soft errors occurring in the routing pipeline stages and is
leveraging on reconfigurable components to handle permanent faults occurrence
in links, input buffers, and crossbar. In-depth evaluation results show that
the 3D-FETO system is able to work around different kinds of hard faults and
soft errors while ensuring graceful performance degradation, minimizing the
additional hardware complexity and remaining power-efficient.
