  To run quantum algorithms on emerging gate-model quantum hardware, quantum
circuits must be compiled to take into account constraints on the hardware. For
near-term hardware, with only limited means to mitigate decoherence, it is
critical to minimize the duration of the circuit. We investigate the
application of temporal planners to the problem of compiling quantum circuits
to newly emerging quantum hardware. While our approach is general, we focus on
compiling to superconducting hardware architectures with nearest neighbor
constraints. Our initial experiments focus on compiling Quantum Alternating
Operator Ansatz (QAOA) circuits whose high number of commuting gates allow
great flexibility in the order in which the gates can be applied. That freedom
makes it more challenging to find optimal compilations but also means there is
a greater potential win from more optimized compilation than for less flexible
circuits. We map this quantum circuit compilation problem to a temporal
planning problem, and generated a test suite of compilation problems for QAOA
circuits of various sizes to a realistic hardware architecture. We report
compilation results from several state-of-the-art temporal planners on this
test set. This early empirical evaluation demonstrates that temporal planning
is a viable approach to quantum circuit compilation.
