  Solution processed field-effect transistors based on single crystalline
silicon nanowires (Si NWs) with metal Schottky contacts are demonstrated. The
semiconducting layer was deposited from a nanowire ink formulation at room
temperature. The devices with 230nm thick SiO2 gate insulating layers show
excellent output current-voltage characteristics with early saturation voltages
under 2 volts, constant saturation current and exceptionally low dependence of
saturation voltage with the gate field. Operational principles of these devices
are markedly different from traditional ohmic-contact field-effect transistors
(FETs), and are explained using the source-gated transistor (SGT) concept in
which the semiconductor under the reverse biased Schottky source barrier is
depleted leading to low voltage pinch-off and saturation of drain current.
Device parameters including activation energy are extracted at different
temperatures and gate voltages to estimate the Schottky barrier height for
different electrode materials to establish transistor performance - barrier
height relationships. Numerical simulations are performed using 2D thin-film
approximation of the device structures at various Schottky barrier heights.
Without any adjustable parameters and only assuming low p-doping of the
transistor channel, the modelled data show exceptionally good correlation with
the measured data. From both experimental and simulation results, it is
concluded that source-barrier controlled nanowire transistors have excellent
potential advantages compared with a standard FET including mitigation of
short-channel effects, insensitivity in device operating currents to device
channel length variation, higher on/off ratios, higher gain, lower power
consumption and higher operational speed for solution processable and printable
nanowire electronics.
