  Historically, VLSI designers have focused on increasing the speed and
reducing the area of digital systems. However, the evolution of portable
systems and advanced Deep Sub-Micron fabrication technologies have brought
power dissipation as another critical design factor. Low power design reduces
cooling cost and increases reliability especially for high density systems.
Moreover, it reduces the weight and size of portable devices. The power
dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2 dd and static power is proportional to Vdd,
lowering the supply voltage and device dimensions, the transistor threshold
voltage also has to be scaled down to achieve the required performance. In case
of static power, the power is consumed during the steady state condition i.e
when there are no input/output transitions. Static power has two sources: DC
power and Leakage power. Consecutively to facilitate voltage scaling without
disturbing the performance, threshold voltage has to be minimized. Furthermore
it leads to better noise margins and helps to avoid the hot carrier effects in
short channel devices. In this paper we have been proposed the new CMOS library
for the complex digital design using scaling the supply voltage and device
dimensions and also suggest the methods to control the leakage current to
obtain the minimum power dissipation at optimum value of supply voltage and
transistor threshold. In this paper CMOS Cell library has been implemented
using TSMC (0.18um) and TSMC (90nm) technology using HEP2 tool of IC designing
from Mentor Graphics for various analysis and simulations.
