  This paper examines the performance degradation of a MOS device fabricated on
silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE)
as the channel length is scaled to meet the increasing demand for high-speed
high-performing ULSI applications. The review assesses recent proposals to
circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and
weaknesses specific to each attempt is presented. A new device structure called
the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in
suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length
modulation (CLM) and hot-carrier effects, all of which affect the reliability
of ultra-small geometry MOSFETs, is assessed.
