  A superconducting loop stores persistent current without any ohmic loss,
making it an ideal platform for energy efficient memories. Conventional
superconducting memories use an architecture based on Josephson junctions (JJs)
and have demonstrated access times less than 10 ps and power dissipation as low
as $10^{-19}$ J. However, their scalability has been slow to develop due to the
challenges in reducing the dimensions of JJs and minimizing the area of the
superconducting loops. In addition to the memory itself, complex readout
circuits require additional JJs and inductors for coupling signals, increasing
the overall area. Here, we have demonstrated a superconducting memory based
solely on lithographic nanowires. The small dimensions of the nanowire ensure
that the device can be fabricated in a dense area in multiple layers, while the
high kinetic inductance makes the loop essentially independent of geometric
inductance, allowing it to be scaled down without sacrificing performance. The
memory is operated by a group of nanowire cryotrons patterned alongside the
storage loop, enabling us to reduce the entire memory cell to 3 {\mu}m $\times
$ 7 {\mu}m in our proof-of-concept device. In this work we present the
operation principles of a superconducting nanowire memory (nMem) and
characterize its bit error rate, speed, and power dissipation.
