  Packaging has become a crucial process due to the paradigm shift of More than
Moore. Addressing manufacturing and yield issues is a significant challenge for
modern layout algorithms.
  We propose to use printed circuit board (PCB) placement as a benchmark for
the packaging problem. A maximum-margin formulation is devised to improve the
separation between nets. Our framework includes seed layout proposals, a
coordinate descent-based procedure to optimize routability, and a mixed-integer
linear programming method to legalize the layout. We perform an extensive study
with 14 PCB designs and an open-source router. We show that the placements
produced by NS-place improve routed wirelength by up to 25\%, reduce the number
of vias by up to 50\%, and reduce the number of DRVs by 79\% compared to manual
and wirelength-minimal placements.
