  Superconducting logic is fast and energy-efficient relative to CMOS, but also
fundamental studies are needed to scale up circuits for greater utility.
Recently, ballistic shift registers for single-flux quanta (SFQ) bits were
shown in simulation to allow high-efficiency superconducting gates. However,
these gates are unpowered such that the bits slow after each gate operation and
only a short sequence of gates is possible without added power. Here we show
that a circuit based on an Aharonov-Casher ring can power these shift registers
by boosting the bit velocity to a constant value, despite their unusual bit
states constituted by two polarities of SFQ. As a step in its operation, each
bit state is forced into a different ring arm and then accelerated. The circuit
dynamics depend on various circuit parameters and choices of how to merge the
bit-state paths. One design from each merge design choice is proposed to enable
scaling up to an array of gates by adding serial biasing in a relatively simple
way. We find adequate performance for ballistic logic in terms of boosted
velocity, energy efficiency, and parameter margins. We also discuss the
circuit's classical barriers; in a different regime this relates to the
Aharonov-Casher effect.
