  Progress in quantum computing hardware raises questions about how these
devices can be controlled, programmed, and integrated with existing
computational workflows. We briefly describe several prominent quantum
computational models, their associated quantum processing units (QPUs), and the
adoption of these devices as accelerators within high-performance computing
systems. Emphasizing the interface to the QPU, we analyze instruction set
architectures based on reduced and complex instruction sets, i.e., RISC and
CISC architectures. We clarify the role of conventional constraints on memory
addressing and instruction widths within the quantum computing context.
Finally, we examine existing quantum computing platforms, including the D-Wave
2000Q and IBM Quantum Experience, within the context of future ISA development
and HPC needs.
