  This article describes technology for diagnosing SoC HDL-models, based on
transactional graph. Diagnosis method is focused to considerable decrease the
time of fault detection and memory for storage of diagnosis matrix by means of
forming ternary relations in the form of test, monitor, and functional
component. The following problems are solved: creation of digital system model
in the form of transaction graph and multi-tree of fault detection tables, as
well as ternary matrices for activating functional components in tests,
relative to the selected set of monitors; development of a method for analyzing
the activation matrix to detect the faults with given depth and synthesizing
logic functions for subsequent embedded hardware fault diagnosing.
