  Reliability issues stemming from device level non-idealities of non-volatile
emerging technologies like ferroelectric field-effect transistors (FeFET),
especially at scaled dimensions, cause substantial degradation in the accuracy
of In-Memory crossbar-based AI systems. In this work, we present a
variation-aware design technique to characterize the device level variations
and to mitigate their impact on hardware accuracy employing a Bayesian Neural
Network (BNN) approach. An effective conductance variation model is derived
from the experimental measurements of cycle-to-cycle (C2C) and device-to-device
(D2D) variations performed on FeFET devices fabricated using 28 nm high-$k$
metal gate technology. The variations were found to be a function of different
conductance states within the given programming range, which sharply contrasts
earlier efforts where a fixed variation dispersion was considered for all
conductance values. Such variation characteristics formulated for three
different device sizes at different read voltages were provided as prior
variation information to the BNN to yield a more exact and reliable inference.
Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST
dataset and limited accuracy decline by $\sim$3.8-16.1% for deeper AlexNet
models on CIFAR10 dataset under a wide range of variations corresponding to
different device sizes and read voltages, demonstrates the efficacy of our
proposed device-algorithm co-design technique.
