  In programmers point of view, Datatypes in programming language level have a
simple description but inside hardware, huge machine codes are responsible to
describe type features. Datatype architecture design is a novel approach to
match programming features along with hardware design. In this paper a novel
Data type-Based Code Reducer (TYPELINE) architecture is proposed and
implemented according to significant data types (SDT) of programming languages.
TYPELINE uses TEUs for processing various SDT operations. This architecture
design leads to reducing the number of machine codes, and increases execution
speed, and also improves some parallelism level. This is because this
architecture supports some operation for the execution of Abstract Data Types
in parallel. Also it ensures to maintain data type features and entire
application level specifications using the proposed type conversion unit. This
framework includes compiler level identifying execution modes and memory
management unit for decreasing object read/write in heap memory by ISA support.
This energy-efficient architecture is completely compatible with object
oriented programming languages and in combination mode it can process complex
C++ data structures with respect to parallel TYPELINE architecture support.
