  The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution
to handle the strict communication requirements between the increasingly large
number of cores on a single chip. However, NoC systems are exposed to the
aggressive scaling down of transistors, low operating voltages, and high
integration and power densities, making them vulnerable to permanent (hard)
faults and transient (soft) errors. A hard fault in a NoC can lead to external
blocking, causing congestion across the whole network. A soft error is more
challenging because of its silent data corruption, which leads to a large area
of erroneous data due to error propagation, packet re-transmission, and
deadlock. In this paper, we present the architecture and design of a
comprehensive soft error and hard fault-tolerant 3D-NoC system, named
3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of
efficient mechanisms and algorithms, 3D-FETO is capable of detecting and
recovering from soft errors which occur in the routing pipeline stages and
leverages reconfigurable components to handle permanent faults in links, input
buffers, and crossbars. In-depth evaluation results show that the 3D-FETO
system is able to work around different kinds of hard faults and soft errors,
ensuring graceful performance degradation, while minimizing additional hardware
complexity and remaining power efficient.
