  Sequential logic synthesis can provide better Power-Performance-Area (PPA)
than combinational logic synthesis since it explores a larger solution space.
As the gate cost in advanced technologies keeps rising, sequential logic
synthesis provides a powerful alternative that is gaining momentum in the EDA
community. In this work, we present a new scalable algorithm for
don't-care-based sequential logic synthesis. Our new approach is based on
sequential k-step induction and can apply both redundancy removal and
resubstitution transformations under Sequential Observability Don't Cares
(SODCs). Using SODC-based optimizations with induction is a challenging problem
due to dependencies and alignment of don't cares among the base case and the
inductive case. We propose a new approach utilizing the full power of SODCs
without limiting the solution space. Our algorithm is implemented as part of an
industrial tool and achieves 6.9% average area improvement after technology
mapping when compared to state-of-the-art sequential synthesis methods.
Moreover, all the new sequential optimizations can be verified using
state-of-the-art sequential verification tools.
