  The increased memory demands of workloads is putting high pressure on Last
Level Caches (LLCs). Unfortunately, there is limited opportunity to increase
the capacity of LLCs due to the area and power requirements of the underlying
SRAM technology. Interestingly, emerging Non-Volatile Memory (NVM) technologies
promise a feasible alternative to SRAM for LLCs due to their higher area
density. However, NVMs have substantially higher read and write latencies,
which offset their area density benefit. Although researchers have proposed
methods to tolerate NVM's increased write latency, little emphasis has been
placed on reducing the critical NVM read latency.
  To address this problem, this paper proposes Cloak. Cloak exploits data reuse
in the LLC at the page level, to hide NVM read latency. Specifically, on
certain L1 TLB misses to a page, Cloak transfers LLC-resident data belonging to
the page from the LLC NVM array to a set of small SRAM Page Buffers that will
service subsequent requests to this page. Further, to enable the
high-bandwidth, low-latency transfer of lines of a page to the page buffers,
Cloak uses an LLC layout that accelerates the discovery of LLC-resident cache
lines from the page. We evaluate Cloak with full-system simulations of a 4-core
processor across 14 workloads. We find that, on average, Cloak outperforms an
SRAM LLC by 23.8% and an NVM-only LLC by 8.9% -- in both cases, with negligible
additional area. Further, Cloak's ED^2 is 39.9% and 17.5% lower, respectively,
than these designs.
