  Totally self-checking (TSC) circuits are synthesised with a grid of computers
running a distributed population based stochastic optimisation algorithm. The
presented method is the first to automatically synthesise TSC circuits from
arbitrary logic as all previous methods fail to guarantee the checker is
self-testing (ST) for circuits with limited output codespaces. The circuits
synthesised by the presented method have significantly lower overhead than the
previously reported best for every one of a set of 11 frequently used
benchmarks. Average overhead across the entire set is 23% of duplication and
comparison overhead, compared with an average of 69% for the previous best
reported values across the set. The methodology presented represents a
breakthrough in concurrent error detection (CED). The highly efficient, novel
designs produced are tailored to each circuit's function, rather than being
constrained by a particular modular CED design methodology. Results are
synthesised using two-input gates and are TSC with respect to all gate input
and output stuck-at faults. The method can be used to add CED with or without
modifications to the original logic, and can be generalised to any
implementation technology and fault model. An example circuit is analysed and
rigorously proven to be TSC.
