  We present an FPGA-based readout chip emulator board for the CMS Endcap
Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone
10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips
(ETROCs). Based on the actual ETROC design, the firmware is implemented and
verified. The emulator board is being used for the ETROC digital design
verification and system development.
