  In this article, we investigate the impact of architectural parameters of
array-based DNN accelerators on accelerator's energy consumption and
performance in a wide variety of network topologies. For this purpose, we have
developed a tool that simulates the execution of neural networks on array-based
accelerators and has the capability of testing different configurations for the
estimation of energy consumption and processing latency. Based on our analysis
of the behavior of benchmark networks under different architectural parameters,
we offer a few recommendations for having an efficient yet high performance
accelerator design. Next, we propose a heterogeneous multi-core chip scheme for
deep neural network execution. The evaluations of a selective small search
space indicate that the execution of neural networks on their near-optimal core
configuration can save up to 36% and 67% of energy consumption and energy-delay
product respectively. Also, we suggest an algorithm to distribute the
processing of network's layers across multiple cores of the same type in order
to speed up the computations through model parallelism. Evaluations on
different networks and with the different number of cores verify the
effectiveness of the proposed algorithm in speeding up the processing to
near-optimal values.
