  Software Defined Radio (SDR) platforms are useful tools to design new
wireless technologies or to improve specifications of existing ones. The IEEE
802.11p is the de-facto standard for Wireless Vehicular Ad-hoc NETworks
(VANETs). It has been implemented on GNU Radio SDR [1], which experiences
frames decoding/encoding latency. In this paper an FPGA based SDR is proposed
as a solution to accelerate frame decoding of IEEE 802.11p waveforms. We share
our experience in designing and validating an SDR on the top of real FPGA based
embedded hardware architecture. On the top of an FPGA Zynq platform, we port an
SDR GNU Radio following hardware/software (HW/SW) codesign approach. A real
time profiling of the SDR system shows that the OFDM equalizer with FFT
software function is the most time consuming task of the whole SDR receiver
functions (34.74%). We suggest hardware acceleration of the FFT processing
function using the free logic gates of the FPGA Zynq as a Hardware (HW)
accelerator. The HW OFDM Equalizer with FFT sub-function could accelerate the
SDR chain processing in comparison with a pure software implementation. Our
FPGA based SDR design is a key step toward proposing an embedded SDR. It would
be an alternative for not only the IEEE 802.11p standard but for any OFDM based
SDR.
