  Reconfigurable computing offers a good balance between flexibility and energy
efficiency. When combined with software-programmable devices such as CPUs, it
is possible to obtain higher performance by spatially distributing the
parallelizable sections of an application throughout the reconfigurable device
while the CPU is in charge of control-intensive sections. This work introduces
an elastic Coarse-Grained Reconfigurable Architecture (CGRA) integrated into an
energy-efficient RISC-V-based SoC designed for the embedded domain. The
microarchitecture of CGRA supports conditionals and irregular loops, making it
adaptable to domain-specific applications. Additionally, we propose specific
mapping strategies that enable the efficient utilization of the CGRA for both
simple applications, where the fabric is only reconfigured once (one-shot
kernel), and more complex ones, where it is necessary to reconfigure the CGRA
multiple times to complete them (multi-shot kernels). Large kernels also
benefit from the independent memory nodes incorporated to streamline data
accesses. Due to the integration of CGRA as an accelerator of the RISC-V
processor enables a versatile and efficient framework, providing adaptability,
processing capacity, and overall performance across various applications.
  The design has been implemented in TSMC 65 nm, achieving a maximum frequency
of 250 MHz. It achieves a peak performance of 1.22 GOPs computing one-shot
kernels and 1.17 GOPs computing multi-shot kernels. The best energy efficiency
is 72.68 MOPs/mW for one-shot kernels and 115.96 MOPs/mW for multi-shot
kernels. The design integrates power and clock-gating techniques to tailor the
architecture to the embedded domain while maintaining performance. The best
speed-ups are 17.63x and 18.61x for one-shot and multi-shot kernels. The best
energy savings in the SoC are 9.05x and 11.10x for one-shot and multi-shot
kernels.
