  We study the impact of top SiO2 interlayer thickness on the memory window
(MW) of Si channel ferroelectric field-effect transistor (FeFET) with
TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW
increases with the increasing thickness of the top SiO2 interlayer, and such an
increase exhibits a two-stage linear dependence. The physical origin is the
presence of the different interfacial charges trapped at the top
SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of
endurance characteristics on initial MW. We find that the endurance
characteristic degrades with increasing the initial MW. By inserting a 3.4 nm
SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric
Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is
helpful in the device design of FeFET.
