  Ising Machine is a promising computing approach for solving combinatorial
optimization problems. It is naturally suited for energy-saving and compact
in-memory computing implementations with emerging memories. A na\"ive in-memory
computing implementation of a quadratic Ising Machine requires an array of
coupling weights that grows quadratically with problem size. However, the
resources in such an approach are used inefficiently due to sparsity in
practical optimization problems. We first show that this issue can be addressed
by partitioning a coupling array into smaller sub-arrays. This technique,
however, requires interconnecting subarrays; hence, we developed in-memory
computing architecture for quadratic Ising Machines inspired by island-type
field programmable gate arrays, which is the main contribution of our paper. We
adapt open-source tools to optimize problem embedding and model routing
overhead. Modeling results of benchmark problems for the developed architecture
show up to 60x area improvement and faster operation than the baseline
approach. Finally, we discuss algorithm/circuit co-design techniques for
further improvements.
