  Optical Network-on-Chip (ONoC) is an emerging technology considered as one of
the key solutions for future generation on-chip interconnects. However, silicon
photonic devices in ONoC are highly sensitive to temperature variation, which
leads to a lower efficiency of Vertical-Cavity Surface-Emitting Lasers
(VCSELs), a resonant wavelength shift of Microring Resonators (MR), and results
in a lower Signal to Noise Ratio (SNR). In this paper, we propose a methodology
enabling thermal-aware design for optical interconnects relying on
CMOS-compatible VCSEL. Thermal simulations allow designing ONoC interfaces with
low gradient temperature and analytical models allow evaluating the SNR.
