  We report our work on fabricating lithographically aligned patterned
backgates on thin (50-60$\mu$m) \Roman{roman3}-\Roman{roman5} semiconductor
samples using {\it single sided mask aligners only}. Along with this we also
present a way to photograph both sides of a thin patterned chip using
inexpensive infra-red light emitting diodes (LED) and an inexpensive (consumer)
digital camera. A robust method of contacting both sides of a sample using an
ultrasonic bonder is described. In addition we present a mathematical model to
analyse the variation of the electrochemical potential through the doped layers
and heterojunctions that are normally present in most GaAs based devices. We
utilise the technique and the estimates from our model to fabricate an
electron-hole bilayer device in which each layer is separately contacted and
has tunable densities. The electron and hole layers are separated by barriers
either 25 or 15nm wide. In both cases, the densities can be matched by using
appropriate bias voltages.
