  The number of Digital Signal Processor (DSP) resources available in Field
Programmable Gate Arrays (FPGAs) is often quite limited. Therefore, full
utilization of available DSP resources for the computationally intensive parts
of an algorithm is paramount for optimizing the non-functional properties of an
implementation (i.e., performance, power, and area). The DSPs available in
Xilinx devices implement large bit width operators (i.e. a 48-bit accumulator
or a $18 \times 27$ multiplier). However, using such a DSP for low-precision
quantized data (as is common in image processing or machine learning
applications) leaves the DSP resources underutilized. As a remedy, A method has
been proposed to pack and compute four 4-bit multiplications on a single DSP in
a single clock cycle. This paper presents a generalization of this scheme to
arbitrary bit widths and number of multiplications. We also demonstrate that
the previously proposed approach leads to errors (Mean Absolute Error (MAE) =
0.37). Furthermore, we explain where these errors come from and how they can be
corrected. On top, we introduce a novel approximate method called "Overpacking"
which allows to squeeze even more multiplications into a single DSP at the cost
of small errors (MAE = 0.47). Overpacking allows to squeeze six 4-bit
multiplications into a single DSP compared to just four in the literature.
Finally, we introduce an alternative method for packing multiple small-bit
width additions into a single 48-bit accumulator for use in applications such
as Spiking Neural Networks.
