  In this paper, spin-orbit torque (SOT) magnetoresistive random-access memory
(MRAM) devices are leveraged to realize sigmoidal neurons and binarized
synapses for a single-cycle analog in-memory computing (IMC) architecture.
First, an analog SOT-MRAM-based neuron bitcell is proposed which achieves a 12x
reduction in power-area-product compared to the previous most power- and
area-efficient analog sigmoidal neuron design. Next, proposed neuron and
synapse bit cells are used within memory subarrays to form an analog IMC-based
multilayer perceptron (MLP) architecture for the MNIST pattern recognition
application. The architecture-level results exhibit that our analog IMC
architecture achieves at least two and four orders of magnitude performance
improvement compared to a mixed-signal analog/digital IMC architecture and a
digital GPU implementation, respectively while realizing a comparable
classification accuracy.
