  Edge-computing requires high-performance energy-efficient embedded systems.
Fixed-function or custom accelerators, such as FFT or FIR filter engines, are
very efficient at implementing a particular functionality for a given set of
constraints. However, they are inflexible when facing application-wide
optimizations or functionality upgrades. Conversely, programmable cores offer
higher flexibility, but often with a penalty in area, performance, and, above
all, energy consumption. In this paper, we propose VWR2A, an architecture that
integrates high computational density and low power memory structures (i.e.,
very-wide registers and scratchpad memories). VWR2A narrows the energy gap with
similar or better performance on FFT kernels with respect to an FFT
accelerator. Moreover, VWR2A flexibility allows to accelerate multiple kernels,
resulting in significant energy savings at the application level.
