  Chiplet-based systems have gained significant attention in recent years due
to their low cost and competitive performance. As the complexity and
compactness of a chiplet-based system increase, careful consideration must be
given to microbump assignments, interconnect delays, and thermal limitations
during the floorplanning stage. This paper introduces RLPlanner, an efficient
early-stage floorplanning tool for chiplet-based systems with a novel fast
thermal evaluation method. RLPlanner employs advanced reinforcement learning to
jointly minimize total wirelength and temperature. To alleviate the
time-consuming thermal calculations, RLPlanner incorporates the developed fast
thermal evaluation method to expedite the iterations and optimizations.
Comprehensive experiments demonstrate that our proposed fast thermal evaluation
method achieves a mean absolute error (MAE) of 0.25 K and delivers over 120x
speed-up compared to the open-source thermal solver HotSpot. When integrated
with our fast thermal evaluation method, RLPlanner achieves an average
improvement of 20.28\% in minimizing the target objective (a combination of
wirelength and temperature), within a similar running time, compared to the
classic simulated annealing method with HotSpot.
