  Increasing investment in computing technologies and the advancements in
silicon technology has fueled rapid growth in advanced driver assistance
systems (ADAS) and corresponding SoC developments. An ADAS SoC represents a
heterogeneous architecture that consists of CPUs, GPUs and artificial
intelligence (AI) accelerators. In order to guarantee its safety and
reliability, it must process massive amount of raw data collected from multiple
redundant sources such as high-definition video cameras, Radars, and Lidars to
recognize objects correctly and to make the right decisions promptly. A domain
specific memory architecture is essential to achieve the above goals. We
present a shared memory architecture that enables high data throughput among
multiple parallel accesses native to the ADAS applications. It also provides
deterministic access latency with proper isolation under the stringent
real-time QoS constraints. A prototype is built and analyzed. The results
validate that the proposed architecture provides close to 100\% throughput for
both read and write accesses generated simultaneously by many accessing masters
with full injection rate. It can also provide consistent QoS to the domain
specific payloads while enabling the scalability and modularity of the design.
