  Soft errors have a significant impact on the circuit reliability at nanoscale
technologies. At the architectural level, soft errors are commonly modeled by a
probabilistic bit-flip model. In developing such abstract fault models, an
important issue to consider is the likelihood of multiple bit errors caused by
particle strikes. This likelihood has been studied to a great extent in
memories, but has not been understood to the same extent in logic circuits. In
this paper, we attempt to quantify the likelihood that a single transient event
can cause multiple bit errors in logic circuits consisting of combinational
gates and flip-flops. In particular, we calculate the conditional probability
of multiple bit-flips given that a single bit flips as a result of the
transient. To calculate this conditional probability, we use a Monte Carlo
technique in which samples are generated using detailed post-layout circuit
simulations. Our experiments on the ISCAS'85 benchmarks and a few other
circuits indicate that, this conditional probability is quite significant and
can be as high as 0.31. Thus we conclude that multiple bit-flips must
necessarily be considered in order to obtain a realistic architectural fault
model for soft errors.
