  Learning of deep neural networks (DNN) using Resistive Processing Unit (RPU)
architecture is energy-efficient as it utilizes dedicated neuromorphic hardware
and stochastic computation of weight updates for in-memory computing. Charge
Trap Flash (CTF) devices can implement RPU-based weight updates in DNNs.
However, prior work has shown that the weight updates (V_T) in CTF-based RPU
are impacted by the non-ideal program time of CTF. The non-ideal program time
is affected by two factors of CTF. Firstly, the effects of the number of input
pulses (N) or pulse width (pw), and secondly, the gap between successive update
pulses (t_gap) used for the stochastic computation of weight updates.
Therefore, the impact of this non-ideal program time must be studied for neural
network training simulations. In this study, Firstly, we propose a pulse-train
design compensation technique to reduce the total error caused by non-ideal
program time of CTF and stochastic variance of a network. Secondly, we simulate
RPU-based DNN with non-ideal program time of CTF on MNIST and Fashion-MNIST
datasets. We find that for larger N (~1000), learning performance approaches
the ideal (software-level) training level and, therefore, is not much impacted
by the choice of t_gap used to implement RPU-based weight updates. However, for
lower N (<500), learning performance depends on T_gap of the pulses. Finally,
we also performed an ablation study to isolate the causal factor of the
improved learning performance. We conclude that the lower noise level in the
weight updates is the most likely significant factor to improve the learning
performance of DNN. Thus, our study attempts to compensate for the error caused
by non-ideal program time and standardize the pulse length (N) and pulse gap
(t_gap) specifications for CTF-based RPUs for accurate system-level on-chip
training.
