  The logarithmic and anti-logarithmic converters are realized with the
piecewise linear approximation method, which is implemented by the
shift-and-add architecture. This brief utilizes the similarities of Log and
Antilog functions so that the adder tree block and multiplexer block can be
shared by the Log and Antilog converters. As a result, the Antilog function can
be implemented by the Log converter at the cost of additional 14% area and 6%
latency. It implies the shift-and-add architecture can approximate multiple
similar nonlinear functions with a slightly hardware cost. In addition, this
brief proposes a set of formulas to predict the area and latency of
shift-and-add architecture with different quantized coefficients that can
facilitate the finding of a trade-off point in the Latency-Area-Precision
space.
