  Reliability is an important requirement for both communication and storage
systems. Due to continuous scale down of technology multiple adjacent bits
error probability increases. The data may be corrupted due soft errors. Error
correction codes are used to detect and correct the errors. In this paper,
design of single error correction-double error detection (SEC-DED) and single
error correction-double error detection-double adjacent error correction
(SEC-DED-DAEC) codes of different data lengths have been proposed. Proposed
SEC-DED and SEC-DED-DAEC codes require lower delay and power compared to
existing coding schemes. Area complexity in terms of logic gates of proposed
and existing codes have been presented. ASIC-based synthesis results show a
notable reduction compared to existing SEC-DED codes. All the codec
architectures are synthesized on ASIC platform. Performances of different
SEC-DED-DAEC codes are tabulated in terms of area, power and delay.
