  In this paper, we describe a design of a mixed signal circuit for a binary
neuron (a.k.a perceptron, threshold logic gate) and a methodology for
automatically embedding such cells in ASICs. The binary neuron, referred to as
an FTL (flash threshold logic) uses floating gate or flash transistors whose
threshold voltages serve as a proxy for the weights of the neuron. Algorithms
for mapping the weights to the flash transistor threshold voltages are
presented. The threshold voltages are determined to maximize both the
robustness of the cell and its speed. The performance, power, and area of a
single FTL cell are shown to be significantly smaller (79.4%), consume less
power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic
equivalents. Also included are the architecture and the algorithms to program
the flash devices of an FTL. The FTL cells are implemented as standard cells,
and are designed to allow commercial synthesis and P&R tools to automatically
use them in synthesis of ASICs. Substantial reductions in area and power
without sacrificing performance are demonstrated on several ASIC benchmarks by
the automatic embedding of FTL cells. The paper also demonstrates how FTL cells
can be used for fixing timing errors after fabrication.
