  Bayesian inference is an effective approach for solving statistical learning
problems, especially with uncertainty and incompleteness. However, Bayesian
inference is a computing-intensive task whose efficiency is physically limited
by the bottlenecks of conventional computing platforms. In this work, a
spintronics based stochastic computing approach is proposed for efficient
Bayesian inference. The inherent stochastic switching behaviors of spintronic
devices are exploited to build stochastic bitstream generator (SBG) for
stochastic computing with hybrid CMOS/MTJ circuits design. Aiming to improve
the inference efficiency, an SBG sharing strategy is leveraged to reduce the
required SBG array scale by integrating a switch network between SBG array and
stochastic computing logic. A device-to-architecture level framework is
proposed to evaluate the performance of spintronics based Bayesian inference
system (SPINBIS). Experimental results on data fusion applications have shown
that SPINBIS could improve the energy efficiency about 12X than MTJ-based
approach with 45% design area overhead and about 26X than FPGA-based approach.
