  Phase-locked loops (PLL), Costas loops and other synchronizing circuits are
featured by the presence of a nonlinear phase detector, described by a periodic
nonlinearity. In general, nonlinearities can cause complex behavior of the
system such multi-stability and chaos. However, even phase locking may be
guaranteed under any initial conditions, the transient behavior of the circuit
can be unsatisfactory due to the cycle slipping. Growth of the phase error
caused by cycle slipping is undesirable, leading e.g. to demodulation and
decoding errors. This makes the problem of estimating the phase error
oscillations and number of slipped cycles in nonlinear PLL-based circuits
extremely important for modern telecommunications. Most mathematical results in
this direction, available in the literature, examine the probability density of
the phase error and expected number of slipped cycles under stochastic noise in
the signal. At the same time, cycle slipping occurs also in deterministic
systems with periodic nonlinearities, depending on the initial conditions,
properties of the linear part and the periodic nonlinearity and other factors
such as delays in the loop. In the present paper we give analytic estimates for
the number of slipped cycles in PLL-based systems, governed by
integro-differential equations, allowing to capture effects of high-order
dynamics, discrete and distributed delays. We also consider the effects of
singular small parameter perturbations on the cycle slipping behavior.
