  Noisy intermediate-scale quantum (NISQ) devices seek to achieve quantum
advantage over classical systems without the use of full quantum error
correction. We propose a NISQ processor architecture using a qubit `pipeline'
in which all run-time control is applied globally, reducing the required number
and complexity of control and interconnect resources. This is achieved by
progressing qubit states through a layered physical array of structures which
realise single and two-qubit gates. Such an approach lends itself to NISQ
applications such as variational quantum eigensolvers which require numerous
repetitions of the same calculation, or small variations thereof. In exchange
for simplifying run-time control, a larger number of physical structures is
required for shuttling the qubits as the circuit depth now corresponds to an
array of physical structures. However, qubit states can be `pipelined' densely
through the arrays for repeated runs to make more efficient use of physical
resources. We describe how the qubit pipeline can be implemented in a silicon
spin-qubit platform, to which it is well suited to due to the high qubit
density and scalability. In this implementation, we describe the physical
realisation of single and two qubit gates which represent a universal gate set
that can achieve fidelities of $\mathcal{F} \geq 0.9999$, even under typical
qubit frequency variations.
