  Data breaches and cyberattacks represent a severe problem in higher education
institutions and universities that can result in illegal access to sensitive
information and data loss. To enhance the security of data transmission,
Intrusion Prevention Systems (IPS, i.e., firewalls) and Intrusion Detection
Systems (IDS, i.e., packet sniffers) are used to detect potential threats in
the exchanged data. IPSs and IDSs are usually designed as software programs
running on a server machine. However, when the speed of exchanged data is too
high, this solution can become unreliable. In this case, IPSs and IDSs designed
on a real hardware platform, such as ASICs and FPGAs, represent a more reliable
solution. This paper presents a packet sniffer that was designed using a
commercial FPGA development board. The system can support a data throughput of
10 Gbit/s with preliminary results showing that the speed of data transmission
can be reliably extended to 100 Gbit/s. The designed system is highly
configurable by the user and can enhance the data protection of information
transmitted using the Ethernet protocol. It is particularly suited for the
security of universities and research centers, where point-to-point network
connections are dominant and large amount of sensitive data are shared among
different hosts.
