  The ever-increasing quest for data-level parallelism and variable precision
in ubiquitous multimedia and Deep Neural Network (DNN) applications has
motivated the use of Single Instruction, Multiple Data (SIMD) architectures. To
alleviate energy as their main resource constraint, approximate computing has
re-emerged,albeit mainly specialized for their Application-Specific Integrated
Circuit (ASIC) implementations. This paper, presents for the first time, an
SIMD architecture based on novel multiplier and divider with tunable accuracy,
targeted for Field-Programmable Gate Arrays (FPGAs). The proposed hybrid
architecture implements Mitchell's algorithms and supports precision
variability from 8 to 32 bits. Experimental results obtained from Vivado,
multimedia and DNN applications indicate superiority of proposed architecture
(both SISD and SIMD) over accurate and state-of-the-art approximate
counterparts. In particular, the proposed SISD divider outperforms the accurate
Intellectual Property (IP) divider provided by Xilinx with 4x higher speed and
4.6x less energy and tolerating only < 0.8% error. Moreover, the proposed SIMD
multiplier-divider supersede accurate SIMD multiplier by achieving up to 26%,
45%, 36%, and 56% improvement in area, throughput, power, and energy,
respectively.
