  The assessment of noise margins and the related probability of failure in
digital cells has growingly become essential, as nano-scale CMOS and FinFET
technologies are confronting reliability issues caused by aging mechanisms,
such as NBTI, and variability in process parameters. The influence of such
phenomena is particularly associated to the Write Noise Margins (WNM) in memory
elements, since a wrong stored logic value can result in an upset of the system
state. In this work, we calculated and compared the effect of process
variations and NBTI aging over the years on the actual WNM of various CMOS and
FinFET based flip-flop cells. The massive transistor-level Monte Carlo
simulations produced both nominal (i.e. mean) values and associated standard
deviations of the WNM of the chosen flip-flops. This allowed calculating the
consequent write failure probability as a function of an input voltage shift on
the flip-flop cells, and assessing a comparison for robustness among different
circuit topologies and technologies.
