  This paper proposes ISDC, a novel feedback-guided iterative system of
difference constraints (SDC) scheduling algorithm for high-level synthesis
(HLS). ISDC leverages subgraph extraction-based low-level feedback from
downstream tools like logic synthesizers to iteratively refine HLS scheduling.
Technical innovations include: (1) An enhanced SDC formulation that effectively
integrates low-level feedback into the linear-programming (LP) problem; (2) A
fanout and window-based subgraph extraction mechanism driving the feedback
cycle; (3) A no-human-in-loop ISDC flow compatible with a wide range of
downstream tools and process design kits (PDKs). Evaluation shows that ISDC
reduces register usage by 28.5% against an industrial-strength open-source HLS
tool.
