  A novel power-efficient analog buffer at liquid helium temperature is
proposed. The proposed circuit is based on an input stage consisting of two
complementary differential pairs to achieve rail-to-rail level tracking.
Results of simulation based on SMIC 0.18um CMOS technology show the high
driving capability and low quiescent power consumption at cryogenic
temperature. Operating at single 1.4 V supply, the circuit could achieve a
slew-rate of +51 V/us and -93 V/us for 10 pF capacitive load. The static power
of the circuit is only 79uW.
