  Protecting intellectual property (IP) has become a serious challenge for chip
designers. Most countermeasures are tailored for CMOS integration and tend to
incur excessive overheads, resulting from additional circuitry or device-level
modifications. On the other hand, power density is a critical concern for
sub-50 nm nodes, necessitating alternate design concepts. Although initially
tailored for error-tolerant applications, imprecise computing has gained
traction as a general-purpose design technique. Emerging devices are currently
being explored to implement ultra-low-power circuits for inexact computing
applications. In this paper, we quantify the security threats of imprecise
computing using emerging devices. More specifically, we leverage the innate
polymorphism and tunable stochastic behavior of spin-orbit torque (SOT)
devices, particularly, the giant spin-Hall effect (GSHE) switch. We enable IP
protection (by means of logic locking and camouflaging) simultaneously for
deterministic and probabilistic computing, directly at the GSHE device level.
We conduct a comprehensive security analysis using state-of-the-art Boolean
satisfiability (SAT) attacks; this study demonstrates the superior resilience
of our GSHE primitive when tailored for deterministic computing. We also
demonstrate how probabilistic computing can thwart most, if not all, existing
SAT attacks. Based on this finding, we propose an attack scheme called
probabilistic SAT (PSAT) which can bypass the defense offered by logic locking
and camouflaging for imprecise computing schemes. Further, we illustrate how
careful application of our GSHE primitive can remain secure even on the
application of the PSAT attack. Finally, we also discuss side-channel attacks
and invasive monitoring, which are arguably even more concerning threats than
SAT attacks.
