  Overlay architectures implemented on FPGA devices have been proposed as a
means to increase FPGA adoption in general-purpose computing. They provide the
benefits of software such as flexibility and programmability, thus making it
easier to build dedicated compilers. However, existing overlays are generic,
resource and power hungry with performance usually an order of magnitude lower
than bare metal implementations. As a result, FPGA overlays have been confined
to research and some niche applications. In this paper, we introduce
Application-Specific FPGA Overlays (AS-Overlays), which can provide bare-metal
performance to FPGA overlays, thus opening doors for broader adoption. Our
approach is based on the automatic extraction of hardware kernels from data
flow applications. Extracted kernels are then leveraged for
application-specific generation of hardware accelerators. Reconfiguration of
the overlay is done with RapidWright which allows to bypass the HDL design
flow. Through prototyping, we demonstrated the viability and relevance of our
approach. Experiments show a productivity improvement up to 20x compared to the
state of the art FPGA overlays, while achieving over 1.33x higher Fmax than
direct FPGA implementation and the possibility of lower resource and power
consumption compared to bare metal.
