  Floorplanning for systems-on-a-chip (SoCs) and its sub-systems is a crucial
and non-trivial step of the physical design flow. It represents a difficult
combinatorial optimization problem. A typical large scale SoC with 120
partitions generates a search-space of nearly 10E250. As novel machine learning
(ML) approaches emerge to tackle such problems, there is a growing need for a
modern benchmark that comprises a large training dataset and performance
metrics that better reflect real-world constraints and objectives compared to
existing benchmarks. To address this need, we present FloorSet -- two
comprehensive datasets of synthetic fixed-outline floorplan layouts that
reflect the distribution of real SoCs. Each dataset has 1M training samples and
100 test samples where each sample is a synthetic floor-plan. FloorSet-Prime
comprises fully-abutted rectilinear partitions and near-optimal wire-length. A
simplified dataset that reflects early design phases, FloorSet-Lite comprises
rectangular partitions, with under 5 percent white-space and near-optimal
wire-length. Both datasets define hard constraints seen in modern design flows
such as shape constraints, edge-affinity, grouping constraints, and
pre-placement constraints. FloorSet is intended to spur fundamental research on
large-scale constrained optimization problems. Crucially, FloorSet alleviates
the core issue of reproducibility in modern ML driven solutions to such
problems. FloorSet is available as an open-source repository for the research
community.
