  Although fabrication capabilities of Silicon Dangling Bonds have rapidly
advanced from manual labor-driven laboratory work to automated manufacturing in
just recent years, sub-nanometer substrate defects still pose a hindrance to
production due to the need for atomic precision. In essence, unpassivated or
missing surface atoms, contaminants, and structural deformations disturb the
fabricated logic or prevent its realization altogether. Moreover, design
automation techniques in this domain have not yet adopted any defect-aware
behavior to circumvent the present obstacles. In this paper, we derive a
surface defect model for design automation from experimentally verified defect
types that we apply to identify sensitivities in an established gate library in
an effort to generate more robust designs. Furthermore, we present an automatic
placement and routing algorithm that considers scanning tunneling microscope
data obtained from physical experiments to lay out dot-accurate circuitry that
is resilient against the presence of atomic surface defects. This culminates in
a holistic evaluation on surface data of varying defect rates that enables us
to quantify the severity of such defects. We project that fabrication
capabilities must achieve defect rates of around 0.1 %, if charged defects can
be completely eliminated, or < 0.1 %, otherwise. This realization sets the pace
for future efforts to scale up this promising circuit technology.
