  Inspired by recent interest in quantum computing and recent studies of cryo
CMOS for control electronics, this paper presents a hybrid
semiconductor-superconductor approach for engineering scalable computing
systems that operate across the gradient between room temperature and the
temperature of a cryogenic payload. Such a hybrid computer architecture would
have unique suitability to quantum computers, scalable sensors, and the quantum
internet. The approach is enabled by Cryogenic Adiabatic Transistor Circuits
(CATCs), a novel way of using adiabatic circuits to substantially reduce
cooling requirements. In a hybrid chip of CATCs and a second technology, such
as Josephson junctions (JJs) or cryo CMOS, the CATCs complement the speed,
power, and density of the second technology as well as becoming a longsought
cryogenic memory. This paper describes higher-level design principles for CATC
hybrids with a quantum computer control system that includes CATC memory, an
FPGA-like logic module that uses CATC for dense configuration logic and JJs for
fast configured logic, and I/O subsystems including microwave modulators and
low frequency control signals.
