  Binary machines are a generalization of Feedback Shift Registers (FSRs) in
which both, feedback and feedforward, connections are allowed and no chain
connection between the register stages is required. In this paper, we present
an algorithm for synthesis of binary machines with the minimum number of stages
for a given degree of parallelization. Our experimental results show that for
sequences with high linear complexity such as complementary, Legendre, or truly
random, parallel binary machines are an order of magnitude smaller than
parallel FSRs generating the same sequence. The presented approach can
potentially be of advantage for any application which requires sequences with
high spectrum efficiency or high security, such as data transmission, wireless
communications, and cryptography.
