  A common theme of data acquisition systems is the transport of data from
digitising front-end modules to stable storage and online analysis. A good
choice today is to base this on the ubiquitous, commercially and cheaply
available Ethernet technology. A firmware building block to turn already the
FPGA of front-end electronics into a TCP data source and UDP control interface
using a data-flow architecture is presented. The overall performance targets
are to be able to saturate a 1 Gbps network link with outbound data, while
using few FPGA resources. The goal is to replace the use of custom data buses
and protocols with ordinary Ethernet equipment. These objectives are achieved
by being just-enough conforming, such that no special drivers are needed in the
PC equipment interfacing with the here presented Fakernet system. An important
design choice is to handle all packet-data internally as 16-bit words, thus
reducing the clock-speed requirements. An advantageous circumstance is that
even at 1 Gbps speeds, for local network segments, the round-trip times are
usually well below 500 microseconds. Thus, less than 50 kiB of unacknowledged
data needs to be in-flight, allowing to saturate a network link without TCP
window scaling. The Fakernet system has so far been shown to saturate a 100
Mbps link at 11.7 MB/s of TCP output data, and able to do 32-bit control
register accesses at over 450 kword/s.
