  In this paper, we develop a analytical model and algorithm for calculating
uneven current distribution in via array structures. We propose a stress time
translation formula and cumulative failure distribution equation to model the
memory effect of electro migration stress or damage on a via array structure.
We develop a method to project via array electromigration (EM) lifetime based
on an arbitrary via failure sequence, and demonstrate that the proposed via
array EM lifetime distribution trend correlates well with experimental results.
