  Printed circuit boards (PCBs) are an integral part of electronic systems.
Hence, verifying their physical integrity in the presence of supply chain
attacks (e.g., tampering and counterfeiting) is of utmost importance. Recently,
tamper detection techniques grounded in impedance characterization of PCB's
Power Delivery Network (PDN) have gained prominence due to their global
detection coverage, non-invasive, and low-cost nature. Similar to other
physical verification methods, these techniques rely on the existence of a
physical golden sample for signature comparisons. However, having access to a
physical golden sample for golden signature extraction is not feasible in many
real-world scenarios. In this work, we assess the feasibility of eliminating a
physical golden sample and replacing it with a simulated golden signature
obtained by the PCB design files. By performing extensive simulation and
measurements on an in-house designed PCB, we demonstrate how the parasitic
impedance of the PCB components plays a major role in reaching a successful
verification. Based on the obtained results and using statistical metrics, we
show that we can mitigate the discrepancy between collected signatures from
simulation and measurements.
