  Transaction-Level Verilog (TL-Verilog) is an emerging extension to
SystemVerilog that supports a new design methodology, called transaction-level
design. A transaction, in this methodology, is an entity that moves through
structures like pipelines, arbiters, and queues, A transaction might be a
machine instruction, a flit of a packet, or a memory read/write. Transaction
logic, like packet header decode or instruction execution, that operates on the
transaction can be placed anywhere along the transaction's flow. Tools produce
the logic to carry signals through their flows to stitch the transaction logic.
  We implemented a small library of TL-Verilog flow components, and we
illustrate the use of these components in a top-down design methodology. We
construct a hypothetical microarchitecture simply by instantiating components.
Within the flows created by these components, we add combinational transaction
logic, enabling verification activities and performance evaluation to begin. We
then refine the model by positioning the transaction logic within its flow to
produce a high-quality register-transfer-level (RTL) implementation.
