  The current workloads and applications are highly diversified, facing
critical challenges such as the Power Wall and the Memory Wall Problem.
Different strategies over the multiple levels of Caches have evolved to
mitigate these problems. Also, to work with such diversified applications, the
Asymmetric Multi-Core Processor (AMP) presents itself as a viable solution. In
this paper, we study the performance of L2 and Last Level Cache for different
cache partitions against various AMP configurations. In addition, this study
investigates the optimal cache partitioning for a collection of Multi-threaded
benchmarks from PARSEC and SPLASH2 benchmark suites under medium-sized inputs.
We have studied the effect of block replacement strategies and their impact on
the key metrics such as total on-chip power consumption and L2 \& LLC Miss
rates. Our study presents an intermediate cache design for AMPs between the two
extremities of fully shared and fully private L2 \& LLC level Cache, which
helps achieve the desired power values and optimal cache miss penalties.
