  In this paper, we introduce SCRAMBLE, as a novel logic locking solution for
sequential circuits while the access to the scan chain is restricted. The
SCRAMBLE could be used to lock an FSM by hiding its state transition graph
(STG) among a large number of key-controlled false transitions. Also, it could
be used to lock sequential circuits (sequential datapath) by hiding the timing
paths' connectivity among a large number of key-controlled false connections.
Besides, the structure of SCRAMBLE allows us to engage this scheme as a new
scan chain locking solution by hiding the correct scan chain sequence among a
large number of the key-controlled false sequences. We demonstrate that the
proposed scheme resists against both (1) the 2-stage attacks on FSM, and (2)
SAT attacks integrated with unrolling as well as bounded-model-checking. We
have discussed two variants of SCRAMBLE: (I) Connectivity SCRAMBLE
(SCRAMBLE-C), and (b) Logic SCRAMBLE (SCRAMBLE-L). The SCRAMBLE-C relies on the
SAT-hard and key-controlled modules that are built using near non-blocking
logarithmic switching networks. The SCRAMBLE-L uses input multiplexing
techniques to hide a part of the FSM in a memory. In the result section, we
describe the effectiveness of each variant against state-of-the-art attacks.
