  Chip placement has been one of the most time consuming task in any semi
conductor area, Due to this negligence, many projects are pushed and chips
availability in real markets get delayed. An engineer placing macros on a chip
also needs to place it optimally to reduce the three important factors like
power, performance and time. Looking at these prior problems we wanted to
introduce a new method using Reinforcement Learning where we train the model to
place the nodes of a chip netlist onto a chip canvas. We want to build a neural
architecture that will accurately reward the agent across a wide variety of
input netlist correctly.
