  Many convolutional neural network (CNN) accelerators face performance- and
energy-efficiency challenges which are crucial for embedded implementations,
due to high DRAM access latency and energy. Recently, some DRAM architectures
have been proposed to exploit subarray-level parallelism for decreasing the
access latency. Towards this, we present a design space exploration methodology
to study the latency and energy of different mapping policies on different DRAM
architectures, and identify the pareto-optimal design choices. The results show
that the energy-efficient DRAM accesses can be achieved by a mapping policy
that orderly prioritizes to maximize the row buffer hits, bank- and
subarray-level parallelism.
