  Graph Neural Networks (GNNs) are becoming increasingly popular for
vision-based applications due to their intrinsic capacity in modeling
structural and contextual relations between various parts of an image frame. On
another front, the rising popularity of deep vision-based applications at the
edge has been facilitated by the recent advancements in heterogeneous
multi-processor Systems on Chips (MPSoCs) that enable inference under
real-time, stringent execution requirements. By extension, GNNs employed for
vision-based applications must adhere to the same execution requirements. Yet
contrary to typical deep neural networks, the irregular flow of graph learning
operations poses a challenge to running GNNs on such heterogeneous MPSoC
platforms. In this paper, we propose a novel unified design-mapping approach
for efficient processing of vision GNN workloads on heterogeneous MPSoC
platforms. Particularly, we develop MaGNAS, a mapping-aware Graph Neural
Architecture Search framework. MaGNAS proposes a GNN architectural design space
coupled with prospective mapping options on a heterogeneous SoC to identify
model architectures that maximize on-device resource efficiency. To achieve
this, MaGNAS employs a two-tier evolutionary search to identify optimal GNNs
and mapping pairings that yield the best performance trade-offs. Through
designing a supernet derived from the recent Vision GNN (ViG) architecture, we
conducted experiments on four (04) state-of-the-art vision datasets using both
(i) a real hardware SoC platform (NVIDIA Xavier AGX) and (ii) a
performance/cost model simulator for DNN accelerators. Our experimental results
demonstrate that MaGNAS is able to provide 1.57x latency speedup and is 3.38x
more energy-efficient for several vision datasets executed on the Xavier MPSoC
vs. the GPU-only deployment while sustaining an average 0.11% accuracy
reduction from the baseline.
