  In a superscalar processor, instructions of various types flow through an
execution pipeline, traversing hardware resources which are mostly shared among
many different instruction types. A notable exception to shared pipeline
resources is the collection of functional units, the hardware that performs
specific computations. In a trade-off of cost versus performance, a pipeline
designer must decide how many of each type of functional unit to place in a
processor's pipeline. In this paper, we model a superscalar processor's issue
queue and functional units as a novel queuing network. We treat the issue queue
as a finite-sized waiting area and the functional units as servers. In addition
to common queuing problems, customers of the network share the queue but wait
for specific servers to become ready (e.g., addition instructions wait for
adders). Furthermore, the customers in this queue are not necessary ready for
service, since instructions may be waiting for operands. In this paper we model
a novel queuing network that provides a solution to the expected queue length
of each type of instruction. This network and its solution can also be
generalized to other problems, notably other resource-allocation issues that
arise in superscalar pipelines.
