  Computationally expensive temperature and power grid analyses are required
during the design cycle to guide IC design. This paper employs encoder-decoder
based generative (EDGe) networks to map these analyses to fast and accurate
image-to-image and sequence-to-sequence translation tasks. The network takes a
power map as input and outputs the corresponding temperature or IR drop map. We
propose two networks: (i) ThermEDGe: a static and dynamic full-chip temperature
estimator and (ii) IREDGe: a full-chip static IR drop predictor based on input
power, power grid distribution, and power pad distribution patterns. The models
are design-independent and must be trained just once for a particular
technology and packaging solution. ThermEDGe and IREDGe are demonstrated to
rapidly predict the on-chip temperature and IR drop contours in milliseconds
(in contrast with commercial tools that require several hours or more) and
provide an average error of 0.6% and 0.008% respectively.
