  The design of systems implementing low precision neural networks with
emerging memories such as resistive random access memory (RRAM) is a major lead
for reducing the energy consumption of artificial intelligence (AI). Multiple
works have for example proposed in-memory architectures to implement low power
binarized neural networks. These simple neural networks, where synaptic weights
and neuronal activations assume binary values, can indeed approach
state-of-the-art performance on vision tasks. In this work, we revisit one of
these architectures where synapses are implemented in a differential fashion to
reduce bit errors, and synaptic weights are read using precharge sense
amplifiers. Based on experimental measurements on a hybrid 130 nm CMOS/RRAM
chip and on circuit simulation, we show that the same memory array architecture
can be used to implement ternary weights instead of binary weights, and that
this technique is particularly appropriate if the sense amplifier is operated
in near-threshold regime. We also show based on neural network simulation on
the CIFAR-10 image recognition task that going from binary to ternary neural
networks significantly increases neural network performance. These results
highlight that AI circuits function may sometimes be revisited when operated in
low power regimes.
