  Polynomial multiplication is a bottleneck in most of the public-key
cryptography protocols, including Elliptic-curve cryptography and several of
the post-quantum cryptography algorithms presently being studied. In this
paper, we present a library of various large integer polynomial multipliers to
be used in hardware cryptocores. Our library contains both digitized and
non-digitized multiplier flavours for circuit designers to choose from. The
library is supported by a C++ generator that automatically produces the
multipliers' logic in Verilog HDL that is amenable for FPGA and ASIC designs.
Moreover, for ASICs, it also generates configurable and parameterizable
synthesis scripts. The features of the generator allow for a quick generation
and assessment of several architectures at the same time, thus allowing a
designer to easily explore the (complex) optimization search space of
polynomial multiplication.
