  The design space of current quantum computers is expansive with no obvious
winning solution. This leaves practitioners with a clear question: "What is the
optimal system configuration to run an algorithm?". This paper explores
hardware design trade-offs across NISQ systems to guide algorithm and hardware
design choices. The evaluation is driven by algorithmic workloads and algorithm
fidelity models which capture architectural features such as gate expressivity,
fidelity, and crosstalk. We also argue that the criteria for gate design and
selection should be extended from maximizing average fidelity to a more
comprehensive approach that takes into account the gate expressivity with
respect to algorithmic structures. We consider native entangling gates (CNOT,
ECR, CZ, ZZ, XX, Sycamore, $\sqrt{\text{iSWAP}}$), proposed gates (B Gate,
$\sqrt[4]{\text{CNOT}}$, $\sqrt[8]{\text{CNOT}}$), as well as parameterized
gates (FSim, XY). Our methodology is driven by a custom synthesis driven
circuit compilation workflow, which is able to produce minimal circuit
representations for a given system configuration. By providing a method to
evaluate the suitability of algorithms for hardware platforms, this work
emphasizes the importance of hardware-software co-design for quantum computing.
