  The paper describes the design and hardware implementation of 32-bit
encrypted MIPS processor based on MIPS pipeline architecture. The organization
of pipeline stages in such a way that pipeline can be clocked at high
frequency. Encryption and Decryption blocks of data encryption standard (DES)
cryptosystem and dependency among themselves are explained in detail with the
help of block diagram. In order to increase the processor functionality and
performance, especially for security applications we include three new
instructions 32-bit LKLW, LKUW and CRYPT. The design has been synthesized at
40nm process technology targeting using Xilinx Virtex-6 device. The encrypted
MIPS pipeline processor can work at 218MHz at synthesis level and 744MHz at
simulation level.
