  Approximate computing is a promising approach to reduce the power, delay, and
area in hardware design for many error-resilient applications such as machine
learning (ML) and digital signal processing (DSP) systems, in which multipliers
usually are key arithmetic units. Due to the underlying architectural
differences between ASICs and FPGAs, existing ASIC-based approximate
multipliers do not offer symmetrical gains when they are implemented by FPGA
resources. In this paper, we propose AMG, an open-source automated approximate
multiplier generator for FPGAs driven by Bayesian optimization (BO) with
parallel evaluation. The proposed method simplifies the exact half adders (HAs)
for the initial partial product (PP) compression in a multiplier while
preserving coarse-grained additions for the following accumulation. The
generated multipliers can be effectively mapped to lookup tables (LUTs) and
carry chains provided by modern FPGAs, reducing hardware costs with acceptable
errors. Compared with 1167 multipliers from previous works, our generated
multipliers can form a Pareto front with 28.70%-38.47% improvements in terms of
the product of hardware cost and error on average. All source codes, reproduced
multipliers, and our generated multipliers are available at
https://github.com/phyzhenli/AMG.
