  The systolic accelerator is one of the premier architectural choices for DNN
acceleration. However, the conventional systolic architecture suffers from low
PE utilization due to the mismatch between the fixed array and diverse DNN
workloads. Recent studies have proposed flexible systolic array architectures
to adapt to DNN models. However, these designs support only coarse-grained
reshaping or significantly increase hardware overhead. In this study, we
propose ReDas, a flexible and lightweight systolic array that supports dynamic
fine-grained reshaping and multiple dataflows. First, ReDas integrates
lightweight and reconfigurable roundabout data paths, which achieve
fine-grained reshaping using only short connections between adjacent PEs.
Second, we redesign the PE microarchitecture and integrate a set of multi-mode
data buffers around the array. The PE structure enables additional data
bypassing and flexible data switching. Simultaneously, the multi-mode buffers
facilitate fine-grained reallocation of on-chip memory resources, adapting to
various dataflow requirements. ReDas can dynamically reconfigure to up to 129
different logical shapes and 3 dataflows for a 128x128 array. Finally, we
propose an efficient mapper to generate appropriate configurations for each
layer of DNN workloads. Compared to the conventional systolic array, ReDas can
achieve about 4.6x speedup and 8.3x energy-delay product (EDP) reduction.
