  Polar codes are a new class of block codes with an explicit construction that
provably achieve the capacity of various communications channels, even with the
low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more
complex successive-cancellation list (SCL) decoding algorithm is gathering more
attention lately as it significantly improves the error-correction performance
of short- to moderate-length polar codes, especially when they are concatenated
with a cyclic redundancy check code. However, as SCL decoding explores several
decoding paths, existing hardware implementations tend to be significantly
slower than SC-based decoders. In this paper, we show how the unrolling
technique, which has already been used in the context of SC decoding, can be
adapted to SCL decoding yielding a multi-Gbps SCL-based polar decoder with an
error-correction performance that is competitive when compared to an LDPC code
of similar length and rate. Post-place-and-route ASIC results for 28 nm CMOS
are provided showing that this decoder can sustain a throughput greater than 10
Gbps at 468 MHz with an energy efficiency of 7.25 pJ/bit.
