  This paper presents a memory efficient architecture that implements the
Multi-Scale Line Detector (MSLD) algorithm for real-time retinal blood vessel
detection in fundus images on a Zynq FPGA. This implementation benefits from
the FPGA parallelism to drastically reduce the memory requirements of the MSLD
from two images to a few values. The architecture is optimized in terms of
resource utilization by reusing the computations and optimizing the bit-width.
The throughput is increased by designing fully pipelined functional units. The
architecture is capable of achieving a comparable accuracy to its software
implementation but 70x faster for low resolution images. For high resolution
images, it achieves an acceleration by a factor of 323x.
