  Generators of arithmetic circuits can automatically deliver various
implementations of arithmetic circuits that show different tradeoffs between
the key circuit parameters (delay, area, power consumption). However, existing
(freely-)available generators are limited if more complex circuits with a
hierarchical structure and additional architecture optimization are requested.
Furthermore, they support only a few output formats. In order to overcome the
above-mentioned limitations, we developed a new generator of arithmetic
circuits called ArithsGen. ArithsGen can generate specific architectures of
signed and unsigned adders and multipliers using basic building elements such
as wires and gates. Compared to existing generators, the user can, for example,
specify the type of adders used in multipliers. The tool supports various
outputs formats (Verilog, BLIF, C/C++, or integer netlists). ArithsGen was
evaluated in the synthesis and optimization of generic customizable accurate
and approximate adders and multipliers. Furthermore, we used the circuits
generated by ArithsGen as seeds for a tool developed to automatically create
approximate implementations of arithmetic circuits. We show that different
initial circuits (generated by ArithsGen) significantly impact the properties
of these approximate implementations. The tool is available online at
https://github.com/ehw-fit/ariths-gen.
