  Complementary-metal-oxide-semiconductor (CMOS) is the most widely spread
technology for integrated circuits fabrication. Each foundry offers different
technology nodes that are characterized by the minimum feature size, which is
the smallest dimension that can be fabricated using photo-lithography with the
required precision. The minimum feature size ranges from 350nm to 5nm. Each
designer has to select the best technology for implementing their designs, and
the designer has to specify the foundry, the technology node, and any
additional features like the number of metal layers, and MIM capacitor density.
In this white paper, we will describe the various trade-offs while selecting
the optimal technology node for power management. You will learn 1)
Semiconductor products business models 2) fabrication technologies features 3)
how to select the optimal technology node for fabrication according to the
application, 4) how the cost of a silicon chip scales with the sales of your
design.
