  Energy efficiency is a growing concern for modern computing, especially for
HPC due to operational costs and the environmental impact. We propose a
methodology to find energy-optimal frequency and number of active cores to run
single-node HPC applications using an application-agnostic power model of the
architecture and an architecture-aware performance model of the application. We
characterize the application performance using Support Vector Regression. The
power consumption is estimated by modeling CMOS dynamic and static power
without knowledge of the application. The energy-optimal configuration is
estimated by minimizing the product of the power model and the performance
model's outcomes. Results for four PARSEC applications with five different
inputs show that the proposed approach used about 14X less energy when compared
to the worst case of the default Linux DVFS governor. For the best case of the
DVFS scheme, 23% savings were observed, with an overall average of 6% less
energy.
