  A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realized
in a standard digital 0.13 $\mu$m CMOS copper technology is presented.
Employing capacitive interpolation gives various advantages when designing for
low power: no need for a reference resistor ladder, implicit sample-and-hold
operation, no edge effects in the interpolation network (as compared to
resistive interpolation), and a very low input capacitance of only 400fF, which
leads to an easily drivable analog converter interface. Operating at 1.2GSps
the ADC achieves an effective resolution bandwidth (ERBW) of 700MHz, while
consuming 160mW of power. At 600MSps we achieve an ERBW of 600MHz with only
90mW power consumption, both from a 1.5V supply. This corresponds to
outstanding Figure-of-Merit numbers (FoM) of 2.2 and 1.5pJ/convstep,
respectively. The module area is 0.12mm^2.
