  This paper describes a pipelined analog-to-digital converter (ADC) employing
a power and area efficient architecture. The adjacent stages of a pipeline
share operational amplifiers. In order to keep accuracy of the amplifiers in
the first stages, they use a partially sharing technique. The feature of the
proposed scheme is that it also shares the comparators. The capacitors of the
first stages of a pipeline are scaled down along a pipeline for a further
reducing the chip area and its power consumption. A 9-bit 20-MSamples/s ADC,
intended for use in multi-channel mixed-signal chips, has been fabricated via
Europractice in a 180-nm CMOS process from UMC. The prototype ADC shows a
spurious-free dynamic range of 58.5 dB at a sample rate of 20 MSamples/s, when
a 400 kHz input signal with a swing of 1 dB below full scale is applied. The
effective number of bits is 8.0 at the same conditions. ADC occupies an active
area of 0.4 mm2 and dissipates 8.6 mW at a 1.8 V supply.
