  Stochastic magnetic tunnel junctions (s-MTJ) is a promising component of
probabilistic bit (p-bit), which plays a pivotal role in probabilistic
computers. For a standard cell structure of the p-bit, s-MTJ is desired to be
insensitive to voltage across the junction over several hundred millivolts. In
conventional s-MTJs with a reference layer having a fixed magnetization
direction, however, the stochastic output significantly varies with the voltage
due to spin-transfer torque (STT) acting on the stochastic free layer. In this
work, we study a s-MTJ with a "double-free-layer" design theoretically proposed
earlier, in which the fixed reference layer of the conventional structure is
replaced by another stochastic free layer, effectively mitigating the influence
of STT on the stochastic output. We show that the key device property
characterized by the ratio of relaxation times between the high- and
low-resistance states is one to two orders of magnitude less sensitive to bias
voltage variations compared to conventional s-MTJs when the top and bottom free
layers are designed to possess the same effective thickness. This work opens a
pathway for reliable, nanosecond-operation, high-output, and scalable
spintronics-based p-bits.
