  Turbo code is a great achievement in the field of communication system. It
can be created by connecting a turbo encoder and a decoder serially. A Turbo
encoder is build with parallel concatenation of two simple convolutional codes.
By varying the number of memory element (encoder configuration), code rate (1/2
or 1/3), block size of data and iteration, we can achieve better BER
performance. Turbo code also consists of interleaver unit and its BER
performance also depends on interleaver size. Turbo Decoder can be implemented
using different algorithm, but Log -MAP decoding algorithm is less
computationaly complex with respect to MAP (maximux a posteriori) algorithm,
without compromising its BER performance, nearer to Shannon limit. A register
transfer level (RTL) turbo encoder is designed and simulated using VHDL (Very
high speed integrated circuit Hardware Description Language). In this paper
VHDL model of different turbo encoder are implemented using Log MAP decoder and
its performance are compared and verified with corresponding MATLAB simulated
results.
