  With transistor scaling reaching its limits, interposer-based integration of
dies (chiplets) is gaining traction. Such an interposer-based integration
enables finer and tighter interconnect pitch than traditional
system-on-packages and offers two key benefits: 1. It reduces design-to-market
time by bypassing the time-consuming process of verification and fabrication.
2. It reduces the design cost by reusing chiplets. While black-boxing of the
slow design stages cuts down the design time, it raises significant security
concerns. We study the security implications of the emerging interposer-based
integration methodology. The black-boxed design stages deploy security measures
against hardware Trojans, reverse engineering, and intellectual property piracy
in traditional systems-on-chip (SoC) designs and hence are not suitable for
interposer-based integration. We propose using functionally diverse chiplets to
detect and thwart hardware Trojans and use the inherent logic redundancy to
shore up anti-piracy measures. Our proposals do not rely on access to the
black-box design stages. We evaluate the security, time and cost benefits of
our plan by implementing a MIPS processor, a DCT core, and an AES core using
various IPs from the Xilinx CORE GENERATOR IP catalog, on an interposer-based
Xilinx FPGA.
