  A key distinguishing feature of single flux quantum (SFQ) circuits is that
each logic gate is clocked. This feature forces the introduction of
path-balancing flip-flops to ensure proper synchronization of inputs at each
gate. This paper proposes a polynomial time complexity approximation algorithm
for clocking assignments that minimizes the insertion of path balancing buffers
for multi-threaded multi-phase clocking of SFQ circuits. Existing SFQ
multi-phase clocking solutions have been shown to effectively reduce the number
of required buffers inserted while maintaining high throughput, however, the
associated clock assignment algorithms have exponential complexity and can have
prohibitively long runtimes for large circuits, limiting the scalability of
this approach. Our proposed algorithm is based on a linear program (LP) that
leads to solutions that are experimentally on average within 5% of the optimum
and helps accelerate convergence towards the optimal integer linear program
(ILP) based solution. The improved LP and ILP runtimes permit multi-phase
clocking schemes to scale to larger SFQ circuits than previous state of the art
clocking assignment methods. We further extend the existing algorithm to
support fanout sharing of the added buffers, saving, on average, an additional
10% of the inserted DFFs. Compared to traditional full path balancing (FPB)
methods across 10 benchmarks, our enhanced LP saves 79.9%, 87.8%, and 91.2% of
the inserted buffers for 2, 3, and 4 clock phases respectively. Finally, we
extend this approach to the generation of circuits that completely mitigate
potential hold-time violations at the cost of either adding on average less
than 10% more buffers (for designs with 3 or more clock phases) or, more
generally, adding a clock phase and thereby reducing throughput.
