  In this contribution, it is proposes to limit the quantization search space
of a successive approximation analog-to-digital converter through an analytic
derivation of maximum possible sample-to-sample variation. The presented
example design of the proposed ADC is an 8-bit 1MS/s ADC with SAR logic
customized to incorporate this priori information while no modification has
been required to the analog circuitry. In comparison to conventional SAR
conversion, the proposed tracking approach yields significant reduction in
total power consumption in oversampling mode. The power savings are due to the
reduced number of SAR cycles, and voltage variation minimization across DAC
capacitors. The design is reconfigurable both to conventional SAR sampling and
the proposed tracking scheme. The approach is attractive for SAR ADCs embedded
in very low power micro-controllers.
