  We present a gigabit transceiver prototype Application Specific Integrated
Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout
upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four
upstream receiver channels, a downstream transmitter channel, and an
Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at
5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial
(Twinax) cables, equalize them, retime them with a recovered clock, and then
drive an optical transmitter. The downstream channel receives the data at 2.56
Gbps from an optical receiver and drives the cable as same as the upstream
channels. The jitter of the upstream channel output is measured to be 35 ps
(peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the
jitter of the downstream channel output after the cable is 138 ps (peak-peak).
The power consumption of each upstream channel is 72 mW when the CDR module is
turned on and the downstream channel consumes 27 mW. GBCR survives the total
ionizing dose of 200 kGy.
