  Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are
studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system.
SEU/SET affect the FE-I4B Global Registers as well as the settings for the
individual pixels, causing, among other things, occupancy losses, drops in the
low voltage currents, noisy pixels, and silent pixels. Quantitative data
analysis and simulations indicate that SET dominate over SEU on the load line
of the memory. Operational issues and mitigation techniques are presented.
