  Polynomial multiplication stands out as a highly demanding arithmetic process
in the development of post-quantum cryptosystems. The importance of
number-theoretic transform (NTT) extends beyond post-quantum cryptosystems,
proving valuable in enhancing existing security protocols such as digital
signature schemes and hash functions. Due to the potential for errors to
significantly disrupt the operation of secure, cryptographically-protected
systems, compromising data integrity, and safeguarding against side-channel
attacks initiated through faults it is essential to incorporate mitigating
error detection schemes. This paper introduces algorithm level fault detection
schemes in NTT multiplication, representing a significant enhancement compared
to previous research. We evaluate this through the simulation of a fault model,
ensuring that the conducted assessments accurately mirror the obtained results.
Consequently, we attain a notably comprehensive coverage of errors. Finally, we
assess the performance of our efficient error detection scheme on FPGAs to
showcase its implementation and resource requirements. Through implementation
of our error detection approach on Xilinx/AMD Zynq Ultrascale+ and Artix-7, we
achieve a comparable throughput with just a 9% increase in area and 13%
increase in latency compared to the original hardware implementations.
