  For neuromorphic engineering to emulate the human brain, improving memory
density with low power consumption is an indispensable but challenging goal. In
this regard, emerging RRAMs have attracted considerable interest for their
unique qualities like low power consumption, high integration potential,
durability, and CMOS compatibility. Using RRAMs to imitate the more analog
storage behavior of brain synapses is also a promising strategy for further
improving memory density and power efficiency. However, RRAM devices display
strong stochastic behavior, together with relaxation effects, making it more
challenging to precisely control their multi-level storage capability. To
address this, researchers have reported different multi-level programming
strategies, mostly involving the precise control of analog parameters like
compliance current during write operations and/or programming voltage
amplitudes. Here, we present a new fully digital relaxation-aware method for
tuning the conductance of analog RRAMs. The method is based on modulating
digital pulse widths during erase operations while keeping other parameters
fixed, and therefore requires no precise alterations to analog parameters like
compliance currents or programming voltage amplitudes. Experimental results,
with and without relaxation effect awareness, on a 64 RRAM 1T1R HfOx memory
array of cells, fabricated in 130nm CMOS technology, indicate that it is
possible to obtain 2-bit memory per cell multi-value storage at the array
level, verified 1000 seconds after programming.
