  Transistor aging phenomena manifest themselves as degradations in the main
electrical characteristics of transistors. Over time, they result in a
significant increase of cell propagation delay, leading to errors due to timing
violations, since the operating frequency becomes unsustainable as the circuit
ages. Conventional techniques employ timing guardbands to mitigate
aging-induced delay increase, which leads to considerable performance losses
from the beginning of the circuit's lifetime. Leveraging the inherent error
resilience of a vast number of application domains, approximate computing was
recently introduced as an aging mitigation mechanism. In this work, we present
the first automated framework for generating aging-aware approximate circuits.
Our framework, by applying directed gate-level netlist approximation, induces a
small functional error and recovers the delay degradation due to aging. As a
result, our optimized circuits eliminate aging-induced timing errors.
Experimental evaluation over a variety of arithmetic circuits and image
processing benchmarks demonstrates that for an average error of merely
$5\times10^{-3}$, our framework completely eliminates aging-induced timing
guardbands. Compared to the respective baseline circuits without timing
guardbands (i.e., iso-performance evaluation), the error of the circuits
generated by our framework is $1208$x smaller.
