  Fully Homomorphic Encryption (FHE) enables privacy-preserving computation and
has many applications. However, its practical implementation faces massive
computation and memory overheads. To address this bottleneck, several
Application-Specific Integrated Circuit (ASIC) FHE accelerators have been
proposed. All these prior works put every component needed for FHE onto one
chip (monolithic), hence offering high performance. However, they suffer from
practical problems associated with large-scale chip design, such as
inflexibility, low yield, and high manufacturing cost.
  In this paper, we present the first-of-its-kind multi-chiplet-based FHE
accelerator `REED' for overcoming the limitations of prior monolithic designs.
To utilize the advantages of multi-chiplet structures while matching the
performance of larger monolithic systems, we propose and implement several
novel strategies in the context of FHE. These include a scalable chiplet design
approach, an effective framework for workload distribution, a custom
inter-chiplet communication strategy, and advanced pipelined Number Theoretic
Transform and automorphism design to enhance performance.
  Experimental results demonstrate that REED 2.5D microprocessor consumes 96.7
mm$^2$ chip area, 49.4 W average power in 7nm technology. It could achieve a
remarkable speedup of up to 2,991x compared to a CPU (24-core 2xIntel X5690)
and offer 1.9x better performance, along with a 50% reduction in development
costs when compared to state-of-the-art ASIC FHE accelerators. Furthermore, our
work presents the first instance of benchmarking an encrypted deep neural
network (DNN) training. Overall, the REED architecture design offers a highly
effective solution for accelerating FHE, thereby significantly advancing the
practicality and deployability of FHE in real-world applications.
