  In this paper, we propose an architecture for FPGA emulation of mixed-signal
systems that achieves high accuracy at a high throughput. We represent the
analog output of a block as a superposition of step responses to changes in its
analog input, and the output is evaluated only when needed by the digital
subsystem. Our architecture is therefore intended for digitally-driven systems;
that is, those in which the inputs of analog dynamical blocks change only on
digital clock edges. We implemented a high-speed link transceiver design using
the proposed architecture on a Xilinx FPGA. This design demonstrates how our
approach breaks the link between simulation rate and time resolution that is
characteristic of prior approaches. The emulator is flexible, allowing for the
real-time adjustment of analog dynamics, clock jitter, and various design
parameters. We demonstrate that our architecture achieves 1% accuracy while
running 3 orders of magnitude faster than a comparable high-performance CPU
simulation.
