  Ternary logic system is the most promising and pursued alternate to the
prevailing binary logic systems due to the energy efficiency of circuits
following reduced circuit complexity and chip area. In this paper, we have
proposed a ternary 3-Transistor Dynamic Random-Access Memory (3T-DRAM) cell
using a single word-line for both read and write operation. For simulation of
the circuit, we have used Carbon-Nano-Tube Field Effect Transistor (CNTFET).
Here, we have analyzed the operation of the circuit considering different
process variations and showed the results for write delay, read sensing time,
and consumed current. Along with the basic DRAM design, we have proposed a
ternary sense circuitry for the proper read operation of the proposed DRAM. The
simulation and analysis are executed using the H-SPICE tool with Stanford
University CNTFET model.
