  Multichip systems with memory stacks and various processing chips are at the
heart of platform based designs such as servers and embedded systems. Full
utilization of the benefits of these integrated multichip systems need a
seamless, and scalable in-package interconnection framework. However,
state-of-the-art inter-chip communication requires long wireline channels which
increases energy consumption and latency while decreasing data bandwidth. Here,
we propose the design of an energy-efficient, seamless wireless interconnection
network for multichip systems. We demonstrate with cycle-accurate simulations
that such a design reduces the energy consumption and latency while increasing
the bandwidth in comparison to modern multichip integration systems.
