  The Fujitsu Digital Annealer (DA) is designed to solve fully connected
quadratic unconstrained binary optimization (QUBO) problems. It is implemented
on application-specific CMOS hardware and currently solves problems of up to
1024 variables. The DA's algorithm is currently based on simulated annealing;
however, it differs from it in its utilization of an efficient parallel-trial
scheme and a dynamic escape mechanism. In addition, the DA exploits the massive
parallelization that custom application-specific CMOS hardware allows. We
compare the performance of the DA to simulated annealing and parallel tempering
with isoenergetic cluster moves on two-dimensional and fully connected
spin-glass problems with bimodal and Gaussian couplings. These represent the
respective limits of sparse versus dense problems, as well as high-degeneracy
versus low-degeneracy problems. Our results show that the DA currently exhibits
a time-to-solution speedup of roughly two orders of magnitude for fully
connected spin-glass problems with bimodal or Gaussian couplings, over the
single-core implementations of simulated annealing and parallel tempering Monte
Carlo used in this study. The DA does not appear to exhibit a speedup for
sparse two-dimensional spin-glass problems, which we explain on theoretical
grounds. We also benchmarked an early implementation of the Parallel Tempering
DA. Our results suggest an improved scaling over the other algorithms for fully
connected problems of average difficulty with bimodal disorder. The next
generation of the DA is expected to be able to solve fully connected problems
up to 8192 variables in size. This would enable the study of fundamental
physics problems and industrial applications that were previously inaccessible
using standard computing hardware or special-purpose quantum annealing
machines.
