  This paper investigates an emerging cache side channel attack defense
approach involving the use of hardware performance counters (HPCs). These
counters monitor microarchitectural events and analyze statistical deviations
to differentiate between malicious and benign software. With numerous proposals
and promising reported results, we seek to investigate whether published
HPC-based detection methods are evaluated in a proper setting and under the
right assumptions, such that their quality can be ensured for real-word
deployment against cache side-channel attacks. To achieve this goal, this paper
presents a comprehensive evaluation and scrutiny of existing literature on the
subject matter in a form of a survey, accompanied by experimental evidences to
support our evaluation.
