  RISC-V processors encounter substantial challenges in deploying
multi-precision deep neural networks (DNNs) due to their restricted precision
support, constrained throughput, and suboptimal dataflow design. To tackle
these challenges, a scalable RISC-V vector (RVV) processor, namely SPEED, is
proposed to enable efficient multi-precision DNN inference by innovations from
customized instructions, hardware architecture, and dataflow mapping. Firstly,
dedicated customized RISC-V instructions are proposed based on RVV extensions,
providing SPEED with fine-grained control over processing precision ranging
from 4 to 16 bits. Secondly, a parameterized multi-precision systolic array
unit is incorporated within the scalable module to enhance parallel processing
capability and data reuse opportunities. Finally, a mixed multi-precision
dataflow strategy, compatible with different convolution kernels and data
precision, is proposed to effectively improve data utilization and
computational efficiency. We perform synthesis of SPEED in TSMC 28nm
technology. The experimental results demonstrate that SPEED achieves a peak
throughput of 287.41 GOPS and an energy efficiency of 1335.79 GOPS/W at 4-bit
precision condition, respectively. Moreover, when compared to the pioneer
open-source vector processor Ara, SPEED provides an area efficiency improvement
of 2.04$\times$ and 1.63$\times$ under 16-bit and 8-bit precision conditions,
respectively, which shows SPEED's significant potential for efficient
multi-precision DNN inference.
