  Inspired by the connectivity mechanisms in the brain, neuromorphic computing
architectures model Spiking Neural Networks (SNNs) in silicon. As such,
neuromorphic architectures are designed and developed with the goal of having
small, low power chips that can perform control and machine learning tasks.
However, the power consumption of the developed hardware can greatly depend on
the size of the network that is being evaluated on the chip. Furthermore, the
accuracy of a trained SNN that is evaluated on chip can change due to voltage
and current variations in the hardware that perturb the learned weights of the
network. While efforts are made on the hardware side to minimize those
perturbations, a software based strategy to make the deployed networks more
resilient can help further alleviate that issue. In this work, we study Spiking
Neural Networks in two neuromorphic architecture implementations with the goal
of decreasing their size, while at the same time increasing their resiliency to
hardware faults. We leverage an evolutionary algorithm to train the SNNs and
propose a multiobjective fitness function to optimize the size and resiliency
of the SNN. We demonstrate that this strategy leads to well-performing,
small-sized networks that are more resilient to hardware faults.
