  As conventional memory technologies are challenged by their technological
physical limits, emerging technologies driven by novel materials are becoming
an attractive option for future memory architectures. Among these technologies,
Resistive Memories (ReRAM) created new possibilities because of their
nano-features and unique $I$-$V$ characteristics. One particular problem that
limits the maximum array size is interference from neighboring cells due to
sneak-path currents. A possible device level solution to address this issue is
to implement a memory array using complementary resistive switches (CRS).
Although the storage mechanism for a CRS is fundamentally different from what
has been reported for memristors (low and high resistances), a CRS is simply
formed by two series bipolar memristors with opposing polarities. In this paper
our intention is to introduce modeling principles that have been previously
verified through measurements and extend the simulation principles based on
memristors to CRS devices and hence provide an analytical approach to the
design of a CRS array. The presented approach creates the necessary design
methodology platform that will assist designers in implementation of CRS
devices in future systems.
