  Spin Transfer Torque MRAMs are attractive due to their non-volatility, high
density and zero leakage. However, STT-MRAMs suffer from poor reliability due
to shared read and write paths. Additionally, conflicting requirements for data
retention and write-ability (both related to the energy barrier height of the
magnet) makes design more challenging. Furthermore, the energy barrier height
depends on the physical dimensions of the free layer. Any variations in the
dimensions of the free layer lead to variations in the energy barrier height.
In order to address poor reliability of STT-MRAMs, usage of Error Correcting
Codes (ECC) have been proposed. Unlike traditional CMOS memory technologies,
ECC is expected to correct both soft and hard errors in STT_MRAMs. To achieve
acceptable yield with low write power, stronger ECC is required, resulting in
increased number of encoded bits and degraded memory efficiency. In this paper,
we propose Failure aware ECC (FaECC), which masks permanent faults while
maintaining the same correction capability for soft errors without increased
encoded bits. Furthermore, we investigate the impact of process variations on
run-time reliability of STT-MRAMs. We provide an analysis on the impact of
process variations on the life-time of the free layer and retention failures.
In order to analyze the effectiveness of our methodology, we developed a
cross-layer simulation framework that consists of device, circuit and array
level analysis of STT-MRAM memory arrays. Our results show that using FaECC
relaxes the requirements on the energy barrier height, which reduces the write
energy and results in smaller access transistor size and memory array area.
Keywords: STT-MRAM, reliability, Error Correcting Codes, ECC, magnetic memory
