  With the sensor scaling of next-generation Brain-Machine Interface (BMI)
systems, the massive A/D conversion and analog multiplexing at the neural
frontend poses a challenge in terms of power and data rates for wireless and
implantable BMIs. While previous works have reported the neuromorphic
compression of neural signal, further compression requires integration of spike
detectors on chip. In this work, we propose an efficient HRAM-based spike
detector using In-memory computing for compressive event-based neural frontend.
Our proposed method involves detecting spikes from event pulses without
reconstructing the signal and uses a 10T hybrid in-memory computing bitcell for
the accumulation and thresholding operations. We show that our method ensures a
spike detection accuracy of 92-99% for neural signal inputs while consuming
only 13.8 nW per channel in 65 nm CMOS.
