  With the continuously increasing integration level, manycore processor
systems are likely to be the coming system structure not only in HPC but also
for desktop or mobile systems. Nowadays manycore processors like Tilera TILE,
KALRAY MPPA or Intel SCC combine a rising number of cores in a tiled
architecture and are mainly designed for high performance applications with
focus on direct inter-core communication. The current architectures have
limitations by central or sparse components like memory controllers, memory I/O
or inflexible memory management.
  In the future highly dynamic workloads with multiple concurrently running
applications, changing I/O characteristics and a not predictable memory usage
have to be utilized on these manycore systems. Consequently the memory
management has to become more flexible and distributed in nature and adaptive
mechanisms and system structures are needed. With Self-aware Memory (SaM), a
decentralized, scalable and autonomous self-optimizing memory architecture is
developed. This adaptive memory management can achieve higher flexibility and
an easy usage of memory.
  In this paper the concept of an ongoing decentralized self-optimization is
introduced and the evaluation of its various parameters is presented. The
results show that the overhead of the decentralized optimization process is
amortized by the optimized runtime using the appropriate parameter settings.
