  This work presents a new silicon vertical JFET (V-JFET) device, based on the
trenched 3D-detector technology developed at IMB-CNM, to be used as switches
for the High-Voltage powering scheme of the ATLAS upgrade Inner Tracker. The
optimization of the device characteristics is performed by 2D and 3D TCAD
simulations. Special attention has been paid to the on-resistance and the
switch-off and breakdown voltages to meet the specific requirements of the
system. In addition, a set of parameter values has been extracted from the
simulated curves to implement a SPICE model of the proposed V-JFET transistor.
As these devices are expected to operate under very high radiation conditions
during the whole experiment life-time, a study of the radiation damage effects
and the expected degradation on the device performance is also presented at the
end of the paper.
