  The massive amounts of data generated by camera sensors motivate data
processing inside pixel arrays, i.e., at the extreme-edge. Several critical
developments have fueled recent interest in the processing-in-pixel-in-memory
paradigm for a wide range of visual machine intelligence tasks, including (1)
advances in 3D integration technology to enable complex processing inside each
pixel in a 3D integrated manner while maintaining pixel density, (2) analog
processing circuit techniques for massively parallel low-energy in-pixel
computations, and (3) algorithmic techniques to mitigate non-idealities
associated with analog processing through hardware-aware training schemes. This
article presents a comprehensive technology-circuit-algorithm landscape that
connects technology capabilities, circuit design strategies, and algorithmic
optimizations to power, performance, area, bandwidth reduction, and
application-level accuracy metrics. We present our results using a
comprehensive co-design framework incorporating hardware and algorithmic
optimizations for various complex real-life visual intelligence tasks mapped
onto our P2M paradigm.
