  We describe a programming abstraction for heterogeneous parallel hardware,
designed to capture a wide range of popular parallel hardware, including GPUs,
vector instruction sets and multicore CPUs. Our abstraction, which we call
HPVM, is a hierarchical dataflow graph with shared memory and vector
instructions. We use HPVM to define both a virtual instruction set (ISA) and
also a compiler intermediate representation (IR). The virtual ISA aims to
achieve both functional portability and performance portability across
heterogeneous systems, while the compiler IR aims to enable effective code
generation and optimization for such systems.
  HPVM effectively supports all forms of parallelism used to achieve
computational speedups (as opposed to concurrency), including task parallelism,
coarse-grain data parallelism, fine-grain data parallelism, and pipelined
parallelism. HPVM also enables flexible scheduling and tiling: different nodes
in the dataflow graph can be mapped flexibly to different combinations of
compute units, and the graph hierarchy expresses memory tiling, essential for
achieving high performance on GPU and CPU targets.
