  High-Level Synthesis allows hardware designers to create complex RTL designs
using C/C++. The traditional HLS workflow involves iterations of C/C++
simulation for partial functional verification and HLS synthesis for coarse
timing estimates. However, neither C/C++ simulation nor HLS synthesis estimates
can account for complex behaviors like FIFO interactions and pipeline stalls,
thereby obscuring problems like deadlocks and latency overheads. Such problems
are revealed only through C/RTL co-simulation, which is typically orders of
magnitude slower than either C/C++ simulation or HLS synthesis, far too slow to
integrate into the edit-run development cycle. Addressing this, we propose
LightningSim, a fast simulation tool for HLS that combines the speed of native
C/C++ with the accuracy of C/RTL co-simulation. LightningSim directly operates
on the LLVM intermediate representation (IR) code and accurately simulates a
hardware design's dynamic behavior. First, it traces LLVM IR execution to
capture the run-time information; second, it maps the static HLS scheduling
information to the trace to simulate the dynamic behavior; third, it calculates
stalls and deadlocks from inter-function interactions to get precise cycle
counts. Evaluated on 33 benchmarks, LightningSim produces 99.9%-accurate timing
estimates up to 95x faster than RTL simulation. Our code is publicly available
on GitHub.
