  The design of asynchronous circuits typically requires a judicious definition
of signals and modules, combined with a proper specification of their timing
constraints, which can be a complex and error-prone process, using standard
Hardware Description Languages (HDLs). In this paper we introduce Yak, a new
dataflow description language for asynchronous bundled data circuits. Yak
allows designers to generate Verilog and timing constraints automatically, from
a textual description of bundled data control flow structures and combinational
logic blocks. The timing constraints are generated using the Local Clock Set
methodology and can be consumed by standard industry tools. Yak includes
ergonomic language features such as structured bindings of channels undergoing
fork and join operations, named value scope propagation along channels, and
channel typing. Here we present Yak's language front-end and compare the
automated synthesis and layout results of an example circuit with a manual
constraint specification approach.
