  The computational efficiency of the human brain is believed to stem from the
parallel information processing capability of neurons with integrated storage
in synaptic interconnections programmed by local spike triggered learning rules
such as spike timing dependent plasticity (STDP). The extremely low operating
voltages (approximately $100\,$mV) used to trigger neuronal signaling and
synaptic adaptation is believed to be a critical reason for the brain's power
efficiency. We demonstrate the feasibility of spike triggered STDP behavior in
a two-terminal Cu/SiO$_2$/W memristive device capable of operating below
$500\,$mV. We analyze the state-dependent nature of conductance updates in the
device to develop a phenomenological model. Using the model, we evaluate the
potential of such devices to generate precise spike times under supervised
learning conditions and classify handwritten digits from the MNIST dataset in
an unsupervised learning setting. The results form a promising step towards
creating a low power synaptic device capable of on-chip learning.
