  In the upgrade of ATLAS experiment, the front-end electronics components are
subjected to a large radiation background. Meanwhile high speed optical links
are required for the data transmission between the on-detector and off-detector
electronics. The GBT architecture and the Versatile Link (VL) project are
designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed
data transmission which is called GBT link. In the ATLAS upgrade, besides the
link with on-detector, the GBT link is also used between different off-detector
systems. The GBTX ASIC is designed for the on-detector front-end,
correspondingly for the off-detector electronics, the GBT architecture is
implemented in Field Programmable Gate Arrays (FPGA). CERN launches the
GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS
upgrade framework, the Front-End LInk eXchange (FELIX) system is used to
interface the front-end electronics of several ATLAS subsystems. The GBT link
is used between them, to transfer the detector data and the timing, trigger,
control and monitoring information. The trigger signal distributed in the
down-link from FELIX to the front-end requires a fixed and low latency. In this
paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve
a lower fixed latency. For FELIX, a common firmware will be used to interface
different front-ends with support of both GBT modes: the forward error
correction mode and the wide mode. The modified GBT-FPGA core has the ability
to switch between the GBT modes without FPGA reprogramming. The system clock
distribution of the multi-channel FELIX firmware is also discussed in this
paper.
