  We present a power efficient clock-less fully asynchronous bit-serial Low
Voltage Differential Signaling (LVDS) link with event-driven instant wake-up
and self-sleep features, optimized for high speed inter-chip communication of
asynchronous address-events between neuromorphic chips. The proposed LVDS link
makes use of the Level-Encoded Dual-Rail (LEDR) representation and a token-ring
architecture to encode and transmit data, avoiding the use of conventional
large ClockData Recovery (CDR) modules with power-hungry DLL or PLL circuits.
We implemented the LVDS circuits in a device fabricated with a standard 0.18 um
CMOS process. The total silicon area used for such block is of 0.14 mm^2. We
present experimental measurement results to demonstrate that, with a bit rate
of 1.5 Gbps and an event width of 32-bit, the proposed LVDS link can achieve
transmission event rates of 35.7 M Events/second with current consumption of
19.3 mA and 3.57 mA for receiver and transmitter blocks, respectively. Given
the clock-less and instant on/off design choices made, the power consumption of
the whole link depends linearly on the data transmission rate. We show that the
current consumption can go down to sub-uA for low event rates (e.g., <1k
Events/second), with a floor of 80 nA for transmitter and 42 nA for receiver,
determined mainly by static off-leakage currents.
