  Metal inter-layer via (MIV) in Monolithic three-dimensional integrated
circuits (M3D-IC) is used to connect inter-layer devices and provide power and
clock signals across multiple layers. The size of MIV is comparable to logic
gates because of the significant reduction in substrate layers due to
sequential integration. Despite MIV's small size, the impact of MIV on the
performance of adjacent devices should be considered to implement IC designs in
M3D-IC technology. In this work, we systematically study the changes in
performance of transistors when they are placed near MIV to understand the
effect of MIV on adjacent devices when MIV passes through the substrate.
Simulation results suggest that the keep-out-zone (KOZ) for MIV should be
considered to ensure the reliability of M3D-IC technology and this KOZ is
highly dependent on the M3D-IC process. In this paper, we show that the
transistor placed near MIV considering the M1 metal pitch as the separation
will have up to $68,668\times$ increase in leakage current, when the channel
doping is $10^{15} cm^{-3}$, source/drain doping of $10^{18}cm^{-3}$ and
substrate layer height of $100\ nm$. We also show that, this increase in
leakage current can also be reduced significantly by having KOZ around MIV,
which is dependent on the process.
