  Power consumption has emerged as a primary design constraint for integrated
circuits (ICs). In the Nano meter technology regime, leakage power has become a
major component of total power. Full adder is the basic functional unit of an
ALU. The power consumption of a processor is lowered by lowering the power
consumption of an ALU, and the power consumption of an ALU can be lowered by
lowering the power consumption of Full adder. So the full adder designs with
low power characteristics are becoming more popular these days. This proposed
work illustrates the design of the low-power less transistor full adder designs
using cadence tool and virtuoso platform, the entire simulations have been done
on 180nm single n-well CMOS bulk technology, in virtuoso platform of cadence
tool with the supply voltage 1.8V and frequency of 100MHz. These circuits
consume less power with maximum (6T design)of 93.1% power saving compare to
conventional 28T design and 80.2% power saving compare to SERF design without
much delay degradation. The proposed circuit exploits the advantage of GDI
technique and pass transistor logic
