  Compute eXpress Link (CXL) is emerging as a promising memory interface
technology. Because of the common unavailiability of CXL devices, the
performance of the CXL memory is largely unknown. What are the use cases for
the CXL memory? What are the impacts of the CXL memory on application
performance? How to use the CXL memory in combination with existing memory
components? In this work, we study the performance of three genuine CXL
memory-expansion cards from different vendors. We characterize the basic
performance of the CXL memory, study how HPC applications and large language
models can benefit from the CXL memory, and study the interplay between memory
tiering and page interleaving. We also propose a novel data object-level
interleaving policy to match the interleaving policy with memory access
patterns. We reveal the challenges and opportunities of using the CXL memory.
