  High luminosity conditions at the LHC pose many unique challenges for
potential silicon based track trigger systems. One of the major challenges is
data formatting, where hits from thousands of silicon modules must first be
shared and organized into overlapping eta-phi trigger towers. Communication
between nodes requires high bandwidth, low latency, and flexible real time data
sharing, for which a full mesh backplane is a natural solution. A custom
Advanced Telecommunications Computing Architecture data processing board is
designed with the goal of creating a scalable architecture abundant in
flexible, non-blocking, high bandwidth board to board communication channels
while keeping the design as simple as possible. We have performed the first
prototype board testing and our first attempt at designing the prototype system
has proven to be successful. Leveraging the experience we gained through
designing, building and testing the prototype board system we are in the final
stages of laying out the next generation board, which will be used in the ATLAS
Level-2 Fast TracKer as Data Formatter, as well as in the CMS Level-1 tracking
trigger R&D for early technical demonstrations.
