  Continuous technology scaling and the introduction of advanced technology
nodes in Integrated Circuit (IC) fabrication is constantly exposing new
manufacturability issues. One such issue, stemming from complex interaction
between design and process, is the problem of design hotspots. Such hotspots
are known to vary from design to design and, ideally, should be predicted early
and corrected in the design stage itself, as opposed to relying on the foundry
to develop process fixes for every hotspot, which would be intractable. In the
past, various efforts have been made to address this issue by using a known
database of hotspots as the source of information. The majority of these
efforts use either Machine Learning (ML) or Pattern Matching (PM) techniques to
identify and predict hotspots in new incoming designs. However, almost all of
them suffer from high false-alarm rates, mainly because they are oblivious to
the root causes of hotspots. In this work, we seek to address this limitation
by using a novel database enhancement approach through synthetic pattern
generation based on carefully crafted Design of Experiments (DOEs).
Effectiveness of the proposed method against the state-of-the-art is evaluated
on a 45nm process using industry-standard tools and designs.
