  Error correcting codes use multi-qubit measurements to realize fault-tolerant
quantum logic steps. In fact, the resources needed to scale-up fault-tolerant
quantum computing hardware are largely set by this task. Tailoring
next-generation processors for joint measurements, therefore, could result in
improvements to speed, accuracy, or cost -- accelerating the development
large-scale quantum computers. Here, we motivate such explorations by analyzing
an unconventional surface code based on multi-body interactions between
superconducting transmon qubits. Our central consideration, Hardware Optimized
Parity (HOP) gates, achieves stabilizer-type measurements through simultaneous
multi-qubit conditional phase accumulation. Despite the multi-body effects that
underpin this approach, our estimates of logical faults suggest that this
design can be at least as robust to realistic noise as conventional designs. We
show a higher threshold of $1.25 \times 10^{-3}$ compared to the standard
code's $0.79 \times 10^{-3}$. However, in the HOP code the logical error rate
decreases more slowly with decreasing physical error rate. Our results point to
a fruitful path forward towards extending gate-model platforms for error
correction at the dawn of its empirical development.
