  A time-domain analog-weighted-sum calculation model based on a pulse-width
modulation (PWM) approach is proposed. The proposed calculation model can be
applied to any types of network structure including multi-layer feedforward
networks. We also propose very large-scale integrated (VLSI) circuits to
implement the proposed model. Unlike the conventional analog voltage or current
mode circuits used in computing-in-memory circuits, our time-domain analog
circuits use transient operation in charging/discharging processes to
capacitors. Since the circuits can be designed without operational amplifiers,
they can be operated with extremely low power consumption. However, they have
to use very high-resistance devices, on the order of giga-ohms. We designed a
CMOS VLSI chip to verify weighted-sum operation based on the proposed model
with binary weights, which realizes the BinaryConnect model. In the chip,
memory cells of static-random-access memory (SRAM) are used for synaptic
connection weights. High-resistance operation was realized by using the
subthreshold operation region of MOS transistors unlike the ordinary
computing-in-memory circuits. The chip was designed and fabricated using a
250-nm fabrication technology. Measurement results showed that energy
efficiency for the weighted-sum calculation was 300~TOPS/W (Tera-Operations Per
Second per Watt), which is more than one order of magnitude higher than that in
state-of-the-art digital AI processors, even though the minimum width of
interconnection used in this chip was several times larger than that in such
digital processors. If state-of-the-art VLSI technology is used to implement
the proposed model, an energy efficiency of more than 1,000~TOPS/W will be
possible. For practical applications, development of emerging analog memory
devices such as ferroelectric-gate field effect transistors (FeFETs) is
necessary.
