  Power consumption has become the major concern in neural network accelerators
for edge devices. The novel non-volatile-memory (NVM) based computing-in-memory
(CIM) architecture has shown great potential for better energy efficiency.
However, most of the recent NVM-CIM solutions mainly focus on fixed-point
calculation and are not applicable to floating-point (FP) processing. In this
paper, we propose an analog-domain floating-point CIM architecture (AFPR-CIM)
based on resistive random-access memory (RRAM). A novel adaptive dynamic-range
FP-ADC is designed to convert the analog computation results into FP codes.
Output current with high dynamic range is converted to a normalized voltage
range for readout, to prevent precision loss at low power consumption.
Moreover, a novel FP-DAC is also implemented which reconstructs FP digital
codes into analog values to perform analog computation. The proposed AFPR-CIM
architecture enables neural network acceleration with FP8 (E2M5) activation for
better accuracy and energy efficiency. Evaluation results show that AFPR-CIM
can achieve 19.89 TFLOPS/W energy efficiency and 1474.56 GOPS throughput.
Compared to traditional FP8 accelerator, digital FP-CIM, and analog INT8-CIM,
this work achieves 4.135x, 5.376x, and 2.841x energy efficiency enhancement,
respectively.
