  This paper presents an extensive characterization of the low-frequency noise
(LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm
bulk-CMOS transistors. The noise is measured over a wide range of bias
conditions and geometries to generate a comprehensive overview of LFN in this
technology. While the RT results are in-line with the literature and the
foundry models, the cryogenic behavior diverges in many aspects. These
deviations include changes with respect to RT in magnitude and bias dependence
that are conditional on transistor type and geometry, and even an additional
systematic Lorentzian feature that is common among individual devices.
Furthermore, we find the scaling of the average LFN with the area and its
variability to be similar between RT and 4.2 K, with the cryogenic scaling
reported systematically for the first time. The findings suggest that, as no
consistent decrease of LFN at lower temperatures is observed while the white
noise is reduced, the impact of LFN for precision analog design at cryogenic
temperatures gains a more predominant role.
