  Reversible computing has attracted the attention of researchers due to its
low power consumption and less heat dissipation compared to conventional
computing. A number of reversible gates have been proposed by different
researchers and various combinational circuits based on reversible gates have
been developed. However the realization of sequential circuit in reversible
logic is still at premature stage. Sequential circuits were not available
because of feedback was not allowed in reversible circuit. However allowing
feedback in space (not in time), some sequential reversible gates and circuits
have been reported in the literature. In this dissertation, we have addressed
the problem from two sides. One side is to propose a low cost reversible gate
suitable for sequential building block i.e. T flip-flop and hence designing low
cost synchronous and asynchronous counters. Another side is to generate the
circuit from its behavioral description described in FSM form. Our propose
designs of reversible counters are significantly better in optimization
parameters such as gate counts, garbage outputs and constant inputs available
in literature. We have also proposed a procedure for obtaining reversible
circuit from behavioral description through FSM. A very few attempts have been
reported in the literature for the conversion FSM to reversible FSM.Because of
non-availability of generated sequential reversible circuit in literature, our
results cannot be compared with any other circuits. We expect that the
sequential reversible circuits will help in debugging the reversible circuits,
handling the ambiguous state of an FSM and generating the original input in
reverse direction by reversing the original output.
