  Using Error Detection Code (EDC) and Error Correction Code (ECC) is a
noteworthy way to increase cache memories robustness against soft errors. EDC
enables detecting errors in cache memory while ECC is used to correct erroneous
cache blocks. ECCs are often costly as they impose considerable area and energy
overhead on cache memory. Reducing this overhead has been the subject of many
studies. In particular, a previous study has suggested mapping ECC to the main
memory at the expense of high cache traffic and energy. A major source of this
excessive traffic and energy is the high frequency of cache writes. In this
work, we show that a significant portion of cache writes are silent, i.e., they
write the same data already existing. We build on this observation and
introduce Traffic-aware ECC (or simply TCC). TCC detects silent writes by an
efficient mechanism. Once such writes are detected updating their ECC is
avoided effectively reducing L2 cache traffic and access frequency. Using our
solution, we reduce L2 cache access frequency by 8% while maintaining
performance. We reduce L2 cache dynamic and overall cache energy by up to 32%
and 8%, respectively. Furthermore, TCC reduces L2 cache miss rate by 3%.
