  This paper presents the design and characterisation of a front-end prototype
ASIC for the ATLAS High Granularity Timing Detector, which is planned for the
High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of
a 5$\times$5-pad matrix and contains the analog part of the single-channel
readout (preamplifier, discriminator, two TDCs and SRAM). Two preamplifier
architectures (transimpedance and voltage) were implemented and tested. The
ASIC was characterised both alone and as a module when connected to a
5$\times$5-pad array of LGAD sensors. In calibration measurements, the ASIC
operating alone was found to satisfy the technical requirements for the
project, with similar performances for both preamplifier types. In particular,
the jitter was found to be 15$\pm$1~ps (35$\pm$1~ps) for an injected charge of
10~fC (4~fC). A degradation in performance was observed when the ASIC was
connected to the LGAD array. This is attributed to digital couplings at the
entrance of the preamplifiers. When the ASIC is connected to the LGAD array,
the lowest detectable charge increased from 1.5~fC to 3.4~fC. As a consequence,
the jitter increased for an injected charge of 4~fC. Despite this increase,
ALTIROC1 still satisfies the maximum jitter specification (below 65~ps) for the
HGTD project. This coupling issue also affects the time over threshold
measurements and the time-walk correction can only be performed with
transimpedance preamplifiers. Beam test measurements with a pion beam at CERN
were also undertaken to evaluate the performance of the module. The best time
resolution obtained using only ALTIROC TDC data was 46.3$\pm$0.7~ps for a
restricted time of arrival range where the coupling issue is minimized. The
residual time-walk contribution is equal to 23~ps and is the dominant
electronic noise contribution to the time resolution at 15~fC.
