  Process induced efficiency variation is a major concern for all thin film
solar cells, including the emerging perovskite based solar cells. In this
manuscript, we address the effect of pinholes or process induced surface
coverage aspects on the efficiency of such solar cells through detailed
numerical simulations. Interestingly, we find the pinhole size distribution
affects the short circuit current and open circuit voltage in contrasting
manners. Specifically, while the Jsc is heavily dependent on the pinhole size
distribution, surprisingly, the Voc seems to be only nominally affected by it.
Further, our simulations also indicate that, with appropriate interface
engineering, it is indeed possible to design a nanostructured device with
efficiencies comparable to that of ideal planar structures. Additionally, we
propose a simple technique based on terminal IV characteristics to estimate the
surface coverage in perovskite solar cells.
