  Carbon nanotube field-effect transistors (CNFET) emerge as a promising
alternative to CMOS transistors for the much higher speed and energy
efficiency, which makes the technology particularly suitable for building the
energy-hungry last level cache (LLC). However, the process variations (PVs) in
CNFET caused by the imperfect fabrication lead to large timing variation and
the worst-case timing dramatically limits the LLC operation speed.
Particularly, we observe that the CNFET-based cache latency distribution is
closely related to the LLC layouts. For the two typical LLC layouts that have
the CNT growth direction aligned to the cache way direction and cache set
direction respectively, we proposed variation-aware set aligned (VASA) cache
and variation-aware way aligned (VAWA) cache in combination with corresponding
cache optimizations such as data shuffling and page mapping to enable
low-latency cache for frequently used data. According to our experiments, the
optimized LLC reduces the average access latency by 32% and 45% compared to the
baseline designs on the two different CNFET layouts respectively while it
improves the overall performance by 6\% and 9\% and reduces the energy
consumption by 4% and 8% respectively. In addition, with both the architecture
induced latency variation and PV incurred latency variation considered in a
unified model, we extended the VAWA and VASA cache design for the CNFET-based
NUCA and the proposed NUCA achieves both significant performance improvement
and energy saving compared to the straightforward variation-aware NUCA.
