  This paper presents a small-area monolithic pixel detector ASIC designed in
130 nm SiGe BiCMOS technology for the upgrade of the pre-shower detector of the
FASER experiment at CERN. The purpose of this prototype is to study the
integration of fast front-end electronics inside the sensitive area of the
pixels and to identify the configuration that could satisfy at best the
specifications of the experiment. Self-induced noise, instabilities and
cross-talk were minimised to cope with the several challenges associated to the
integration of pre-amplifiers and discriminators inside the pixels. The
methodology used in the characterisation and the design choices will also be
described. Two of the variants studied here will be implemented in the
pre-production ASIC of the FASER experiment pre-shower for further tests.
