  Strong-ARM Dynamic Latch Comparators are widely used in high-speed
analog-to-digital converters (ADCs), sense amplifiers in memory, RFID
applications, and data receivers. This paper presents different methods to
improve the performance of Strong-Arm latch-based comparators. The comparator's
significant features such as power dissipation, propagation delay, offset
voltage, clock feedthrough, area, and kickback noises are discussed and
compared with state-of-the-art candidate topologies. Simulation results show
that the new comparator topologies of Strong-ARM Dynamic Latch proposed by
these authors gave the best results. The proposed designs are tested. The
simulations are carried out using UMC 180nm double metal, double poly standard
CMOS process technology, for a 100 MHz clock, at 1.8V supply-rail on the
Cadence Virtuoso EDA platform.
