  In this paper, we propose a high-performance RISC-V soft processor with an
efficient fetch unit supporting the compressed instructions targeting on FPGA.
The compressed instruction extension in RISC-V can reduce the program size by
about 25%. But it needs a complicated logic for the instruction fetch unit and
has a significant impact on performance. We propose an instruction fetch unit
that supports the compressed instructions while exhibiting high performance.
Furthermore, we propose a RISC-V soft processor using this unit. We implement
this proposed processor in Verilog HDL and verify the behavior using Verilog
simulation and an actual Xilinx Atrix-7 FPGA board. We compare the results of
some benchmarks and the amount of hardware with related works. DMIPS, CoreMark
value, and Embench value of the proposed processor achieved 42.5%, 41.1% and
21.3% higher performance than the related work, respectively.
