  One of the most challenging obstacles to realizing exascale computing is
minimizing the energy consumption of L2 cache, main memory, and interconnects
to that memory. For promising cryogenic computing schemes utilizing Josephson
junction superconducting logic, this obstacle is exacerbated by the cryogenic
system requirements that expose the technology's lack of high-density,
high-speed and power-efficient memory. Here we demonstrate an array of
cryogenic memory cells consisting of a non-volatile three-terminal magnetic
tunnel junction element driven by the spin Hall effect, combined with a
superconducting heater-cryotron bit-select element. The write energy of these
memory elements is roughly 8 pJ with a bit-select element, designed to achieve
a minimum overhead power consumption of about 30%. Individual magnetic memory
cells measured at 4 K show reliable switching with write error rates below
$10^{-6}$, and a 4x4 array can be fully addressed with bit select error rates
of $10^{-6}$. This demonstration is a first step towards a full cryogenic
memory architecture targeting energy and performance specifications appropriate
for applications in superconducting high performance and quantum computing
control systems, which require significant memory resources operating at 4 K.
