  Quantum computing promises an effective way to solve targeted problems that
are classically intractable. Among them, quantum computers built with
superconducting qubits are considered one of the most advanced technologies,
but they suffer from short coherence times. This can get exaggerated when they
are controlled directly by general-purpose host machines, which leads to the
loss of quantum information. To mitigate this, we need quantum control
processors (QCPs) positioned between quantum processing units and host machines
to reduce latencies. However, existing QCPs are built on top of designs with no
or inefficient scalability, requiring a large number of instructions when
scaling to more qubits. In addition, interactions between current QCPs and host
machines require frequent data transmissions and offline computations to obtain
final results, which limits the performance of quantum computers.
  In this paper, we propose a QCP called HiSEP-Q featuring a novel quantum
instruction set architecture (QISA) and its microarchitecture implementation.
For efficient control, we utilize mixed-type addressing modes and mixed-length
instructions in HiSEP-Q, which provides an efficient way to concurrently
address more than 100 qubits. Further, for efficient read-out and analysis, we
develop a novel onboard accumulation and sorting unit, which eliminates the
data transmission of raw data between the QCPs and host machines and enables
real-time result processing. Compared to the state-of-the-art, our proposed
QISA achieves at least 62% and 28% improvements in encoding efficiency with
real and synthetic quantum circuits, respectively. We also validate the
microarchitecture on a field-programmable gate array, which exhibits low power
and resource consumption. Both hardware and ISA evaluations demonstrate that
HiSEP-Q features high scalability and efficiency toward the number of
controlled qubits.
