  Since the 1960's when Gordon Moore proposed that the transistor density in
our electronic devices should double every two years while the cost is halved,
the semiconductor industry has taken this statement to heart. Over the last few
decades, no other industry has seen growth even comparably close to that
experienced by the semiconductors industry. This has all been made possible by
the unbroken string of ingenious breakthroughs by brilliant minds that have
been working tirelessly to shrink down transistors. The latest of which is the
use of high-k dielectrics and a return to metal gates combined with
3D-transistor architectures. This has been the enabling technology for the
transition from the 90 nm node to the 45 nm node, allowing us to shrink our
transistors further without losing additional gate control. The fundamental
reason for using a high-k gate dielectric compared to SiO2 is that shrinking
our gate oxide further, which is already at a few angstroms, is no longer a
feasible option to gain additional gate control. High-k dielectric overcome
this by exploiting the fundamental physics of capacitors and the materials
science of dielectrics to provide a viable option to increase gate control
without the need for successively thinner gate oxides. Hafnium Oxide is the
most studied and popular of such materials. Its high dielectric constant ~16-25
and interface stability with silicon at operating temperatures make it an ideal
candidate for use in current CMOS technology. Despite its deceivingly simple
appearance, the processes involved in the fabrication of such high-k HfO2/Si
interfaces are full of process subtleties and nuances. In this term paper we
hope to explore the physics and materials science of these high-k HfO2/Si
interfaces, discussing the challenges and ways to overcome them when it comes
to its actual fabrication, and how this ultimately affects our device
performance.
