  Networks-on-Chip (NoCs) used in commercial many-core processors typically
incorporate priority arbitration. Moreover, they experience bursty traffic due
to application workloads. However, most state-of-the-art NoC analytical
performance analysis techniques assume fair arbitration and simple traffic
models. To address these limitations, we propose an analytical modeling
technique for priority-aware NoCs under bursty traffic. Experimental
evaluations with synthetic and bursty traffic show that the proposed approach
has less than 10% modeling error with respect to cycle-accurate NoC simulator.
