  A new asynchronous early output section-carry based carry lookahead adder
(SCBCLA) with alias carry output logic is presented in this paper. To evaluate
the proposed SCBCLA with alias carry logic and to make a comparison with other
CLAs, a 32-bit addition operation is considered. Compared to the
weak-indication SCBCLA with alias logic, the proposed early output SCBCLA with
alias logic reports a 13% reduction in area without any increases in latency
and power dissipation. On the other hand, in comparison with the early output
recursive CLA (RCLA), the proposed early output SCBCLA with alias logic reports
a 16% reduction in latency while occupying almost the same area and dissipating
almost the same average power. All the asynchronous CLAs are
quasi-delay-insensitive designs which incorporate the delay-insensitive
dual-rail data encoding and adhere to the 4-phase return-to-zero handshaking.
The adders were realized and the simulations were performed based on a 32/28nm
CMOS process.
