  Application Specific Instruction-set Processor (ASIP) is one of the popular
processor design techniques for embedded systems which allows customizability
in processor design without overly hindering design flexibility. Multi-pipeline
ASIPs were proposed to improve the performance of such systems by compromising
between speed and processor area. One of the problems in the multi-pipeline
design is the limited inherent instruction level parallelism (ILP) available in
applications. The ILP of application programs can be improved via a compiler
optimization technique known as loop unrolling. In this paper, we present how
loop unrolling effects the performance of multi-pipeline ASIPs. The
improvements in performance average around 15% for a number of benchmark
applications with the maximum improvement of around 30%. In addition, we
analyzed the variable of performance against loop unrolling factor, which is
the amount of unrolling we perform.
