  This paper presents the design and simulation results of a gigabit
transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the
ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four
upstream receiver channels and a downstream transmitter channel. Each upstream
channel operates at 5.12 Gbps, while the downstream channel operates at 2.56
Gbps. In each upstream channel, GBCR equalizes a signal received through a
5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a
recovered clock, and drives an optical transmitter. In the downstream channel,
GBCR receives the data from an optical receiver and drives the same type of
cable as the upstream channels. The output jitter of an upstream channel is
26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps.
Each upstream channel consumes 78 mW and each downstream channel consumes 27
mW. Simulation results of the upstream test channel suggest that a significant
jitter reduction could be achieved with minimally increased power consumption
by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE)
in addition to the linear equalization of the baseline channel. GBCR is
designed in a 65-nm CMOS technology.
