  In the future, embedded processors must process more computation-intensive
network applications and internet traffic and packet-processing tasks become
heavier and sophisticated. Since the processor performance is severely related
to the average memory access delay and also the number of processor registers
affects the performance, cache and register file are two major parts in
designing embedded processor architecture. Although increasing cache and
register file size leads to performance improvement in embedded applications
and packet-processing tasks in high traffic networks with too much packets, the
increased area, power consumption and memory hierarchy delay are the overheads
of these techniques. Therefore, implementing these components in the optimum
size is of significant interest in the design of embedded processors. This
paper explores the effect of cache and register file size on the processor
performance to calculate the optimum size of these components for embedded
applications. Experimental results show that although having bigger cache and
register file is one of the performance improvement approaches in embedded
processors, however, by increasing the size of these parameters over a
threshold level, performance improvement is saturated and then, decreased.
