  Current-steering (CS) digital-to-analog converters (DACs) generate analog
signals by combining weighted current sources. Ideally, the current sources are
combined at each switching instant simultaneously. However, this is not true in
practice due to timing mismatch, resulting in nonlinear distortion. This work
uses the equivalent timing error model, introduced by previous work, to analyze
the signal-to-distortion ratio (SDR) resulting from these timing errors. Using
a behavioral simulation model we demonstrate that our analysis is significantly
more accurate than the previous methods. We also use our simulation model to
investigate the effect of timing mismatch in partially-segmented CS-DACs, i.e.,
those comprised of both equally-weighted and binary-weighted current sources.
