  The capacity of offloading data and control tasks to the network is becoming
increasingly important, especially if we consider the faster growth of network
speed when compared to CPU frequencies. In-network compute alleviates the host
CPU load by running tasks directly in the network, enabling additional
computation/communication overlap and potentially improving overall application
performance. However, sustaining bandwidths provided by next-generation
networks, e.g., 400 Gbit/s, can become a challenge. sPIN is a programming model
for in-NIC compute, where users specify handler functions that are executed on
the NIC, for each incoming packet belonging to a given message or flow. It
enables a CUDA-like acceleration, where the NIC is equipped with lightweight
processing elements that process network packets in parallel. We investigate
the architectural specialties that a sPIN NIC should provide to enable
high-performance, low-power, and flexible packet processing. We introduce
PsPIN, a first open-source sPIN implementation, based on a multi-cluster RISC-V
architecture and designed according to the identified architectural
specialties. We investigate the performance of PsPIN with cycle-accurate
simulations, showing that it can process packets at 400 Gbit/s for several use
cases, introducing minimal latencies (26 ns for 64 B packets) and occupying a
total area of 18.5 mm 2 (22 nm FDSOI).
