  Despite the promises of low-power and high-frequency of single-flux quantum
(SFQ) technology, scaling these circuits remains a serious challenge that
motivates the support of multiple SFQ clock domains. Towards this end, this
paper analyzes the impact of setup time violations and metastability in SFQ
circuits comparing the derived analytical models to their CMOS counterparts. It
then extends this model to estimate the Mean Time Between Failure (MTBF) of
flip-flop-based synchronizers and curve fits this model to simulations in the
state-of-the-art SFQ5ee process. Interestingly, we find a two-flop SFQ
synchronizer has an estimated MTBF of 10^6 years.
