  Artificial neural networks have become ubiquitous in modern life, which has
triggered the emergence of a new class of application specific integrated
circuits for their acceleration. ReRAM-based accelerators have gained
significant traction due to their ability to leverage in-memory computations.
In a crossbar structure, they can perform multiply-and-accumulate operations
more efficiently than standard CMOS logic. By virtue of being resistive
switches, ReRAM switches can only reliably store one of two states. This is a
severe limitation on the range of values in a computational kernel. This paper
presents a novel scheme in alleviating the single-bit-per-device restriction by
exploiting frequency dependence of v-i plane hysteresis, and assigning kernel
information not only to the device conductance but also partially distributing
it to the frequency of a time-varying input. We show this approach reduces
average power consumption for a single crossbar convolution by up to a factor
of x16 for an unsigned 8-bit input image, where each convolutional process
consumes a worst-case of 1.1mW, and reduces area by a factor of x8, without
reducing accuracy to the level of binarized neural networks. This presents a
massive saving in computing cost when there are many simultaneous in-situ
multiply-and-accumulate processes occurring across different crossbars.
