  Early generations of superconducting quantum annealing processors have
provided a valuable platform for studying the performance of a scalable quantum
computing technology. These studies have directly informed our approach to the
design of the next-generation processor. Our design priorities for this
generation include an increase in per-qubit connectivity, a problem Hamiltonian
energy scale similar to previous generations, reduced Hamiltonian specification
errors, and an increase in the processor scale that also leaves programming and
readout times fixed or reduced. Here we discuss the specific innovations that
resulted in a processor architecture that satisfies these design priorities.
