  Virtually indexed and virtually tagged (VIVT) caches are an attractive option
for micro-processor level-1 caches, because of their fast response time and
because they are cheaper to implement than more complex caches such as
virtually-indexed physical-tagged (VIPT) caches. The level-1 VIVT cache becomes
even simpler to construct if it is implemented as a direct-mapped cache
(VIVT-DM cache). However, VIVT and VIVT-DM caches have some drawbacks. When the
number of sets in the cache is larger than the smallest page size, there is a
possibility of synonyms (two or more virtual addresses mapped to the same
physical address) existing in the cache. Further, maintenance of cache
coherence across multiple processors requires a physical to virtual translation
mechanism in the hardware. We describe a simple, efficient reverse lookup table
based approach to address the synonym and the coherence problems in VIVT (both
set associative and direct-mapped) caches. In particular, the proposed scheme
does not disturb the critical memory access paths in a typical micro-processor,
and requires a low overhead for its implementation. We have implemented and
validated the scheme in the AJIT 32-bit microprocessor core (an implementation
of the SPARC-V8 ISA) and the implementation uses approximately 2% of the gates
and 5.3% of the memory bits in the processor core.
