  Memory disaggregation has emerged as an alternative to traditional server
architecture in data centers. This paper introduces DRackSim, a simulation
infrastructure to model rack-scale hardware disaggregated memory. DRackSim
models multiple compute nodes, memory pools, and a rack-scale interconnect
similar to GenZ. An application-level simulation approach simulates an x86
out-of-order multi-core processor with a multi-level cache hierarchy at compute
nodes. A queue-based simulation is used to model a remote memory controller and
rack-level interconnect, which allows both cache-based and page-based access to
remote memory. DRackSim models a central memory manager to manage address space
at the memory pools. We integrate community-accepted DRAMSim2 to perform memory
simulation at local and remote memory using multiple DRAMSim2 instances. An
incremental approach is followed to validate the core and cache subsystem of
DRackSim with that of Gem5. We measure the performance of various HPC workloads
and show the performance impact for different nodes/pools configuration.
