  Reverse engineering an integrated circuit netlist is a powerful tool to help
detect malicious logic and counteract design piracy. A critical challenge in
this domain is the correct classification of data-path and control-logic
registers in a design. We present ReIGNN, a novel learning-based register
classification methodology that combines graph neural networks (GNNs) with
structural analysis to classify the registers in a circuit with high accuracy
and generalize well across different designs. GNNs are particularly effective
in processing circuit netlists in terms of graphs and leveraging properties of
the nodes and their neighborhoods to learn to efficiently discriminate between
different types of nodes. Structural analysis can further rectify any registers
misclassified as state registers by the GNN by analyzing strongly connected
components in the netlist graph. Numerical results on a set of benchmarks show
that ReIGNN can achieve, on average, 96.5% balanced accuracy and 97.7%
sensitivity across different designs.
