  Exascale computing and its associated applications have required increasing
degrees of efficiency. Semiconductor-Transistor-based Circuits (STbCs) have
struggled with increasing the GHz frequency while dealing with power
dissipation issues. Emerging as an alternative to STbC, single flux quantum
(SFQ) logic in the superconducting electrons (SCE) technology promises
higher-speed clock frequencies at ultra-low power consumption. However, its
quantized pulse-based operation and high environmental requirements, process
variations and other SFQ-specific non-idealities are the significant causes of
logic error for SFQ circuits. A suitable method of minimizing the impact of the
afore-mentioned error sources is to minimize the number of Josephson Junctions
(JJs) in the circuits, hence an essential part of the design flow of large SFQ
circuits. This paper presents a novel SFQ logic synthesis framework that given
a netlist, offers an automated mapping solution including majority (MAJ) logic
with the goal of minimizing the number of JJs, while catering to the unique
characteristics and requirements of the design. Our experiments confirm that
our synthesis framework significantly outperforms the state-of-the-art academic
SFQ technology mapper, namely reducing the number of JJs on average by 35.0%.
