  This paper outlines an FPGA VLSI design methodology that was used to realize
a fully functioning FPGA chip in 130nm CMOS with improved routability and
memory robustness. The architectural design space exploration and synthesis
capability were enabled by the Verilog-to-Routing CAD tool. The capabilities of
this tool were extended to enable bitstream generation and deployment. To
validate the architecture and bitstream implementation, a Chisel (Constructing
Hardware in the Embedded Scala Language) model of the FPGA was created to
rapidly verify the microarchitectural details of the device prior to schematic
design. A custom carrier board and configuration tool were used to verify
correct operational characteristics of the FPGA over various resource
utilizations and clock frequencies.
