  Phosphorus donor spins in silicon offer a number of promising characteristics
for the implementation of robust qubits. Amongst various concepts for scale-up,
the shared-control concept takes advantage of 3D scanning tunnelling microscope
(STM) fabrication techniques to minimise the number of control lines, allowing
the donors to be placed at the pitch limit of $\geq$30 nm, enabling dipole
interactions. A fundamental challenge is to exploit the faster exchange
interaction, however, the donor spacings required are typically 15 nm or less,
and the exchange interaction is notoriously sensitive to lattice site
variations in donor placement. This work presents a proposal for a fast
exchange-based surface-code quantum computer architecture which explicitly
addresses both donor placement imprecision commensurate with the
atomic-precision fabrication techniques and the stringent qubit pitch
requirements. The effective pitch is extended by incorporation of an
intermediate donor acting as an exchange-interaction switch. We consider both
global control schemes and a scheduled series of operations by designing GRAPE
pulses for individual CNOTs based on coupling scenarios predicted by atomistic
tight-binding simulations. The architecture is compatible with the existing
fabrication capabilities and may serve as a blueprint for the experimental
implementation of a full-scale fault-tolerant quantum computer based on donor
impurities in silicon.
