  Hardware IP protection has been one of the most critical areas of research in
the past years. Recently, attacks on hardware IPs (such as reverse engineering
or cloning) have evolved as attackers have developed sophisticated techniques.
Therefore, hardware obfuscation has been introduced as a powerful tool to
protect IPs against piracy attacks. However, many recent attempts to break
existing obfuscation methods have been successful in unlocking the IP and
restoring its functionality. In this paper, we propose SARO, a Scalable
Attack-Resistant Obfuscation that provides a robust functional and structural
design transformation process. SARO treats the target circuit as a graph, and
performs a partitioning algorithm to produce a set of sub-graphs, then applies
our novel Truth Table Transformation (T3) process to each partition. We also
propose the $T3_{metric}$, which is developed to quantify the structural and
functional design transformation level caused by the obfuscation process. We
evaluate SARO on ISCAS85 and EPFL benchmarks, and provide full security and
performance analysis of our proposed framework.
