  Neural networks have proven to be extremely powerful tools for modern
artificial intelligence applications, but computational and storage complexity
remain limiting factors. This paper presents two compatible contributions
towards reducing the time, energy, computational, and storage complexities
associated with multilayer perceptrons. Pre-defined sparsity is proposed to
reduce the complexity during both training and inference, regardless of the
implementation platform. Our results show that storage and computational
complexity can be reduced by factors greater than 5X without significant
performance loss. The second contribution is an architecture for hardware
acceleration that is compatible with pre-defined sparsity. This architecture
supports both training and inference modes and is flexible in the sense that it
is not tied to a specific number of neurons. For example, this flexibility
implies that various sized neural networks can be supported on various sized
Field Programmable Gate Array (FPGA)s.
