  We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm
CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the
top metal layer of the process for the trap electrodes. The process includes
doped active regions and metal interconnect layers, allowing for co-fabrication
of standard CMOS circuitry as well as devices for optical control and
measurement. With one of the interconnect layers defining a ground plane
between the trap electrode layer and the p-type doped silicon substrate, ion
loading is robust and trapping is stable. We measure a motional heating rate
comparable to those seen in surface-electrode traps of similar size. This is
the first demonstration of scalable quantum computing hardware, in any
modality, utilizing a commercial CMOS process, and it opens the door to
integration and co-fabrication of electronics and photonics for large-scale
quantum processing in trapped-ion arrays.
