  The expansive globalization of the semiconductor supply chain has introduced
numerous untrusted entities into different stages of a device's lifecycle. To
make matters worse, the increase complexity in the design as well as aggressive
time to market requirements of the newer generation of integrated circuits can
lead either designers to unintentionally introduce security vulnerabilities or
verification engineers to fail in detecting them earlier in the design
lifecycle. These overlooked or undetected vulnerabilities can be exploited by
malicious entities in subsequent stages of the lifecycle through an ever
widening variety of hardware attacks. The ability to ascertain the provenance
of these vulnerabilities, therefore, becomes a pressing issue when the security
assurance across the whole lifecycle is required to be ensured. We posit that
if there is a malicious or unintentional breach of security policies of a
device, it will be reflected in the form of anomalies in the traditional
design, verification and testing activities throughout the lifecycle. With
that, a digital simulacrum of a device's lifecycle, called a digital twin (DT),
can be formed by the data gathered from different stages to secure the
lifecycle of the device. In this paper, we put forward a realization of
intertwined relationships of security vulnerabilities with data available from
the silicon lifecycle and formulate different components of an AI driven DT
framework. The proposed DT framework leverages these relationships and
relational learning to achieve Forward and Backward Trust Analysis
functionalities enabling security aware management of the entire lifecycle.
Finally, we provide potential future research avenues and challenges for
realization of the digital twin framework to enable secure semiconductor
lifecycle management.
