  Efficient and real time segmentation of color images has a variety of
importance in many fields of computer vision such as image compression, medical
imaging, mapping and autonomous navigation. Being one of the most
computationally expensive operation, it is usually done through software imple-
mentation using high-performance processors. In robotic systems, however, with
the constrained platform dimensions and the need for portability, low power
consumption and simultaneously the need for real time image segmentation, we
envision hardware parallelism as the way forward to achieve higher
acceleration. Field-programmable gate arrays (FPGAs) are among the best suited
for this task as they provide high computing power in a small physical area.
They exceed the computing speed of software based implementations by breaking
the paradigm of sequential execution and accomplishing more per clock cycle
operations by enabling hardware level parallelization at an architectural
level. In this paper, we propose three novel architectures of a well known
Efficient Graph based Image Segmentation algorithm. These proposed
implementations optimizes time and power consumption when compared to software
implementations. The hybrid design proposed, has notable furtherance of
acceleration capabilities delivering atleast 2X speed gain over other implemen-
tations, which henceforth allows real time image segmentation that can be
deployed on Mobile Robotic systems.
