  Polar codes are a recently proposed class of block codes that provably
achieve the capacity of various communication channels. They received a lot of
attention as they can do so with low-complexity encoding and decoding
algorithms, and they have an explicit construction. Their recent inclusion in a
5G communication standard will only spur more research. However, only a couple
of ASICs featuring decoders for polar codes were fabricated, and none of them
implements a list-based decoding algorithm. In this paper, we present ASIC
measurement results for a fabricated 28 nm CMOS chip that implements two
different decoders: the first decoder is tailored toward error-correction
performance and flexibility. It supports any code rate as well as three
different decoding algorithms: successive cancellation (SC), SC flip and SC
list (SCL). The flexible decoder can also decode both non-systematic and
systematic polar codes. The second decoder targets speed and energy efficiency.
We present measurement results for the first silicon-proven SCL decoder, where
its coded throughput is shown to be of 306.8 Mbps with a latency of 3.34 us and
an energy per bit of 418.3 pJ/bit at a clock frequency of 721 MHz for a supply
of 1.3 V. The energy per bit drops down to 178.1 pJ/bit with a more modest
clock frequency of 308 MHz, lower throughput of 130.9 Mbps and a reduced supply
voltage of 0.9 V. For the other two operating modes, the energy per bit is
shown to be of approximately 95 pJ/bit. The less flexible high-throughput
unrolled decoder can achieve a coded throughput of 9.2 Gbps and a latency of
628 ns for a measured energy per bit of 1.15 pJ/bit at 451 MHz.
