  Neural decoders for quantum error correction (QEC) rely on neural networks to
classify syndromes extracted from error correction codes and find appropriate
recovery operators to protect logical information against errors. Despite the
good performance of neural decoders, important practical requirements remain to
be achieved, such as minimizing the decoding time to meet typical rates of
syndrome generation in repeated error correction schemes, and ensuring the
scalability of the decoding approach as the code distance increases. Designing
a dedicated integrated circuit to perform the decoding task in co-integration
with a quantum processor appears necessary to reach these decoding time and
scalability requirements, as routing signals in and out of a cryogenic
environment to be processed externally leads to unnecessary delays and an
eventual wiring bottleneck. In this work, we report the design and performance
analysis of a neural decoder inference accelerator based on an in-memory
computing (IMC) architecture, where crossbar arrays of resistive memory devices
are employed to both store the synaptic weights of the decoder neural network
and perform analog matrix-vector multiplications during inference. In
proof-of-concept numerical experiments supported by experimental measurements,
we investigate the impact of TiO$_\textrm{x}$-based memristive devices'
non-idealities on decoding accuracy. Hardware-aware training methods are
developed to mitigate the loss in accuracy, allowing the memristive neural
decoders to achieve a pseudo-threshold of $9.23\times 10^{-4}$ for the
distance-three surface code, whereas the equivalent digital neural decoder
achieves a pseudo-threshold of $1.01\times 10^{-3}$. This work provides a
pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated
QEC.
