  The computational complexity of neural networks for large scale or real-time
applications necessitates hardware acceleration. Most approaches assume that
the network architecture and parameters are unknown at design time, permitting
usage in a large number of applications. This paper demonstrates, for the case
where the neural network architecture and ternary weight values are known a
priori, that extremely high throughput implementations of neural network
inference can be made by customising the datapath and routing to remove
unnecessary computations and data movement. This approach is ideally suited to
FPGA implementations as a specialized implementation of a trained network
improves efficiency while still retaining generality with the reconfigurability
of an FPGA. A VGG style network with ternary weights and fixed point
activations is implemented for the CIFAR10 dataset on Amazon's AWS F1 instance.
This paper demonstrates how to remove 90% of the operations in convolutional
layers by exploiting sparsity and compile-time optimizations. The
implementation in hardware achieves 90.9 +/- 0.1% accuracy and 122 k frames per
second, with a latency of only 29 us, which is the fastest CNN inference
implementation reported so far on an FPGA.
