  The Versal Adaptive Compute Acceleration Platform (ACAP) is a new
architecture that combines AI Engines (AIEs) with reconfigurable fabric. This
architecture offers significant acceleration potential for uniform recurrences
in various domains, such as deep learning, high-performance computation, and
signal processing. However, efficiently mapping these computations onto the
Versal ACAP architecture while achieving high utilization of AIEs poses a
challenge.
  To address this issue, we propose a mapping scheme called \fname, which aims
to accelerate uniform recurrences on the Versal ACAP architecture by leveraging
the features of both the hardware and the computations. Considering the array
architecture of AIEs, our approach utilizes space-time transformations based on
the polyhedral model to generate legally optimized systolic array mappings.
Concurrently, we have developed a routing-aware PLIO assignment algorithm
tailored for communication on the AIE array, and the algorithm aims at
successful compilation while maximizing array utilization. Furthermore, we
introduce an automatic mapping framework. This framework is designed to
generate the corresponding executable code for uniform recurrences, which
encompasses the AIE kernel program, programmable logic bitstreams, and the host
program. The experimental results validate the effectiveness of our mapping
scheme. Specifically, when applying our scheme to matrix multiplication
computations on the VCK5000 board, we achieve a throughput of 4.15TOPS on float
data type, which is 1.11$\times$ higher compared to the state-of-the-art
accelerator on the Versal ACAP architecture.
