  DRAM-based memory is a critical factor that creates a bottleneck on the
system performance since the processor speed largely outperforms the DRAM
latency. In this thesis, we develop a low-cost mechanism, called ChargeCache,
which enables faster access to recently-accessed rows in DRAM, with no
modifications to DRAM chips. Our mechanism is based on the key observation that
a recently-accessed row has more charge and thus the following access to the
same row can be performed faster. To exploit this observation, we propose to
track the addresses of recently-accessed rows in a table in the memory
controller. If a later DRAM request hits in that table, the memory controller
uses lower timing parameters, leading to reduced DRAM latency. Row addresses
are removed from the table after a specified duration to ensure rows that have
leaked too much charge are not accessed with lower latency. We evaluate
ChargeCache on a wide variety of workloads and show that it provides
significant performance and energy benefits for both single-core and multi-core
systems.
