  A system-on-chip (SoC) photonic-electronic linear-algebra accelerator with
the features of wavelength-division-multiplexing (WDM) based broadband
photodetections and high-dimensional matrix-inversion operations fabricated in
advanced monolithic silicon-photonics (M-SiPh) semiconductor process technology
is proposed to achieve substantial leaps in computation density and energy
efficiency, including realistic considerations of energy/area overhead due to
electronic/photonic on-chip conversions, integrations, and calibrations through
holistic co-design methodologies to support linear-detection based massive
multiple-input multiple-output (MIMO) decoding technology requiring the
inversion of channel matrices and other emergent applications limited by
linear-algebra computation capacities.
