  Implementing large-scale quantum circuits is one of the challenges of quantum
computing. One of the central challenges of accurately modeling the
architecture of these circuits is to schedule a quantum application and
generate the layout while taking into account the cost of communications and
classical resources as well as the maximum exploitable parallelism. In this
paper, we present and evaluate a design flow for arbitrary quantum circuits in
ion trap technology. Our design flow consists of two parts. First, a scheduler
takes a description of a circuit and finds the best order for the execution of
its quantum gates using integer linear programming (ILP) regarding the
classical resources (qubits) and instruction dependencies. Then a layout
generator receives the schedule produced by the scheduler and generates a
layout for this circuit using a graph-drawing algorithm. Our experimental
results show that the proposed flow decreases the average latency of quantum
circuits by about 11% for a set of attempted benchmarks and by about 9% for
another set of benchmarks compared with the best in literature.
