  This paper concentrates on building a multi-antenna FPGA based Channel
Sounder with single transmitter and multiple receivers to realize wireless
propagation characteristics of an indoor environment. A DSSS signal (spread
with a real maximum length PN sequence) is transmitted, which is correlated
with the same PN sequence at each receiver to obtain the power delay profile .
Multiple power delay profiles are averaged and the result is then sent to host.
To utilize high bandwidth, the computationally expensive tasks related to
generation and parallel correlation of PN sequences are moved to the FPGA
present in each USRP (Universal Software Radio Peripheral). Channel sounder
blocks were built using Vivado HLS and integrated with RFNoC (RF Network on
Chip) framework, which were then used on USRP X310 devices.
