  Large scale scientific instrumentation-and-control FPGA gateware designs have
numerous run-time settable parameters. These can be used either for user-level
control or by automated processes (e.g., calibration). The number of such
parameters in a single design can reach on the order of 1000, and keeps
evolving as the gateware and its functionality evolves. One must keep track of
which module the registers belong to, where the registers need to be decoded,
and how to express the properties (or even semantics) of the register to the
next level of user or software. Note, the registers maybe embedded anywhere
throughout the module hierarchy. Purely manual handling of these tasks by HDL
developers is considered burdensome and error-prone at this scale. Typically
these registers are writable via an on-chip bus, vaguely VME-like, that is
controlled by an on-chip or off-chip CPU. There have been several attempts in
the community to address this task at different levels. However, we have found
no tool that is able to generate a register map, generate decoders and encoders
with minimal overhead to the developer. So, here we present a tool that scours
native HDL source files and looks for specific language-supported attributes
and automatically generates a register map and bus decoders, respecting
multiple clock domains, and presents a JSON file to the network that maps
register names to addresses.
