  The performance of deep learning algorithms such as neural networks (NNs) has
increased tremendously recently, and they can achieve state-of-the-art
performance in many domains. However, due to memory and computation resource
constraints, implementing NNs on edge devices is a challenging task. Therefore,
hardware accelerators such as computation-in-memory (CIM) with memristive
devices have been developed to accelerate the most common operations, i.e.,
matrix-vector multiplication. However, due to inherent device properties,
external environmental factors such as temperature, and an immature fabrication
process, memristors suffer from various non-idealities, including defects and
variations occurring during manufacturing and runtime. Consequently, there is a
lack of complete confidence in the predictions made by the model. To improve
confidence in NN predictions made by hardware accelerators in the presence of
device non-idealities, in this paper, we propose a Bayesian test vector
generation framework that can estimate the model uncertainty of NNs implemented
on memristor-based CIM hardware. Compared to the conventional point estimate
test vector generation method, our method is more generalizable across
different model dimensions and requires storing only one test Bayesian vector
in the hardware. Our method is evaluated on different model dimensions, tasks,
fault rates, and variation noise to show that it can consistently achieve
$100\%$ coverage with only $0.024$ MB of memory overhead.
