  Spiking Neural Networks (SNN) are an emerging type of biologically plausible
and efficient Artificial Neural Network (ANN). This work presents the
development of a hardware accelerator for a SNN for high-performance inference,
targeting a Xilinx Artix-7 Field Programmable Gate Array (FPGA). The model used
inside the neuron is the Leaky Integrate and Fire (LIF). The execution is
clock-driven, meaning that the internal state of the neuron is updated at every
clock cycle, even in absence of spikes. The inference capabilities of the
accelerator are evaluated using the MINST dataset. The training is performed
offline on a full precision model. The results show a good improvement in
performance if compared with the state-of-the-art accelerators, requiring
215{\mu}s per image. The energy consumption is slightly higher than the most
optimized design, with an average value of 13mJ per image. The test design
consists of a single layer of four-hundred neurons and uses around 40% of the
available resources on the FPGA. This makes it suitable for a time-constrained
application at the edge, leaving space for other acceleration tasks on the
FPGA.
