  Wireless Network-on-Chip (WNoC) has been proposed as a low-latency,
versatile, and broadcast-capable complement to current interconnects in the
quest for satisfying the ever-increasing communications needs of modern
computing systems. However, to realize the promise of WNoC, multiple wireless
links operating at several tens of Gb/s need to be created within a computing
package. Unfortunately, the highly integrated and enclosed nature of such
computing packages incurs significant Co-Channel Interference (CCI) and
Inter-Symbol Interference (ISI), not only preventing the deployment of multiple
spatial channels, but also severely limiting the symbol rate of each individual
channel. In this work, Time Reversal (TR) is proposed as a means to compensate
the channel impairments and enable multiple concurrent high-speed links at the
chip scale. We offer evidence, via full-wave simulations at 140 GHz, that TR
can increase the symbol rate by an order of magnitude and allow the deployment
of multiple concurrent links towards achieving aggregate speeds in excess of
100 Gb/s. Finally, the challenges relative to the realization of TR at the chip
scale are analyzed from the implementation, protocol support, and architectural
perspectives.
