  Macro placement is a critical phase in chip design, which becomes more
intricate when involving general rectilinear macros and layout areas.
Furthermore, macro placement that incorporates human-like constraints, such as
design hierarchy and peripheral bias, has the potential to significantly reduce
the amount of additional manual labor required from designers. This study
proposes a methodology that leverages an approach suggested by Google's Circuit
Training (G-CT) to provide a learning-based macro placer that not only supports
placing rectilinear cases, but also adheres to crucial human-like design
principles. Our experimental results demonstrate the effectiveness of our
framework in achieving power-performance-area (PPA) metrics and in obtaining
placements of high quality, comparable to those produced with human
intervention. Additionally, our methodology shows potential as a generalized
model to address diverse macro shapes and layout areas.
