  The scaling of high density NOR Flash memory devices with multi level cell
(MLC) hits the reliability break wall because of relatively high intrinsic bit
error rate (IBER). The chip maker companies offer two solutions to meet the
output bit error rate (OBER) specification: either partial coverage with error
correction code (ECC) or data storage in single level cell (SLC) with
significant increase of the die cost. The NOR flash memory allows to write
information in small portions, therefore the full error protection becomes
costly due to high required redundancy, e.g. $\sim$50%. This is very different
from the NAND flash memory writing at once large chunks of information; NAND
ECC requires just $\sim$10% redundancy. This paper gives an analysis of a novel
error protection scheme applicable to NOR storage of one byte. The method does
not require any redundant cells, but assumes 5th program level. The information
is mapped to states in the 4-dimensional space separated by the minimal
Manhattan distance equal 2. This code preserves the information capacity: one
byte occupies four memory cells. We demonstrate the OBER $\sim$ IBER$^{3/2}$
scaling law, where IBER is calculated for the 4-level MLC memory. As an
example, the 4-level MLC with IBER $\sim10^{-9}$, which is unacceptable for
high density products, can be converted to OBER $\sim10^{-12}$. We assume that
the IBER is determined by the exponentially distributed read noise. This is the
case for NOR Flash memory devices, since the exponential tails are typical for
the random telegraph signal (RTS) noise and for most of the charge loss, charge
gain, and charge sharing data losses.
