  Floating point multiplication is a crucial operation in high power computing
applications such as image processing, signal processing etc. And also
multiplication is the most time and power consuming operation. This paper
proposes an efficient method for IEEE 754 floating point multiplication which
gives a better implementation in terms of delay and power. A combination of
Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is
used to implement unsigned binary multiplier for mantissa multiplication. The
multiplier is implemented using Verilog HDL, targeted on Spartan-3E and
Virtex-4 FPGA.
