  Combinational or Classical logic circuits dissipate heat for every bit of
information that is lost. Information is lost when the input vector cannot be
recovered from its corresponding output vector. Reversible logic circuit
implements only the functions having one-to-one mapping between its input and
output vectors and therefore naturally takes care of heating. Reversible logic
design becomes one of the promising research directions in low power
dissipating circuit design in the past few years and has found its application
in low power CMOS design, digital signal processing and nanotechnology. This
paper presents the efficient approaches for designing fault tolerant reversible
fast adders that implement carry look-ahead and carry-skip logic. The proposed
high speed reversible adders include MIG gates for the realization of its basic
building block. The MIG gate is universal and parity preserving. It allows any
fault that affects no more than a single signal readily detectable at the
circuit's primary outputs. It has also been demonstrated that the proposed
design offers less hardware complexity and is efficient in terms of gate count,
garbage outputs and constant inputs than the existing counterparts.
