  The domain wall-magnetic tunnel junction (DW-MTJ) is a versatile device that
can simultaneously store data and perform computations. These three-terminal
devices are promising for digital logic due to their nonvolatility, low-energy
operation, and radiation hardness. Here, we augment the DW-MTJ logic gate with
voltage controlled magnetic anisotropy (VCMA) to improve the reliability of
logical concatenation in the presence of realistic process variations. VCMA
creates potential wells that allow for reliable and repeatable localization of
domain walls. The DW-MTJ logic gate supports different fanouts, allowing for
multiple inputs and outputs for a single device without affecting area. We
simulate a systolic array of DW-MTJ Multiply-Accumulate (MAC) units with 4-bit
and 8-bit precision, which uses the nonvolatility of DW-MTJ logic gates to
enable fine-grained pipelining and high parallelism. The DW-MTJ systolic array
provides comparable throughput and efficiency to state-of-the-art CMOS systolic
arrays while being radiation-hard. These results improve the feasibility of
using domain wall-based processors, especially for extreme-environment
applications such as space.
