  The new open and royalty-free RISC-V ISA is attracting interest across the
whole computing continuum, from microcontrollers to supercomputers.
High-performance RISC-V processors and accelerators have been announced, but
RISC-V-based HPC systems will need a holistic co-design effort, spanning
memory, storage hierarchy interconnects and full software stack. In this paper,
we describe Monte Cimone, a fully-operational multi-blade computer prototype
and hardware-software test-bed based on U740, a double-precision capable
multi-core, 64-bit RISC-V SoC. Monte Cimone does not aim to achieve strong
floating-point performance, but it was built with the purpose of "priming the
pipe" and exploring the challenges of integrating a multi-node RISC-V cluster
capable of providing an HPC production stack including interconnect, storage
and power monitoring infrastructure on RISC-V hardware. We present the results
of our hardware/software integration effort, which demonstrate a remarkable
level of software and hardware readiness and maturity - showing that the first
generation of RISC-V HPC machines may not be so far in the future.
