  Multiplication of two sparse matrices is a key operation in the simulation of
the electronic structure of systems containing thousands of atoms and
electrons. The highly optimized sparse linear algebra library DBCSR
(Distributed Block Compressed Sparse Row) has been specifically designed to
efficiently perform such sparse matrix-matrix multiplications. This library is
the basic building block for linear scaling electronic structure theory and low
scaling correlated methods in CP2K. It is parallelized using MPI and OpenMP,
and can exploit GPU accelerators by means of CUDA. We describe a performance
comparison of DBCSR on systems with Intel Xeon Phi Knights Landing (KNL)
processors, with respect to systems with Intel Xeon CPUs (including systems
with GPUs). We find that the DBCSR on Cray XC40 KNL-based systems is 11%-14%
slower than on a hybrid Cray XC50 with Nvidia P100 cards, at the same number of
nodes. When compared to a Cray XC40 system equipped with dual-socket Intel Xeon
CPUs, the KNL is up to 24% faster.
