  Contemporary field-programmable gate arrays (FPGAs) are predestined for the
application of finite impulse response (FIR) filters. Their embedded digital
signal processing (DSP) blocks for multiply-accumulate operations enable
efficient fixed-point computations, in cases where the filter structure is
accurately mapped to the dedicated hardware architecture. This brief presents a
generic systolic structure for high-order FIR filters, efficiently exploiting
the hardware resources of an FPGA in terms of routability and timing. Although
this seems to be an easily implementable task, the synthesizing tools require
an adaptation of the straightforward digital filter implementation for an
optimal mapping. Using the example of a symmetric FIR filter with 90 taps, we
demonstrate the performance of the proposed structure with FPGAs from Xilinx
and Altera. The implementation utilizes less than 1% of slice logic and runs at
clock frequencies up to 526 MHz. Moreover, an enhancement of the structure
ultimately provides an extended dynamic range for the quantized coefficients
without the costs of additional slice logic.
