  Video processing systems such as HEVC requiring low energy consumption needed
for the multimedia market has lead to extensive development in fast algorithms
for the efficient approximation of 2-D DCT transforms. The DCT is employed in a
multitude of compression standards due to its remarkable energy compaction
properties. Multiplier-free approximate DCT transforms have been proposed that
offer superior compression performance at very low circuit complexity. Such
approximations can be realized in digital VLSI hardware using additions and
subtractions only, leading to significant reductions in chip area and power
consumption compared to conventional DCTs and integer transforms. In this
paper, we introduce a novel 8-point DCT approximation that requires only 14
addition operations and no multiplications. The proposed transform possesses
low computational complexity and is compared to state-of-the-art DCT
approximations in terms of both algorithm complexity and peak signal-to-noise
ratio. The proposed DCT approximation is a candidate for reconfigurable video
standards such as HEVC. The proposed transform and several other DCT
approximations are mapped to systolic-array digital architectures and
physically realized as digital prototype circuits using FPGA technology and
mapped to 45 nm CMOS technology.
