  We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit
(ALU). The ALU design employs wave-pipelined instruction execution and features
modular bit-slice architecture that is easily extendable to any number of bits
and adaptable to current recycling. A carry signal synchronized with an
asynchronous instruction propagation provides the wave-pipeline operation of
the ALU. The ALU instruction set consists of 14 arithmetical and logical
instructions. It has been designed and simulated for operation up to a 10 GHz
clock rate at the 10-kA/cm2 fabrication process. The ALU is embedded into a
shift-register-based high-frequency testbed with on-chip clock generator to
allow for comprehensive high frequency testing for all possible operands. The
8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with
MIT Lincoln Lab 10-kA/cm2 SFQ5ee fabrication process featuring eight Nb wiring
layers and a high-kinetic inductance layer needed for ERSFQ technology. We
evaluated the bias margins for all instructions and various operands at both
low and high frequency clock. At low frequency, clock and all instruction
propagation through ALU were observed with bias margins of +/-11% and +/-9%,
respectively. Also at low speed, the ALU exhibited correct functionality for
all arithmetical and logical instructions with +/-6% bias margins. We tested
the 8-bit ALU for all instructions up to 2.8 GHz clock frequency.
