  The integration of III-V on silicon is still a hot topic as it will open up a
way to co-integrate Si CMOS logic with photonic vices. To reach this aim,
several hurdles should be solved, and more particularly the generation of
antiphase boundaries (APBs) at the III-V/Si(001) interface. Density functional
theory (DFT) has been used to demonstrate the existence of a double-layer steps
on nominal Si(001) which is formed during annealing under proper hydrogen
chemical potential. This phenomenon could be explained by the formation of
dimer vacancy lines which could be responsible for the preferential and
selective etching of one type of step leading to the double step surface
creation. To check this hypothesis, different experiments have been carried in
an industrial 300 mm MOCVD where the total pressure during the anneal step of
Si(001) surface has been varied. Under optimized conditions, an APBs-free GaAs
layer was grown on a nominal Si(001) surface paving the way for III-V
integration on silicon industrial platform.
