  Increase in image resolution require the ability of image sensors to pack an
increased number of circuit components in a given area. On the the other hand a
high speed processing of signals from the sensors require the ability of pixel
to carry out pixel parallel operations. In the paper, we propose a modified 3T
and 4T CMOS wide dynamic range pixels, which we refer as 2T-M and 3T-M
configurations, comprising of MOSFETS and memristors. The low leakage currents
and low area of memristors helps to achieve the objective of reducing the area,
while the possibility to create arrays of memristors and MOSFETs across
different layers within the chip, ensure the possibility to scale the circuit
architecture.
