  We optimize the area and latency of Shor's factoring while simultaneously
improving fault tolerance through: (1) balancing the use of ancilla generators,
(2) aggressive optimization of error correction, and (3) tuning the core adder
circuits. Our custom CAD flow produces detailed layouts of the physical
components and utilizes simulation to analyze circuits in terms of area,
latency, and success probability. We introduce a metric, called ADCR, which is
the probabilistic equivalent of the classic Area-Delay product. Our error
correction optimization can reduce ADCR by an order of magnitude or more.
Contrary to conventional wisdom, we show that the area of an optimized quantum
circuit is not dominated exclusively by error correction. Further, our adder
evaluation shows that quantum carry-lookahead adders (QCLA) beat ripple-carry
adders in ADCR, despite being larger and more complex. We conclude with what we
believe is one of most accurate estimates of the area and latency required for
1024-bit Shor's factorization: 7659 mm$^{2}$ for the smallest circuit and $6 *
10^8$ seconds for the fastest circuit.
