  Vertical field effect transistors (VOFETs) can offer short channel
architecture which can further enhance the performance at low operating
voltages which makes it more viable for organic electronics applications.
VOFETs can be prepared with low-cost techniques which reduce the high
processing costs and can also operate at high current density and relatively
higher frequencies. To further improve the performance, high current density,
and operating frequency the physics of charge carrier transport should be
understood well with the simulation. The main problem with VOFET is the high
off-current which is inevitable due to conduction from source to drain contact.
There have been many efforts in reducing the off-state current by the addition
of an insulating layer on top of the source electrode, which further increases
the complexity and cost of processing. Simulations based on device geometry,
contact barriers, and organic semiconductor parameters are carried out to study
the charge carrier transport in VOFET. The simulation results show that the
most important factor to enhance the performance is the device geometry or
architecture, which requires a specific fill factor, a ratio between the
exposed gate dielectric, and the total length with the source electrode.
Optimized VOFET architecture is then simulated for variation in contact barrier
and semiconductor parameters, which show some enhancement in performance but
also a rise in off-state current density.
