  This paper presents a physical mapping tool for quantum circuits, which
generates the optimal Universal Logic Block (ULB) that can perform any logical
fault-tolerant (FT) quantum operations with the minimum latency. The operation
scheduling, placement, and qubit routing problems tackled by the quantum
physical mapper are highly dependent on one another. More precisely, the
scheduling solution affects the quality of the achievable placement solution
due to resource pressures that may be created as a result of operation
scheduling whereas the operation placement and qubit routing solutions
influence the scheduling solution due to resulting distances between
predecessor and current operations, which in turn determines routing latencies.
The proposed flow for the quantum physical mapper captures these dependencies
by applying (i) a loose scheduling step, which transforms an initial quantum
data flow graph into one that explicitly captures the no-cloning theorem of the
quantum computing and then performs instruction scheduling based on a modified
force-directed scheduling approach to minimize the resource contention and
quantum circuit latency, (ii) a placement step, which uses timing-driven
instruction placement to minimize the approximate routing latencies while
making iterative calls to the aforesaid force-directed scheduler to correct
scheduling levels of quantum operations as needed, and (iii) a routing step
that finds dynamic values of routing latencies for the qubits. In addition to
the quantum physical mapper, an approach is presented to determine the single
best ULB size for a target quantum circuit by examining the latency of
different FT quantum operations mapped onto different ULB sizes and using
information about the occurrence frequency of operations on critical paths of
the target quantum algorithm to weigh these latencies.
