  The APEnet+ board delivers a point-to-point, low-latency, 3D torus network
interface card. In this paper we describe the latest generation of APEnet NIC,
APEnet v5, integrated in a PCIe Gen3 board based on a state-of-the-art, 28 nm
Altera Stratix V FPGA. The NIC features a network architecture designed
following the Remote DMA paradigm and tailored to tightly bind the computing
power of modern GPUs to the communication fabric. For the APEnet v5 board we
show characterizing figures as achieved bandwidth and BER obtained by
exploiting new high performance ALTERA transceivers and PCIe Gen3 compliancy.
