  We present the design and test results of a Time-to-Digital-Converter (TDC).
The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain
Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of
High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that
the TDC is required to consume less than 200 W for each pixel at the nominal
hit occupancy of 1%. To meet the low-power requirement, we use a single delay
line for both the Time of Arrival (TOA) and the Time over Threshold (TOT)
measurements without delay control. A double-strobe self-calibration scheme is
used to compensate for process variation, temperature, and power supply
voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall
performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps
within its effective dynamic range of 11.6 ns. The effective measurement
precision of the TOA is 5.6 ps and 9.9 ps with and without the nonlinearity
correction, respectively. The TDC block consumes 97 W at the hit occupancy of
1%. Over a temperature range from 23 C to 78 C and a power supply voltage range
from 1.05 V to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin
size of the TOA varies within 0.4%. The measured TDC performances meet the
requirements except that more tests will be performed in the future to verify
that the TDC complies with the radiation-tolerance specifications.
