  Driven by a need for ever increasing chip performance and inclusion of
innovative features, a growing number of semiconductor companies are opting for
all-inclusive System-on-Chip (SoC) architectures. Although Moore's Law has been
able to keep up with the demand for more complex logic, manufacturing large
dies still poses a challenge. Increasingly the solution adopted to minimize the
impact of silicon defects on manufacturing yield has been to split a design
into multiple smaller dies called chiplets which are then brought together on a
silicon interposer. Advanced 2.5D and 3D packaging techniques that enable this
kind of integration also promise increased power efficiency and opportunities
for heterogeneous integration.
  However, despite their advantages, chiplets are not without issues. Apart
from manufacturing challenges that come with new packaging techniques,
disaggregating a design into multiple logically and physically separate dies
introduces new threats, including the possibility of tampering with and probing
exposed data lines. In this paper we evaluate the exposure of chiplets to
probing by applying laser contactless probing techniques to a chiplet-based
AMD/Xilinx VU9P FPGA. First, we identify and map interposer wire drivers and
show that probing them is easier compared to probing internal nodes. Lastly, we
demonstrate that delay-based sensors, which can be used to protect against
physical probes, are insufficient to protect against laser probing as the delay
change due to laser probing is only 0.792ps even at 100\% laser power.
