  We present a first of its kind framework which overcomes a major challenge in
the design of digital systems that are resilient to reliability failures:
achieve desired resilience targets at minimal costs (energy, power, execution
time, area) by combining resilience techniques across various layers of the
system stack (circuit, logic, architecture, software, algorithm). This is also
referred to as cross-layer resilience. In this paper, we focus on
radiation-induced soft errors in processor cores. We address both single-event
upsets (SEUs) and single-event multiple upsets (SEMUs) in terrestrial
environments. Our framework automatically and systematically explores the large
space of comprehensive resilience techniques and their combinations across
various layers of the system stack (586 cross-layer combinations in this
paper), derives cost-effective solutions that achieve resilience targets at
minimal costs, and provides guidelines for the design of new resilience
techniques. We demonstrate the practicality and effectiveness of our framework
using two diverse designs: a simple, in-order processor core and a complex,
out-of-order processor core. Our results demonstrate that a carefully optimized
combination of circuit-level hardening, logic-level parity checking, and
micro-architectural recovery provides a highly cost-effective soft error
resilience solution for general-purpose processor cores. For example, a 50x
improvement in silent data corruption rate is achieved at only 2.1% energy cost
for an out-of-order core (6.1% for an in-order core) with no speed impact.
However, selective circuit-level hardening alone, guided by a thorough analysis
of the effects of soft errors on application benchmarks, provides a
cost-effective soft error resilience solution as well (with ~1% additional
energy cost for a 50x improvement in silent data corruption rate).
