  The BCD (Binary Coded Decimal) being the more accurate and human-readable
representation with ease of conversion, is prevailing in the computing and
electronic communication.In this paper, a tree-structured parallel BCD addition
algorithm is proposed with the reduced time complexity. BCD adder is more
effective with a LUT (Look-Up Table)-based design, due to FPGA (Field
Programmable Gate Array) technology's enumerable benefits and applications. A
size-minimal and depth-minimal LUT-based BCD adder circuit construction is the
main contribution of this paper.
