  In this work, using 3D device simulation, we perform an extensive gate to
source/drain underlap optimization for the recently proposed hybrid transistor,
HFinFET, to show that the underlap lengths can be suitably tuned to improve the
on-off ratio as well as the subthreshold characteristics in an ultra-short
channel n-type device without significant on performance degradation. We also
show that the underlap knob can be tuned to mitigate the device quality
degradation in presence of interface traps. The obtained results are shown to
be very promising when compared against ITRS 2009 performance projections as
well as published state of the art planar and non-planar Silicon MOSFET data of
comparable gate lengths using standard benchmarking techniques.
