  Nonbinary LDPC codes have shown superior performance close to the Shannon
limit. Compared to binary LDPC codes of similar lengths, they can reach orders
of magnitudes lower error rate. However, multitude of design freedoms of
nonbinary LDPC codes complicates the practical code and decoder design process.
Fast simulations are critically important to evaluate the pros and cons. Rapid
prototyping on FPGA is attractive but takes significant design efforts due to
its high design complexity. We propose a high-throughput reconfigurable
hardware emulation architecture with decoder and peripheral co-design. The
architecture enables a library and script-based framework that automates the
construction of FPGA emulations. Code and decoder design parameters are
programmed either during run time or by script in design time. We demonstrate
the capability of the framework in evaluating practical code and decoder design
by experimenting with two popular nonbinary LDPC codes, regular (2, dc) codes
and quasi-cyclic codes: each emulation model can be auto-constructed within
hours and the decoder delivers excellent error-correcting performance on a
Xilinx Virtex-5 FPGA with throughput of up to hundreds of Mbps.
