  Full Adder is one of the critical parts of logical and arithmetic units. So,
presenting a low power full adder cell reduces the power consumption of the
entire circuit. Also, using Nano-scale transistors, because of their unique
characteristics will save energy consumption and decrease the chip area. In
this paper we presented a low power full adder cell by using carbon nanotube
field effect transistors (CNTFETs). Simulation results were carried out using
HSPICE based on the CNTFET model in 32 nanometer technology in Different values
of temperature and VDD.
