  Building large, cryogenic MKID arrays requires processing highly-multiplexed,
wideband readout signals in real time; a task that has previously required
large, heavy, and power-intensive custom electronics. In this work, we present
the third-generation UVOIR MKID readout system (Gen3) which is capable of
reading out twice as many detectors with a fifth the weight and power and an
order of magnitude less volume and cost-per-pixel as compared to the previous
system. Gen3 leverages the Xilinx RFSoC4x2 platform to read out 2048, 1 MHz
MKID channels per board. The system takes a modern approach to FPGA design
using Vitis High-Level Synthesis (HLS) to specify signal processing blocks in
C/C++, Vivado ML Intelligent Design Runs (IDR) to inform implementation
stragety and close timing, and Python Productivity for ZYNQ (PYNQ) to simplify
interacting with and programming the FPGA using Python. This design suite and
tool flow allows general users to contribute to and maintain the design and
positions Gen3 to rapidly migrate to future platforms as they become available.
In this work, we describe the system requirements, design, and implementation.
We also provide performance characterization details and show that the system
achieves detector-limited resolving power in the case of few readout tones and
minimal degradation with all 2048 tones. Planned upgrades and future work are
also discussed. The Gen3 MKID readout system is fully open-source and is
expected to facilitate future array scaling to megapixel-sized formats and
increase the feasibility of deploying UVOIR MKIDs in space.
