  This work discusses the implementation of Markov Chain Monte Carlo (MCMC)
sampling from an arbitrary Gaussian mixture model (GMM) within SRAM. We show a
novel architecture of SRAM by embedding it with random number generators
(RNGs), digital-to-analog converters (DACs), and analog-to-digital converters
(ADCs) so that SRAM arrays can be used for high performance Metropolis-Hastings
(MH) algorithm-based MCMC sampling. Most of the expensive computations are
performed within the SRAM and can be parallelized for high speed sampling. Our
iterative compute flow minimizes data movement during sampling. We characterize
power-performance trade-off of our design by simulating on 45 nm CMOS
technology. For a two-dimensional, two mixture GMM, the implementation consumes
~ 91 micro-Watts power per sampling iteration and produces 500 samples in 2000
clock cycles on an average at 1 GHz clock frequency. Our study highlights
interesting insights on how low-level hardware non-idealities can affect
high-level sampling characteristics, and recommends ways to optimally operate
SRAM within area/power constraints for high performance sampling.
