  Neuromorphic architectures built with Non-Volatile Memory (NVM) can
significantly improve the energy efficiency of machine learning tasks designed
with Spiking Neural Networks (SNNs). A major source of voltage drop in a
crossbar of these architectures are the parasitic components on the crossbar's
bitlines and wordlines, which are deliberately made longer to achieve lower
cost-per-bit. We observe that the parasitic voltage drops create a significant
asymmetry in programming speed and reliability of NVM cells in a crossbar.
Specifically, NVM cells that are on shorter current paths are faster to program
but have lower endurance than those on longer current paths, and vice versa.
This asymmetry in neuromorphic architectures create reliability-performance
trade-offs, which can be exploited efficiently using SNN mapping techniques. In
this work, we demonstrate such trade-offs using a previously-proposed SNN
mapping technique with 10 workloads from contemporary machine learning tasks
for a state-of-the art neuromoorphic hardware.
