  Developing high quality GaN/dielectric interfaces is a fundamental step for
manufacturing GaN vertical power transistors. In this paper, we quantitatively
investigate the effect of planar etching treatment and trench formation on the
performance of GaN-based MOS (metal oxide semiconductor) stacks. The results
demonstrate that (i) blanket etching the GaN surface does not degrade the
robustness of the deposited dielectric layer; (ii) the addition of the trench
etch, while improving reproducibility, results in a decrease of breakdown
performance compared to the planar structures. (iii) for the trench structures,
the voltage for a 10 years lifetime is still above 20 V, indicating a good
robustness. (iv) To review the trapping performance across the
metal-dielectric-GaN stack, forward-reverse capacitance-voltage measurements
with and without stress and photo-assistance are performed. Overall, as-grown
planar capacitors devoid of prior etching steps show lowest trapping, while
trench capacitors have higher interface trapping, and bulk trapping comparable
to the blanket etched capacitors. (v) The nanostructure of the GaN/dielectric
interface was characterized by high resolution scanning transmission electron
microscopy (HR-STEM). An increased roughness of 2-3 monolayers at the GaN
surface was observed after blanket etching, which was correlated to the higher
density of interface traps. The results presented in this paper give
fundamental insight on how the etch and trench processing affects the trapping
and robustness of trench-gate GaN-MOSFETs, and provide guidance for the
optimization of device performance.
