  With the advent of high-speed, high-precision, and low-power mixed-signal
systems, there is an ever-growing demand for accurate, fast, and
energy-efficient analog-to-digital (ADCs) and digital-to-analog converters
(DACs). Unfortunately, with the downscaling of CMOS technology, modern ADCs
trade off speed, power and accuracy. Recently, memristive neuromorphic
architectures of four-bit ADC/DAC have been proposed. Such converters can be
trained in real-time using machine learning algorithms, to break through the
speedpower-accuracy trade-off while optimizing the conversion performance for
different applications. However, scaling such architectures above four bits is
challenging. This paper proposes a scalable and modular neural network ADC
architecture based on a pipeline of four-bit converters, preserving their
inherent advantages in application reconfiguration, mismatch selfcalibration,
noise tolerance, and power optimization, while approaching higher resolution
and throughput in penalty of latency. SPICE evaluation shows that an 8-bit
pipelined ADC achieves 0.18 LSB INL, 0.20 LSB DNL, 7.6 ENOB, and 0.97 fJ/conv
FOM. This work presents a significant step towards the realization of
large-scale neuromorphic data converters.
