  The controlled depletion of electrons in semiconductors is the basis for
numerous devices. Reactive-ion etching provides an effective technique for
fabricating both classical and quantum devices. However, Fermi level pinning
can occur, and must be carefully considered in the development of small
devices, such as quantum dots. Because of depletion, the electrical size of the
device is reduced in comparison with its physical dimension. To investigate
this issue, we fabricate several types of devices in silicon-germanium
heterostructures using two different etches, CF$_4$ and SF$_6$. We estimate the
depletion width associated with each etch by two methods: (i) conductance
measurements in etched wires of decreasing thickness (to determine the onset of
depletion), (ii) capacitance measurements of quantum dots (to estimate the size
of the active region). We find that the SF$_6$ etch causes a much smaller
depletion width, making it more suitable for device fabrication.
