  Disaggregation and rack-scale systems have the potential of drastically
decreasing TCO and increasing utilization of cloud datacenters, while
maintaining performance. While the concept of organising resources in separate
pools and interconnecting them together on demand is straightforward, its
materialisation can be radically different in terms of performance and scale
potential.
  In this paper, we present a memory bus bridge architecture which enables
communication between 100s of masters and slaves in todays complex
multiprocessor SoCs, that are physically intregrated in different chips and
even different mainboards. The bridge tightly couples serial transceivers and a
circuit network for chip-to-chip transfers. A key property of the proposed
bridge architecture is that it is software-defined and thus can be configured
at runtime, via a software control plane, to prepare and steer memory access
transactions to remote slaves. This is particularly important because it
enables datacenter orchestration tools to manage the disaggregated resource
allocation. Moreover, we evaluate a bridge prototype we have build for ARM AXI4
memory bus interconnect and we discuss application-level observed performance.
