  Processor design validation and debug is a difficult and complex task, which
consumes the lion's share of the design process. Design bugs that affect
processor performance rather than its functionality are especially difficult to
catch, particularly in new microarchitectures. This is because, unlike
functional bugs, the correct processor performance of new microarchitectures on
complex, long-running benchmarks is typically not deterministically known.
Thus, when performance benchmarking new microarchitectures, performance teams
may assume that the design is correct when the performance of the new
microarchitecture exceeds that of the previous generation, despite significant
performance regressions existing in the design. In this work, we present a
two-stage, machine learning-based methodology that is able to detect the
existence of performance bugs in microprocessors. Our results show that our
best technique detects 91.5% of microprocessor core performance bugs whose
average IPC impact across the studied applications is greater than 1% versus a
bug-free design with zero false positives. When evaluated on memory system
bugs, our technique achieves 100% detection with zero false positives.
Moreover, the detection is automatic, requiring very little performance
engineer time.
