  Synapse plays an important role of learning in a neural network; the learning
rules which modify the synaptic strength based on the timing difference between
the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent
Plasticity (STDP). The most commonly used rule posits weight change based on
time difference between one pre- and one post spike and is hence termed doublet
STDP (DSTDP). However, D-STDP could not reproduce results of many biological
experiments; a triplet STDP (T-STDP) that considers triplets of spikes as the
fundamental unit has been proposed recently to explain these observations. This
paper describes the compact implementation of a synapse using single
floating-gate (FG) transistor that can store a weight in a nonvolatile manner
and demonstrate the triplet STDP (T-STDP) learning rule by modifying drain
voltages according to triplets of spikes. We describe a mathematical procedure
to obtain control voltages for the FG device for T-STDP and also show
measurement results from a FG synapse fabricated in TSMC 0.35um CMOS process to
support the theory. Possible VLSI implementation of drain voltage waveform
generator circuits are also presented with simulation results.
