  Spin-Transfer Torque RAM (STTRAM) is promising for cache applications.
However, it brings new data security issues that were absent in volatile memory
counterparts such as Static RAM (SRAM) and embedded Dynamic RAM (eDRAM). This
is primarily due to the fundamental dependency of this memory technology on
ambient parameters such as magnetic field and temperature that can be exploited
to tamper with the stored data. In this paper we propose three techniques to
enable error free computation without stalling the system, (a) stalling where
the system is halted during attack; (b) cache bypass during gradually ramping
attack where the last level cache (LLC) is bypassed and the upper level caches
interact directly with the main memory; and, (c) checkpointing along with
bypass during sudden attack where the processor states are saved periodically
and the LLC is written back at regular intervals. During attack the system goes
back to the last checkpoint and the computation continues with bypassed cache.
We performed simulation for different duration and frequency of attack on
SPLASH benchmark suite and the results show an average of 8% degradation in IPC
for a one-time attack lasting for 50% of the execution time. The energy
overhead is 2% for an attack lasting for the entire duration of execution.
