  Compared to conventional general-purpose processors, accelerator-rich
architectures (ARAs) can provide orders-of-magnitude performance and energy
gains and are emerging as one of the most promising solutions in the age of
dark silicon. However, many design issues related to the complex interaction
between general-purpose cores, accelerators, customized on-chip interconnects,
and memory systems remain unclear and difficult to evaluate.
  In this paper we design and implement the ARAPrototyper to enable rapid
design space explorations for ARAs in real silicons and reduce the tedious
prototyping efforts far down to manageable efforts. First, ARAPrototyper
provides a reusable baseline prototype with a highly customizable memory
system, including interconnect between accelerators and buffers, interconnect
between buffers and last-level cache (LLC) or DRAM, coherency choice at LLC or
DRAM, and address translation support. Second, ARAPrototyper provides a clean
interface to quickly integrate users' own accelerators written in high-level
synthesis (HLS) code. The whole design flow is highly automated to generate a
prototype of ARA on an FPGA system-on-chip (SoC). Third, to quickly develop
applications that run seamlessly on the ARA prototype, ARAPrototyper provides a
system software stack, abstracts the accelerators as software libraries, and
provides APIs for software developers. Our experimental results demonstrate
that ARAPrototyper enables a wide range of design space explorations for ARAs
at manageable prototyping efforts, which has 4,000X to 10,000X faster
evaluation time than full-system simulations. We believe that ARAPrototyper can
be an attractive alternative for ARA design and evaluation.
