  This paper shows how the input offset of sampling flip-flops in the Alexander
phase detector affects the jitter transfer from data to the recovered clock in
a clock data recovery circuit. The Alexander phase detector samples the data at
both the edges of the clock in order to recover the data, as well as the clock
timing information. The timing information is used in a clock recovery circuit,
which is basically a PLL or a DLL. Once the PLL (or DLL) is locked, the phase
detector samples the data at the center of the eye as well as at the data
transitions. It is shown how the offset of the sampling flip-flop that samples
the data at its transitions influences the jitter transfer from data to the
recovered clock. Importantly, it is shown that zero offset is not always the
best case. The effect is studied for different levels of data dependent jitter.
The mechanism of this phenomenon is explained and the predictions are supported
with simulations. The paper also discusses a tracking circuit that keeps the
offset at the minimum jitter point.
