  Processing-in-memory (PIM) architectures have demonstrated great potential in
accelerating numerous deep learning tasks. Particularly, resistive
random-access memory (RRAM) devices provide a promising hardware substrate to
build PIM accelerators due to their abilities to realize efficient in-situ
vector-matrix multiplications (VMMs). However, existing PIM accelerators suffer
from frequent and energy-intensive analog-to-digital (A/D) conversions,
severely limiting their performance. This paper presents a new PIM architecture
to efficiently accelerate deep learning tasks by minimizing the required A/D
conversions with analog accumulation and neural approximated peripheral
circuits. We first characterize the different dataflows employed by existing
PIM accelerators, based on which a new dataflow is proposed to remarkably
reduce the required A/D conversions for VMMs by extending shift and add (S+A)
operations into the analog domain before the final quantizations. We then
leverage a neural approximation method to design both analog accumulation
circuits (S+A) and quantization circuits (ADCs) with RRAM crossbar arrays in a
highly-efficient manner. Finally, we apply them to build an RRAM-based PIM
accelerator (i.e., \textbf{Neural-PIM}) upon the proposed analog dataflow and
evaluate its system-level performance. Evaluations on different benchmarks
demonstrate that Neural-PIM can improve energy efficiency by 5.36x (1.73x) and
speed up throughput by 3.43x (1.59x) without losing accuracy, compared to the
state-of-the-art RRAM-based PIM accelerators, i.e., ISAAC (CASCADE).
