  The Vienna Architecture Description Language (VADL) is a powerful processor
description language (PDL) that enables the concise formal specification of
processor architectures. By utilizing a single VADL processor specification,
the VADL system exhibits the capability to automatically generate a range of
artifacts necessary for rapid design space exploration. These include
assemblers, compilers, linkers, functional instruction set simulators,
cycle-accurate instruction set simulators, synthesizable specifications in a
hardware description language, as well as test cases and documentation. One
distinctive feature of VADL lies in its separation of the instruction set
architecture (ISA) specification and the microarchitecture (MiA) specification.
This segregation allows users the flexibility to combine various ISAs with
different MiAs, providing a versatile approach to processor design. In contrast
to existing PDLs, VADL's MiA specification operates at a higher level of
abstraction, enhancing the clarity and simplicity of the design process.
Notably, with a single ISA specification, VADL streamlines compiler generation
and maintenance by eliminating the need for intricate compiler-specific
knowledge. This article introduces VADL, describes the generator techniques in
detail and demonstrates the power of the language and the performance of the
generators in an empirical evaluation. The evaluation shows the expressiveness
and conciseness of VADL and the efficiency of the generated artifacts.
