  Two-dimensional Fourier transform plays a significant role in a variety of
image processing problems, such as medical image processing, digital
holography, correlation pattern recognition, hybrid digital optical processing,
optical computing etc. 2D spatial Fourier transformation involves large number
of image samples and hence it requires huge hardware resources of field
programmable gate arrays (FPGA). In this paper, we present an area efficient
architecture of 2D FFT processor that reuses the butterfly units multiple
times. This is achieved by using a control unit that sends back the previous
computed data of N/2 butterfly units to itself for {log_2(N) - 1} times. A RAM
controller is used to synchronize the flow of data samples between the
functional blocks.The 2D FFT processor is simulated by VHDL and the results are
verified on a Virtex-6 FPGA. The proposed method outperforms the conventional
NxN point 2D FFT in terms of area which is reduced by a factor of log_N(2) with
negligible increase in computation time.
