  We present results of an R&D study for a specialized processor capable of
precisely reconstructing, in pixel detectors, hundreds of charged-particle
tracks from high-energy collisions at 40 MHz rate. We apply a highly parallel
pattern-recognition algorithm, inspired by studies of the processing of visual
images by the brain as it happens in nature, and describe in detail an
efficient hardware implementation in high-speed, high-bandwidth FPGA devices.
This is the first detailed demonstration of reconstruction of offline-quality
tracks at 40 MHz and makes the device suitable for processing Large Hadron
Collider events at the full crossing frequency.
