  The risk of soft errors due to radiation continues to be a significant
challenge for engineers trying to build systems that can handle harsh
environments. Building systems that are Radiation Hardened by Design (RHBD) is
the preferred approach, but existing techniques are expensive in terms of
performance, power, and/or area. This paper introduces a novel soft-error
resilient asynchronous bundled-data design template, SERAD, which uses a
combination of temporal and spatial redundancy to mitigate Single Event
Transients (SETs) and upsets (SEUs). SERAD uses Error Detecting Logic (EDL) to
detect SETs at the inputs of sequential elements and correct them via
re-sampling. Because SERAD only pays the delay penalty in the presence of an
SET, which rarely occurs, its average performance is comparable to the baseline
synchronous design. We tested the SERAD design using a combination of Spice and
Verilog simulations and evaluated its impact on area, frequency, and power on
an open-core MIPS-like processor using a NCSU 45nm cell library. Our
post-synthesis results show that the SERAD design consumes less than half of
the area of the Triple Modular Redundancy (TMR), exhibits significantly less
performance degradation than Glitch Filtering (GF), and consumes no more total
power than the baseline unhardened design.
