  With the current increase in the data produced by the Large Hadron Collider
(LHC) at CERN, it becomes important to process this data in a corresponding
manner. To begin with, to efficiently select events that contain relevant
information from a massive flow of data. This is the task of the tau lepton
decay triggering algorithm. The implementation is based on the High-Level
Synthesis (HLS) approach that allows generating a hardware description of the
design from the algorithm written in a high-level programming language like
C++. HLS tools are intended to decrease the time and complexity of hardware
design development, however, their capabilities are limited. The development of
an efficient application requires substantial knowledge of the hardware design
and HLS specifics. This paper presents the optimizations introduced to the
algorithm that improved latency and area and more importantly solved the
problems with the routing, making it possible to implement the algorithm on the
FPGA fabric.
