  Two-dimensional (2D) van der Waals semiconductors are appealing for low-power
transistors. Here, we show the feasibility in enhancing carrier mobility in 2D
semiconductors through engineering the vertical distribution of carriers
confined inside the ultrathin channels via symmetrizing gate configuration or
increasing channel thickness. Through self-consistently solving the
Schr\"odinger-Poisson equations, the shapes of electron envelope functions are
extensively investigated by clarifying their relationship with gate
configuration, channel thickness, dielectric permittivity, and electron
density. The impacts of electron distribution variation on various carrier
scattering matrix elements and overall carrier mobility are insightfully
clarified. It is found that the carrier mobility can be generally enhanced in
the dual-gated configuration due to the centralization of carrier
redistribution in the nanometer-thick semiconductor channels and the rate of
increase reaches up to 23% in HfO$_2$ dual-gated 10-layer MoS$_2$ channels.
This finding represents a viable strategy for performance optimization in
transistors consisting of 2D semiconductors.
