  Due to their capacity-achieving property, polar codes have become one of the
most attractive channel codes. To date, the successive cancellation list (SCL)
decoding algorithm is the primary approach that can guarantee outstanding
error-correcting performance of polar codes. However, the hardware designs of
the original SCL decoder have large silicon area and long decoding latency.
Although some recent efforts can reduce either the area or latency of SCL
decoders, these two metrics still cannot be optimized at the same time. This
paper, for the first time, proposes a general log-likelihood-ratio (LLR)-based
SCL decoding algorithm with multi-bit decision. This new algorithm, referred as
LLR-2Kb-SCL, can determine 2K bits simultaneously for arbitrary K with the use
of LLR messages. In addition, a reduced-data-width scheme is presented to
reduce the critical path of the sorting block. Then, based on the proposed
algorithm, a VLSI architecture of the new SCL decoder is developed. Synthesis
results show that for an example (1024, 512) polar code with list size 4, the
proposed LLR-2Kb-SCL decoders achieve significant reduction in both area and
latency as compared to prior works. As a result, the hardware efficiency of the
proposed designs with K=2 and 3 are 2.33 times and 3.32 times of that of the
state-of-the-art works, respectively.
