  We investigate the low temperature transport in 8 nm diameter Si junctionless
nanowire field effect transistors fabricated by top down techniques with a
wrap-around gate and two different activated doping densities. First we extract
the intrinsic gate capacitance of the device geometry from a device that shows
Coulomb blockade at 13 mK with over 500 Coulomb peaks across a gate voltage
range of 6 V indicating the formation of a single island in the entire nanowire
channel. In two other devices, doped Si:P $4\times10^{19}\,\text{cm}^{-3}$ and
$2\times10^{20}\,\text{cm}^{-3}$, we observe quantum interference and use the
extracted gate coupling to determine the dominant energy scale and the
corresponding mean-free paths. For the higher doped device the analysis yields
a mean free path of $4\pm2\,\text{nm}$, which is on the order of the average
dopant spacing and suggests scattering on unactivated or activated dopants. For
the device with an activated dopant density of $4\times10^{19}\,\text{cm}^{-3}$
the quantum interference effects suggest a mean free path of
$10\pm2\,\text{nm}$, which is comparable to the nanowire width, and thus
quasi-ballistic transport. A temperature dependent analysis of Universal
Conductance Fluctuations suggests a coherence length above the nanowire length
for temperatures below 1.9 K and decoherence from 1D electron-electron
interactions for higher temperatures. The mobility is limited by scattering on
impurities rather than the expected surface roughness scattering for nanowires
with diameters larger or comparable to the Fermi wavelength. Our measurements
therefore provide insight into the performance limitations from dominant
scattering and dephasing mechanisms in technologically relevant silicon device
geometries.
