  This paper presents a design for test (DFT)architecture for fast and scalable
testing of array multipliers (MULTs). Regardless of the MULT size, our proposed
testable architecture, without major changes in the original architecture,
requires only five test vectors. Test pattern generation (TPG) is done by
combining C-testability, bijectivity and deterministic TPG methods.
Experimental results show 100% fault coverage for single stuck-at faults. The
proposed method requires minor testability hardware insertion into the
multiplier with extra delay and area overhead of less than 0.5% for a 64-bit
multiplier.
