  Spiking neural networks (SNNs) have gained attention in recent years due to
their ability to handle sparse and event-based data better than regular
artificial neural networks (ANNs). Since the structure of SNNs is less suited
for typically used accelerators such as GPUs than conventional ANNs, there is a
demand for custom hardware accelerators for processing SNNs. In the past, the
main focus was on platforms that resemble the structure of multiprocessor
systems. In this work, we propose a lightweight neuron layer architecture that
allows network structures to be directly mapped onto digital hardware. Our
approach is based on differential time coding of spike sequences and the
decoupling of processing time and spike timing that allows the SNN to be
processed on different hardware platforms. We present synthesis and performance
results showing that this architecture can be implemented for networks of more
than 1000 neurons with high clock speeds on a State-of-the-Art FPGA. We
furthermore show results on the robustness of our approach to quantization.
These results demonstrate that high-accuracy inference can be performed with
bit widths as low as 4.
