  Crossbar arrays of resistive memories (RRAM) hold the promise of enabling
In-Memory Computing (IMC), but essential challenges due to the impact of device
imperfection and device endurance have yet to be overcome. In this work, we
demonstrate experimentally an RRAM-based IMC logic concept with strong
resilience to RRAM variability, even after one million endurance cycles. Our
work relies on a generalization of the concept of in-memory Scouting Logic, and
we demonstrate it experimentally with up to 16 parallel devices (operands), a
new milestone for RRAM in-memory logic. Moreover, we combine IMC with
Multi-Level-Cell programming and demonstrate experimentally, for the first
time, an IMC RRAM-based MLC 2-bit adder.
