  A chiplet is an integrated circuit that encompasses a well-defined subset of
an overall system's functionality. In contrast to traditional monolithic
system-on-chips (SoCs), chiplet-based architecture can reduce costs and
increase reusability, representing a promising avenue for continuing Moore's
Law. Despite the advantages of multi-chiplet architectures, floorplan design in
a chiplet-based architecture has received limited attention. Conflicts between
cost and performance necessitate a trade-off in chiplet floorplan design since
additional latency introduced by advanced packaging can decrease performance.
Consequently, balancing power, performance, cost, area, and reliability is of
paramount importance. To address this challenge, we propose Floorplet, a
framework comprising simulation tools for performance reporting and
comprehensive models for cost and reliability optimization. Our framework
employs the open-source Gem5 simulator to establish the relationship between
performance and floorplan for the first time, guiding the floorplan
optimization of multi-chiplet architecture. The experimental results show that
our framework decreases inter-chiplet communication costs by 24.81%.
