  Numerous threats are associated with the globalized integrated circuit (IC)
supply chain, such as piracy, reverse engineering, overproduction, and
malicious logic insertion. Many obfuscation approaches have been proposed to
mitigate these threats by preventing an adversary from fully understanding the
IC (or parts of it). The use of reconfigurable elements inside an IC is a known
obfuscation technique, either as a coarse grain reconfigurable block (i.e.,
eFPGA) or as a fine grain element (i.e., FPGA-like look-up tables). This paper
presents a security-aware CAD flow that is LUT-based yet still compatible with
the standard cell based physical synthesis flow. More precisely, our CAD flow
explores the FPGA-ASIC design space and produces heavily obfuscated designs
where only small portions of the logic resemble an ASIC. Therefore, we term
this specialized solution an "embedded ASIC" (eASIC). Nevertheless, even for
heavily LUT-dominated designs, our proposed decomposition and pin swapping
algorithms allow for performance gains that enable performance levels that only
ASICs would otherwise achieve. On the security side, we have developed novel
template-based attacks and also applied existing attacks, both oracle-free and
oracle-based. Our security analysis revealed that the obfuscation rate for an
SHA-256 study case should be at least 45% for withstanding traditional attacks
and at least 80% for withstanding template-based attacks. When the 80\%
obfuscated SHA-256 design is physically implemented, it achieves a remarkable
frequency of 368MHz in a 65nm commercial technology, whereas its FPGA
implementation (in a superior technology) achieves only 77MHz.
