  Stream computation is one of the approaches suitable for FPGA-based custom
computing due to its high throughput capability brought by pipelining with
regular memory access. To increase performance of iterative stream computation,
we can exploit both temporal and spatial parallelism by deepening and
duplicating pipelines, respectively. However, the performance is constrained by
several factors including available hardware resources on FPGA, an external
memory bandwidth, and utilization of pipeline stages, and therefore we need to
find the best mix of the different parallelism to achieve the highest
performance per power. In this paper, we present a domain-specific language
(DSL) based design space exploration for temporally and/or spatially parallel
stream computation with FPGA. We define a DSL where we can easily design a
hierarchical structure of parallel stream computation with abstract description
of computation. For iterative stream computation of fluid dynamics simulation,
we design hardware structures with a different mix of the temporal and spatial
parallelism. By measuring the performance and the power consumption, we find
the best among them.
