  Quantum error correction (QEC) codes can tolerate hardware errors by encoding
fault-tolerant logical qubits using redundant physical qubits and detecting
errors using parity checks. Leakage errors occur in quantum systems when a
qubit leaves its computational basis and enters higher energy states. These
errors severely limit the performance of QEC due to two reasons. First, they
lead to erroneous parity checks that obfuscate the accurate detection of
errors. Second, the leakage spreads to other qubits and creates a pathway for
more errors over time. Prior works tolerate leakage errors by using leakage
reduction circuits (LRCs) that modify the parity check circuitry of QEC codes.
Unfortunately, naively using LRCs always throughout a program is sub-optimal
because LRCs incur additional two-qubit operations that (1) facilitate leakage
transport, and (2) serve as new sources of errors. Ideally, LRCs should only be
used if leakage occurs, so that errors from both leakage as well as additional
LRC operations are simultaneously minimized. However, identifying leakage
errors in real-time is challenging. To enable the robust and efficient usage of
LRCs, we propose ERASER that speculates the subset of qubits that may have
leaked and only uses LRCs for those qubits. Our studies show that the majority
of leakage errors typically impact the parity checks. We leverage this insight
to identify the leaked qubits by analyzing the patterns in the failed parity
checks. We propose ERASER+M that enhances ERASER by detecting leakage more
accurately using qubit measurement protocols that can classify qubits into
$|0\rangle, |1\rangle$ and $|L\rangle$ states. ERASER and ERASER+M improve the
logical error rate by up to $4.3\times$ and $23\times$ respectively compared to
always using LRC.
