  Multiplication is indispensable and is one of the core operations in many
modern applications including signal processing and neural networks.
Conventional right-to-left (RL) multiplier extensively contributes to the power
consumption, area utilization and critical path delay in such applications.
This paper proposes a low latency multiplier based on online or left-to-right
(LR) arithmetic which can increase throughput and reduce latency by digit-level
pipelining. Online arithmetic enables overlapping successive operations
regardless of data dependency because of the most significant digit first mode
of operation. To produce most significant digit first, it uses redundant number
system and we can have a carry-free addition, therefore, the delay of the
arithmetic operation is independent of operand bit width. The operations are
performed digit by digit serially from left to right which allows gradual
increase in the slice activities making it suitable for implementation on
reconfigurable devices. Serial nature of the online algorithm and gradual
increment/decrement of active slices minimize the interconnects and signal
activities resulting in overall reduction of area and power consumption. We
present online multipliers with; both inputs in serial, and one in serial and
one in parallel. Pipelined and non-pipelined designs of the proposed
multipliers have been synthesized with GSCL 45nm technology on Synopsys Design
Compiler. Thorough comparative analysis has been performed using widely used
performance metrics. The results show that the proposed online multipliers
outperform the RL multipliers.
