  Every CPU carries one or more arithmetical and logical units. One popular
operation that is performed by these units is multiplication. Automatic
generation of custom VHDL models for performing this operation, allows the
designer to achieve a time efficient design space exploration. Although these
units are heavily utilized in modern digital circuits and DSP, there is no
tool, accessible from the web, to generate the HDL description of such designs
for arbitrary and different input bitwidths. In this paper, we present our web
accessible tool to construct completely custom optimized multiplication units
together with random generated test vectors for their verification. Our novel
tool is one of the firsts web based EDA tools to automate the design of such
units and simultaneously provide custom testbenches to verify their
correctness. Our synthesized circuits on Xilinx Virtex 6 FPGA, operate up to
589 Mhz.
