  Over the past decade, polar codes have received significant traction and have
been selected as the coding method for the control channel in fifth-generation
(5G) wireless communication systems. However, conventional polar codes are
reliant solely on binary (2x2) kernels, which restricts their block length to
being only powers of 2. In response, multi-kernel (MK) polar codes have been
proposed as a viable solution to attain greater code length flexibility. This
paper proposes an unrolled architecture for encoding both systematic and
non-systematic MK polar codes, capable of high-throughput encoding of codes
constructed with binary, ternary (3x3), or binary-ternary mixed kernels. The
proposed scheme exhibits an unprecedented level of flexibility by supporting 83
different codes and offering various architectures that provide trade-offs
between throughput and resource consumption. The FPGA implementation results
demonstrate that a partially-pipelined polar encoder of size N=4096 operating
at a frequency of 270 MHz gives a throughput of 1080 Gbps. Additionally, a new
compiler implemented in Python is given to automatically generate HDL modules
for the desired encoders. By inserting the desired parameters, a designer can
simply obtain all the necessary VHDL files for FPGA implementation.
