  The algorithms used in wireless applications are increasingly more
sophisticated and consequently more challenging to implement in hardware.
Traditional design flows require developing the micro architecture, coding the
RTL, and verifying the generated RTL against the original functional C or
MATLAB specification. This paper describes a C-based design flow that is well
suited for the hardware implementation of DSP algorithms commonly found in
wireless applications. The C design flow relies on guided synthesis to generate
the RTL directly from the untimed C algorithm. The specifics of the C-based
design flow are described using a simple DSP filtering algorithm consisting of
a forward adaptive equalizer, a 64-QAM slicer and an adaptive decision feedback
equalizer. The example illustrates some of the capabilities and advantages
offered by this flow.
