  The problem of finding the solution of Partial Differential Equations (PDEs)
plays a central role in modeling real world problems. Over the past years,
Multigrid solvers have showed their robustness over other techniques, due to
its high convergence rate which is independent of the problem size. For this
reason, many attempts for exploiting the inherent parallelism of Multigrid have
been made to achieve the desired efficiency and scalability of the method. Yet,
most efforts fail in this respect due to many factors (time, resources)
governed by software implementations. In this paper, we present a hardware
implementation of the V-cycle Multigrid method for finding the solution of a
2D-Poisson equation. We use Handel-C to implement our hardware design, which we
map onto available Field Programmable Gate Arrays (FPGAs). We analyze the
implementation performance using the FPGA vendor's tools. We demonstrate the
robustness of Multigrid over other iterative solvers, such as Jacobi and
Successive Over Relaxation (SOR), in both hardware and software. We compare our
findings with a C++ version of each algorithm. The obtained results show better
performance when compared to existing software versions.
