  Compute Express Link (CXL) is a rapidly emerging coherent interconnect
standard that provides opportunities for memory pooling and sharing. Memory
sharing is a well-established software feature that improves memory utilization
by avoiding unnecessary data movement. In this paper, we discuss multiple
approaches to enable memory sharing with different generations of CXL protocol
(i.e., CXL 2.0 and CXL 3.0) considering the challenges with each of the
architectures from the device hardware and software viewpoint.
