  Memcomputing is a novel computing paradigm beyond the von-Neumann one. Its
digital version is designed for the efficient solution of combinatorial
optimization problems, which emerge in various fields of science and
technology. Previously, the performance of digital memcomputing machines (DMMs)
was demonstrated using software simulations of their ordinary differential
equations. Here, we present the first hardware realization of a DMM algorithm
on a low-cost FPGA board. In this demonstration, we have implemented a Boolean
satisfiability problem solver. To optimize the use of hardware resources, the
algorithm was partially parallelized. The scalability of the present
implementation is explored and our FPGA-based results are compared to those
obtained using a python code running on a traditional (von-Neumann) computer,
showing one to two orders of magnitude speed-up in time to solution. This
initial small-scale implementation is projected to state-of-the-art FPGA boards
anticipating further advantages of the hardware realization of DMMs over their
software emulation.
