  A novel planar device having doped silicon regions (tubs) under the source
and drain of an FDSOI MOSFET is reported at 20 nm gate length. The doped
silicon regions result in formation of potential wells (PW) in the source and
drain regions of FDSOI MOSFET and thus, the device being called as Potential
Well Based FDSOI MOSFET (PWFDSOI MOSFET). Simulation and device physics study
on PWFDSOI MOSFET showed reduction in the OFF current of the device by orders
of magnitude. A low IOF F of 22 pA/um, high ION /IOF F ratio of 1.5 x 107 and
subthreshold swing of 76 mV/decade were achieved in 20 nm gate length PWFDSOI
MOSFET. The study was performed on devices with unstrained silicon channel.
