  The increasing demand of dedicated accelerators to improve energy efficiency
and performance has highlighted FPGAs as a promising option to deliver both.
However, programming FPGAs in hardware description languages requires long time
and effort to achieve optimal results, which discourages many programmers from
adopting this technology.
  High Level Synthesis tools improve the accessibility to FPGAs, but the
optimization process is still time expensive due to the large compilation time,
between minutes and days, required to generate a single bitstream. Whereas
placing and routing take most of this time, the RTL pipeline and memory
organization are known in seconds. This early information about the
organization of the upcoming bitstream is enough to provide an accurate and
fast performance model.
  This paper presents a performance analytical model for HLS designs focused on
memory bound applications. With a careful analysis of the generated memory
architecture and DRAM organization, the model predicts the execution time with
a maximum error of 9.2% for a set of representative applications. Compared with
previous works, our predictions reduce on average at least $2\times$ the
estimation error.
