At the time this chip was designed, people used as few transistors as possible in the CPU, to make them small enough to fit on the available chips.
I suspect that practically every "register" (both programmer-visible instruction-set registers and also internal microarchitecture latches) in a CPU of that era stored data in a transparent gated D latch or something similar.
Nowadays, there's plenty of transistors on a chip, so it's simpler to use full master-slave D flip-flops, even though they use twice as many transistors.
Many instructions take data from some register A, combine it with some other data with the ALU, and store the result back in register A.
That is pretty easy to do if register A is implemented with a full master-slave D flip-flop.
But if register A is a transparent gated D latch, you need non-overlapping clocks.
You use a pulse on one clock to store some intermediate result somewhere (while register A holds its output constant), and then a pulse on another clock to load register A with the new value (while the intermediate register holds its output constant).
This requires a 2-phase clock.
The easiest way to make a non-overlapping 2-phase clock (in those days when transistors were scarce) was a little external circuit that takes an input clock and divides it by two.
As time went on, people figured out how to pack more and more transistors onto an IC.
So people designing CPUs integrated more and more of the stuff around the CPU in a full computer system onto the CPU chip.
Reading between the lines of the Wikipedia clock signal article,
I get the impression that the people who designed the 8085 and the 6502 and other chips of that era had just a little more room than the previous generation of integrated CPUs,
and they decided the best use of that room was to put that little external circuit on-chip.
But they kept all the registers the same gated D latch as before.
So that's why the clock frequency is divided by two. You can think of the first external clock pulse generating a pulse on the phase_one internal clock signal to update that intermediate result register, and the second pulse from the external clock generating a pulse on the phase_two internal clock signal to update the programmer-visible register.