Scientists at the U.S. Department of Energy's National Renewable Energy Laboratory (NREL) have developed an instrument that puts pressure on the wafers to find which ones are too fragile to make it through the manufacturing process — and then kicks out those weak wafers before they go through their costly enhancement. NREL's Silicon Photovoltaic Wafer Screening System (SPWSS) is a cube-shaped furnace about 15 inches each side, and can be retrofitted into an assembly line.
The process looks a lot like the toasting belt that turns a cold sub sandwich into a warm one. As each wafer passes through a narrow — 15-millimeter — high-intensity illumination zone, different strips of the wafer are exposed to the heat. That way, the stress travels through the wafer.
The temperature can be calibrated precisely — most usefully by correlating it to the thickness of the wafer, because the thinner the wafer, the less stress it can withstand. Every manufacturer has different levels at which their wafers can break from stress, so the SPWSS can be calibrated precisely via computer to meet the needs of each solar cell maker.
The SPWSS is essentially a furnace shaped like a trapezoidal prism to narrow the focus of the light and increase its intensity. The ceramic sides of the furnace reflect the light to the intensity zone and ensure that almost no energy is wasted.
The lamps can be as hot as 1,800 degrees Celsius, but the hottest part of the wafer will feel about 500 degrees Celsius on its surface.
It's the rapid increase in thermal energy — made possible by the geometry of the furnace and its highly reflective surfaces — that causes the stress. While one 15-millimeter strip of the wafer is feeling 500 degrees Celsius of stress, the strip adjacent to it feels much cooler. The hot strip wants to expand, but the cool strip doesn't want any part of that. It's these competing forces that cause the stress.
The micro-cracks or breaks that occasionally develop from the thermal stress mirror the stress that will happen to weak wafers as they go through the assembly process. The difference is that the thermal testing happens first, before the expensive coatings and layers are added to the wafers.
This story is reprinted from material from NREL, with editorial changes made by Materials Today. The views expressed in this article do not necessarily represent those of Elsevier. Link to original source.